OpenTitan Introduction
1.
Introduction
❱
1.1.
Product Architecture
1.2.
Use Cases
❱
1.2.1.
Platform Integrity Module
1.2.2.
Trusted Platform Module
1.2.3.
Universal 2nd-Factor Security Key
1.3.
OpenTitan updates - RFCs
2.
Glossary
3.
Update this documentation
OpenTitan Contributions
4.
Getting Started
❱
4.1.
Workflows
4.2.
Design Verification
4.3.
Formal Verification
4.4.
Building (and Testing) Software
4.5.
Building Documentation
4.6.
Using OpenOCD
4.7.
Tools Setup
4.8.
FPGA Setup
4.9.
Verilator Setup
4.10.
Installing Vivado
4.11.
Unofficial Guides
4.12.
RedHat/Fedora
5.
Contributing
❱
5.1.
Detailed Contribution Guide
5.2.
Directory Structure
5.3.
Contributing to Documentation
❱
5.3.1.
An Example IP Block's Documentation
5.4.
Continuous Integration
5.5.
Top-Level Design and Targets
5.6.
GitHub Notes
5.7.
Bazel Notes
5.8.
Using the Container
5.9.
Contributing to Hardware
5.10.
Comportability
5.11.
RACL
5.12.
Hardware Design
5.13.
Design Methodology
5.14.
Vendoring in Hardware
5.15.
Linting
5.16.
Synthesis Flow
5.17.
Contributing to Verification
5.18.
Verification Methodology
5.19.
Security Countermeasure Verification Framework
5.20.
Assertions
5.21.
Contributing to Software
5.22.
Device Interface Functions
5.23.
Committers
5.24.
RFC Process
6.
Contributor Guides
❱
6.1.
HJSON
6.2.
Python
6.3.
C & C++
6.4.
Markdown
6.5.
RISC-V Assembly
6.6.
OTBN Assembly
6.7.
Guidance for Volatile
6.8.
Developing on an FPGA
6.9.
Get a Board
6.10.
FPGA Reference Manual
6.11.
Debugging with an ILA
6.12.
Generalized Priority Definitions
6.13.
Generalized Project Milestone Definitions
6.14.
Hardware Development Stages
6.15.
Signoff Checklist
6.16.
Rust for Embedded C Programmers
OpenTitan Hardware
7.
Introduction
8.
Earl Grey Top-Level Design
❱
8.1.
Datasheet
8.2.
Memory Map
8.3.
Design
8.4.
Pinout / Pinmux Tables
❱
8.4.1.
ASIC
8.4.2.
CW340
8.5.
Design Verification
❱
8.5.1.
Chip Testplan
8.6.
Alert Handler
❱
8.6.1.
Theory of Operation
8.6.2.
Design Verification
❱
8.6.2.1.
Testplan
8.6.3.
Programmer's Guide
8.6.4.
Interface and Registers
8.6.5.
Device Interface Functions
8.6.6.
Checklist
8.7.
Analog Sensor Top
❱
8.7.1.
Interfaces
8.8.
Clock Manager
❱
8.8.1.
Theory of Operation
8.8.2.
Design Verification
❱
8.8.2.1.
Testplan
8.8.3.
Programmer's Guide
8.8.4.
Hardware Interfaces
8.8.5.
Registers
8.8.6.
Device Interface Functions
8.8.7.
Checklist
8.9.
Flash Controller
❱
8.9.1.
Theory of Operation
8.9.2.
Design Verification
❱
8.9.2.1.
Testplan
8.9.3.
Programmer's Guide
8.9.4.
Hardware Interfaces
8.9.5.
Registers
8.9.6.
Device Interface Functions
8.9.7.
Checklist
8.10.
GPIO
❱
8.10.1.
Theory of Operation
8.10.2.
Design Verification
❱
8.10.2.1.
Testplan
8.10.3.
Programmer's Guide
8.10.4.
Hardware Interfaces
8.10.5.
Registers
8.10.6.
Device Interface Functions
8.10.7.
Checklist
8.11.
Ibex RISC-V Core Wrapper
❱
8.11.1.
Theory of Operation
8.11.2.
Boot, ROM execution and Patching
8.11.3.
Design Verification
8.11.4.
Programmer's Guide
8.11.5.
Hardware Interfaces
8.11.6.
Registers
8.11.7.
Checklist
8.12.
Interrupt Controller
❱
8.12.1.
Theory of Operation
8.12.2.
Design Verification
❱
8.12.2.1.
Testplan
8.12.3.
Programmer's Guide
8.12.4.
Interface and Registers
8.12.5.
Device Interface Functions
8.12.6.
Checklist
8.13.
OTP Controller
❱
8.13.1.
Theory of Operation
8.13.2.
Design Verification
❱
8.13.2.1.
Testplan
8.13.3.
Programmer's Guide
8.13.4.
Hardware Interfaces
8.13.5.
Registers
8.13.6.
Device Interface Functions
8.13.7.
Checklist
8.14.
Pinmux
❱
8.14.1.
Theory of Operation
8.14.2.
Design Verification
❱
8.14.2.1.
Testplan
8.14.3.
Programmer's Guide
8.14.4.
Hardware Interfaces
8.14.5.
Registers
8.14.6.
Device Interface Functions
8.14.7.
Checklist
8.15.
Power Management
❱
8.15.1.
Theory of Operation
8.15.2.
Design Verification
❱
8.15.2.1.
Testplan
8.15.3.
Programmer's Guide
8.15.4.
Hardware Interfaces
8.15.5.
Registers
8.15.6.
Device Interface Functions
8.15.7.
Checklist
8.16.
Reset Manager
❱
8.16.1.
Theory of Operation
8.16.2.
Design Verification
❱
8.16.2.1.
Testplan
8.16.3.
Programmer's Guide
8.16.4.
Hardware Interfaces
8.16.5.
Registers
8.16.6.
Device Interface Functions
8.16.7.
Checklist
8.17.
Sensor Control
❱
8.17.1.
Theory of Operation
8.17.2.
Programmer's Guide
8.17.3.
Hardware Interfaces
8.17.4.
Registers
8.17.5.
Device Interface Functions
8.17.6.
Checklist
8.18.
TL-UL Checklist
9.
Darjeeling Top-Level Design
❱
9.1.
Datasheet
9.2.
Memory Map
9.3.
Pinout / Pinmux Tables
❱
9.3.1.
ASIC
9.4.
AC Range Check
❱
9.4.1.
Theory of Operation
9.4.2.
Design Verification
❱
9.4.2.1.
Testplan
9.4.3.
Hardware Interfaces
9.4.4.
Registers
9.4.5.
Checklist
9.5.
Alert Handler
❱
9.5.1.
Theory of Operation
9.5.2.
Design Verification
❱
9.5.2.1.
Testplan
9.5.3.
Programmer's Guide
9.5.4.
Interface and Registers
9.5.5.
Device Interface Functions
9.5.6.
Checklist
9.6.
Clock Manager
❱
9.6.1.
Theory of Operation
9.6.2.
Design Verification
❱
9.6.2.1.
Testplan
9.6.3.
Programmer's Guide
9.6.4.
Hardware Interfaces
9.6.5.
Registers
9.6.6.
Device Interface Functions
9.6.7.
Checklist
9.7.
GPIO
❱
9.7.1.
Theory of Operation
9.7.2.
Design Verification
❱
9.7.2.1.
Testplan
9.7.3.
Programmer's Guide
9.7.4.
Hardware Interfaces
9.7.5.
Registers
9.7.6.
Device Interface Functions
9.7.7.
Checklist
9.8.
Ibex RISC-V Core Wrapper
❱
9.8.1.
Theory of Operation
9.8.2.
Boot, ROM execution and Patching
9.8.3.
Design Verification
9.8.4.
Programmer's Guide
9.8.5.
Hardware Interfaces
9.8.6.
Registers
9.8.7.
Checklist
9.9.
Interrupt Controller
❱
9.9.1.
Theory of Operation
9.9.2.
Design Verification
❱
9.9.2.1.
Testplan
9.9.3.
Programmer's Guide
9.9.4.
Interface and Registers
9.9.5.
Device Interface Functions
9.10.
OTP Controller
❱
9.10.1.
Theory of Operation
9.10.2.
Design Verification
❱
9.10.2.1.
Testplan
9.10.3.
Programmer's Guide
9.10.4.
Hardware Interfaces
9.10.5.
Registers
9.10.6.
Device Interface Functions
9.10.7.
Checklist
9.11.
Pinmux
❱
9.11.1.
Theory of Operation
9.11.2.
Design Verification
❱
9.11.2.1.
Testplan
9.11.3.
Programmer's Guide
9.11.4.
Hardware Interfaces
9.11.5.
Registers
9.11.6.
Device Interface Functions
9.11.7.
Checklist
9.12.
Power Management
❱
9.12.1.
Theory of Operation
9.12.2.
Design Verification
❱
9.12.2.1.
Testplan
9.12.3.
Programmer's Guide
9.12.4.
Hardware Interfaces
9.12.5.
Registers
9.12.6.
Device Interface Functions
9.12.7.
Checklist
9.13.
RACL Control
❱
9.13.1.
RACL Configuration
9.13.2.
Hardware Interfaces
9.13.3.
Registers
9.14.
Reset Manager
❱
9.14.1.
Theory of Operation
9.14.2.
Design Verification
❱
9.14.2.1.
Testplan
9.14.3.
Programmer's Guide
9.14.4.
Hardware Interfaces
9.14.5.
Registers
9.14.6.
Device Interface Functions
9.14.7.
Checklist
10.
Cores
❱
10.1.
Ibex RISC-V Core Wrapper
❱
10.1.1.
Theory of Operation
10.1.2.
Boot, ROM execution and Patching
10.1.3.
Design Verification
10.1.4.
Programmer's Guide
10.1.5.
Hardware Interfaces
10.1.6.
Registers
10.1.7.
Checklist
10.2.
OTBN
❱
10.2.1.
Introduction to OTBN
10.2.2.
Theory of Operation
10.2.3.
ISA Guide
10.2.4.
Design Verification
10.2.5.
Random Instruction Generator
❱
10.2.5.1.
Internals
10.2.5.2.
Configuration
10.2.6.
memutil wrapper
10.2.7.
OTBN Simulation Software
10.2.8.
Tracer
10.2.9.
Formal Masking Verification Using Alma
10.2.10.
Functional Coverage
10.2.11.
Developer's Guide
10.2.12.
Hardware Interfaces
10.2.13.
Registers
10.2.14.
Checklist
11.
Hardware IP Blocks
❱
11.1.
Analog to Digital Converter Control
❱
11.1.1.
Theory of Operation
11.1.2.
Design Verification
11.1.3.
Testplan
11.1.4.
Programmer's Guide
11.1.5.
Hardware Interfaces
11.1.6.
Registers
11.1.7.
Checklist
11.2.
AES
❱
11.2.1.
Theory of Operation
11.2.2.
Design Verification
11.2.3.
Testplan
11.2.4.
Programmer's Guide
11.2.5.
Hardware Interfaces
11.2.6.
Registers
11.2.7.
Device Interface Functions
11.2.8.
Checklist
11.3.
AON Timer
❱
11.3.1.
Theory of Operation
11.3.2.
Design Verification
11.3.3.
Testplan
11.3.4.
Programmer's Guide
11.3.5.
Hardware Interfaces
11.3.6.
Registers
11.3.7.
Device Interface Functions
11.3.8.
Checklist
11.4.
Ascon
❱
11.4.1.
Background
11.4.2.
Theory of Operation
11.4.3.
Programmer's Guide
11.4.4.
Hardware Interfaces
11.4.5.
Registers
11.4.6.
Checklist
11.5.
CSRNG
❱
11.5.1.
Theory of Operation
11.5.2.
Design Verification
11.5.3.
Testplan
11.5.4.
Programmer's Guide
11.5.5.
Hardware Interfaces
11.5.6.
Registers
11.5.7.
Device Interface Functions
11.5.8.
Checklist
11.6.
DMA
❱
11.6.1.
Theory of Operation
11.6.2.
Design Verification
11.6.3.
Testplan
11.6.4.
Programmer's Guide
11.6.5.
Hardware Interfaces
11.6.6.
Registers
11.6.7.
Device Interface Functions
11.6.8.
Checklist
11.7.
EDN
❱
11.7.1.
Theory of Operation
11.7.2.
Design Verification
11.7.3.
Testplan
11.7.4.
Programmer's Guide
11.7.5.
Hardware Interfaces
11.7.6.
Registers
11.7.7.
Device Interface Functions
11.7.8.
Checklist
11.8.
Entropy Source
❱
11.8.1.
Theory of Operation
11.8.2.
Design Verification
11.8.3.
Testplan
11.8.4.
Programmer's Guide
11.8.5.
Hardware Interfaces
11.8.6.
Registers
11.8.7.
Device Interface Functions
11.8.8.
Checklist
11.9.
Flash Controller
❱
11.9.1.
Theory of Operation
11.9.2.
Design Verification
11.9.3.
Testplan
11.9.4.
Programmer's Guide
11.9.5.
Hardware Interfaces
11.9.6.
Registers
11.9.7.
Device Interface Functions
11.9.8.
Checklist
11.10.
HMAC
❱
11.10.1.
Theory of Operation
11.10.2.
Design Verification
11.10.3.
Testplan
11.10.4.
Programmer's Guide
11.10.5.
Hardware Interfaces
11.10.6.
Registers
11.10.7.
Device Interface Functions
11.10.8.
Checklist
11.11.
I2C
❱
11.11.1.
Theory of Operation
11.11.2.
Design Verification
11.11.3.
Testplan
11.11.4.
Programmer's Guide
11.11.5.
Hardware Interfaces
11.11.6.
Registers
11.11.7.
Device Interface Functions
11.11.8.
Checklist
11.12.
Key Manager
❱
11.12.1.
Theory of Operation
11.12.2.
Design Verification
11.12.3.
Testplan
11.12.4.
Programmer's Guide
11.12.5.
Hardware Interfaces
11.12.6.
Registers
11.12.7.
Device Interface Functions
11.12.8.
Checklist
11.13.
Key Manager DPE
❱
11.13.1.
Theory of Operation
11.13.2.
Design Verification
11.13.3.
Testplan
11.13.4.
Programmer's Guide
11.13.5.
Hardware Interfaces
11.13.6.
Registers
11.13.7.
Device Interface Functions
11.13.8.
Checklist
11.14.
KMAC
❱
11.14.1.
Theory of Operation
11.14.2.
Design Verification
11.14.3.
Testplan
11.14.4.
Programmer's Guide
11.14.5.
Hardware Interfaces
11.14.6.
Registers
11.14.7.
Device Interface Functions
11.14.8.
Checklist
11.15.
Life Cycle Controller
❱
11.15.1.
Theory of Operation
11.15.2.
Design Verification
11.15.3.
Testplan
11.15.4.
Programmer's Guide
11.15.5.
Hardware Interfaces
11.15.6.
Registers
11.15.7.
Device Interface Functions
11.15.8.
Checklist
11.16.
Mailbox
❱
11.16.1.
Theory of Operation
11.16.2.
Design Verification
11.16.3.
Testplan
11.16.4.
Programmer's Guide
11.16.5.
Hardware Interfaces
11.16.6.
Registers
11.16.7.
Device Interface Functions
11.16.8.
Checklist
11.17.
Pattern Generator
❱
11.17.1.
Theory of Operation
11.17.2.
Design Verification
11.17.3.
Testplan
11.17.4.
Programmer's Guide
11.17.5.
Hardware Interfaces
11.17.6.
Registers
11.17.7.
Device Interface Functions
11.17.8.
Checklist
11.18.
ROM Control
❱
11.18.1.
Theory of Operation
11.18.2.
Design Verification
11.18.3.
Testplan
11.18.4.
Programmer's Guide
11.18.5.
Hardware Interfaces
11.18.6.
Registers
11.18.7.
Device Interface Functions
11.18.8.
Checklist
11.19.
RISC-V Debug Manager
❱
11.19.1.
Theory of Operation
11.19.2.
Design Verification
11.19.3.
Testplan
11.19.4.
Programmer's Guide
11.19.5.
Hardware Interfaces
11.19.6.
Registers
11.19.7.
Checklist
11.20.
SoC Debug Access Control
❱
11.20.1.
Theory of Operation
11.20.2.
Design Verification
11.20.3.
Testplan
11.20.4.
Programmer's Guide
11.20.5.
Hardware Interfaces
11.20.6.
Registers
11.20.7.
Checklist
11.21.
SPI Device
❱
11.21.1.
Theory of Operation
11.21.2.
Design Verification
11.21.3.
Testplan
11.21.4.
Programmer's Guide
11.21.5.
Hardware Interfaces
11.21.6.
Registers
11.21.7.
Device Interface Functions
11.21.8.
Checklist
11.22.
SPI Host
❱
11.22.1.
Theory of Operation
11.22.2.
Design Verification
11.22.3.
Testplan
11.22.4.
Programmer's Guide
11.22.5.
Hardware Interfaces
11.22.6.
Registers
11.22.7.
Device Interface Functions
11.22.8.
Checklist
11.23.
SRAM Controller
❱
11.23.1.
Theory of Operation
11.23.2.
Design Verification
11.23.3.
Testplan
11.23.4.
Programmer's Guide
11.23.5.
Hardware Interfaces
11.23.6.
Registers
11.23.7.
Device Interface Functions
11.23.8.
Checklist
11.24.
System Reset Controller
❱
11.24.1.
Theory of Operation
11.24.2.
Design Verification
11.24.3.
Testplan
11.24.4.
Hardware Interfaces
11.24.5.
Registers
11.24.6.
Device Interface Functions
11.24.7.
Checklist
11.25.
Timer
❱
11.25.1.
Theory of Operation
11.25.2.
Design Verification
11.25.3.
Testplan
11.25.4.
Programmer's Guide
11.25.5.
Hardware Interfaces
11.25.6.
Registers
11.25.7.
Device Interface Functions
11.25.8.
Checklist
11.26.
TL-UL Bus
❱
11.26.1.
Design Verification
11.26.2.
Testplan
11.26.3.
Protocol Checker
11.27.
UART
❱
11.27.1.
Theory of Operation
11.27.2.
Design Verification
11.27.3.
Testplan
11.27.4.
Programmer's Guide
11.27.5.
Hardware Interfaces
11.27.6.
Registers
11.27.7.
Device Interface Functions
11.27.8.
Checklist
11.28.
USB 2.0
❱
11.28.1.
Theory of Operation
11.28.2.
Design Verification
11.28.3.
Testplan
11.28.4.
Programmer's Guide
11.28.5.
Suspending and Resuming
11.28.6.
Hardware Interfaces
11.28.7.
Registers
11.28.8.
Device Interface Functions
11.28.9.
Checklist
12.
lowRISC Hardware Primitives
❱
12.1.
Flash Wrapper
12.2.
Keccak Permutation
12.3.
Linear Feedback Shift Register
12.4.
Packer
12.5.
Packer FIFO
12.6.
Present Scrambler
12.7.
Prince Scrambler
12.8.
Pseudo Random Number Generator
12.9.
SRAM Scrambler
13.
Common SystemVerilog and UVM Components
❱
13.1.
ALERT_ESC Agent
13.2.
Bus Params Package
13.3.
Comportable IP Testbench Architecture
13.4.
Common Interfaces
13.5.
CSR Utils
13.6.
CSRNG Agent
13.7.
DV Library Classes
13.8.
DV Utils
13.9.
FLASH_PHY_PRIM Agent
13.10.
I2C Agent
13.11.
JTAG Agent
13.12.
JTAG DMI Agent
13.13.
JTAG RISCV Agent
13.14.
KEY_SIDELOAD Agent
13.15.
KMAC_APP Agent
13.16.
Memory Backdoor Scoreboard
13.17.
Memory Backdoor Utility
13.18.
Memory Model
13.19.
PATTGEN Agent
13.20.
PUSH_PULL Agent
13.21.
PWM Monitor
13.22.
RNG Agent
13.23.
Scoreboard
13.24.
Simulation SRAM
13.25.
SPI Agent
13.26.
String Utils
13.27.
Test Vectors
13.28.
Tile Link Agent
13.29.
UART Agent
13.30.
USB20 Agent
OpenTitan Security
14.
Introduction
15.
Cryptography Library
❱
15.1.
API Documentation
15.2.
Security Hardening
15.3.
Contributing
16.
Implementation Guidelines
❱
16.1.
Secure Hardware Design Guidelines
16.2.
Reset vs. Non-Reset Flops
17.
Logical Security Model
18.
Security Model Specification
❱
18.1.
Device Attestation
18.2.
Device Life Cycle
18.3.
Device Provisioning
18.4.
Firmware Update
18.5.
Identities and Root Keys
18.6.
Ownership Transfer
18.7.
Secure Boot
19.
Lightweight Threat Model
20.
Penetration test Framework
OpenTitan Software
21.
Introduction
22.
Build Software
❱
22.1.
External dependencies
22.2.
RISC-V toolchain
22.3.
Build & Test Rules
22.4.
Top selection
22.5.
Creating a new top
22.6.
FPGA Bitstreams
23.
Device Software
❱
23.1.
Device Libraries
❱
23.1.1.
DIF Library
❱
23.1.1.1.
ADC Checklist
23.1.1.2.
AES Checklist
23.1.1.3.
Alert Handler Checklist
23.1.1.4.
Always-On Timer Checklist
23.1.1.5.
Clock Manager Checklist
23.1.1.6.
CSRNG Checklist
23.1.1.7.
DMA Checklist
23.1.1.8.
EDN Checklist
23.1.1.9.
Entropy Source Checklist
23.1.1.10.
Flash Controller Checklist
23.1.1.11.
GPIO Checklist
23.1.1.12.
HMAC Checklist
23.1.1.13.
I2C Checklist
23.1.1.14.
Key Manager Checklist
23.1.1.15.
Key Manager DPE Checklist
23.1.1.16.
KMAC Checklist
23.1.1.17.
Lifecycle Checklist
23.1.1.18.
Mailbox Checklist
23.1.1.19.
OTBN Checklist
23.1.1.20.
OTP Controller Checklist
23.1.1.21.
Pattern Generator Checklist
23.1.1.22.
Pin Multiplexer Checklist
23.1.1.23.
PWM Checklist
23.1.1.24.
Power Manager Checklist
23.1.1.25.
ROM Checklist
23.1.1.26.
Reset Manager Checklist
23.1.1.27.
RV Core Ibex Checklist
23.1.1.28.
PLIC Checklist
23.1.1.29.
RV Timer Checklist
23.1.1.30.
Sensor Controller Checklist
23.1.1.31.
SPI Device Checklist
23.1.1.32.
SPI Host Checklist
23.1.1.33.
SRAM Controller Checklist
23.1.1.34.
System Reset Controller Checklist
23.1.1.35.
UART Checklist
23.1.1.36.
USB Checklist
23.1.2.
OpenTitan Standard Library
❱
23.1.2.1.
Freestanding C Headers
23.1.3.
Top-Level Test Libraries
23.2.
Silicon Creator Software
❱
23.2.1.
Manufacturing Firmware
❱
23.2.1.1.
Test Plan
23.2.2.
ROM
❱
23.2.2.1.
ROM Specification
23.2.2.2.
Bootstrap
23.2.2.3.
Memory Protection
23.2.2.4.
E2E tests
23.2.2.5.
Root Keys
23.2.2.6.
Signature Verification
23.2.2.7.
Test Plan
23.2.2.8.
Signoff Test Plan
23.2.2.9.
Shutdown Specification
23.2.3.
ROM_EXT
❱
23.2.3.1.
ROM_EXT for Silicon Validation
23.2.3.2.
ROM_EXT Ownership Transfer
23.2.3.3.
ROM_EXT Rescue Protocol
23.2.3.4.
Manifest Format
23.2.4.
Boot Log
23.3.
Top-Level Tests
❱
23.3.1.
On-Device Test Framework
23.3.2.
Manufacturer Test Hooks
23.3.3.
Cryptotest
23.3.4.
Silicon Validation
❱
23.3.4.1.
Developer Guide
24.
Host Software
❱
24.1.
OpenTitanLib
❱
24.1.1.
Bitbanging
24.2.
OpenTitanTool
24.3.
OpenTitanSession
24.4.
OpenTitan Certificate Generator
24.5.
Signing Guide
24.6.
TPM2 Test Server
25.
Tooling
❱
25.1.
Design-Related Tooling
25.2.
fpvgen: Initial FPV Testbench Generation
25.3.
reggen & regtool: Register Generator
25.4.
Setup and use of regtool
25.5.
ralgen: FuseSoC UVM RAL Generator
25.6.
uvmdvgen: Initial Testbench Auto-generation
25.7.
tlgen: Crossbar Generation
25.8.
ipgen: Generate IP Blocks from IP Templates
25.9.
topgen: Top Generator
25.10.
vendor: Vendoring In Tool
25.11.
i2csvg: Generate SVGs of I2C Commands
25.12.
dtgen: Generate Device Tables