OpenTitan
Getting Started
1.
Getting Started
2.
Workflows
❱
2.1.
Design Verification
2.2.
Formal Verification
2.3.
Building (and Testing) Software
2.4.
Building Documentation
2.5.
Using OpenOCD
3.
Tools Setup
❱
3.1.
FPGA Setup
3.2.
Verilator Setup
3.3.
Installing Vivado
4.
Unofficial Guides
❱
4.1.
RedHat/Fedora
Hardware
5.
Introduction
6.
Top Earlgrey
❱
6.1.
Datasheet
6.2.
Design
6.3.
Pinout / Pinmux Tables
❱
6.3.1.
ASIC
6.3.2.
CW310
6.3.3.
CW340
6.4.
Design Verification
❱
6.4.1.
Chip Testplan
6.5.
Alert Handler
❱
6.5.1.
Theory of Operation
6.5.2.
Design Verification
❱
6.5.2.1.
Testplan
6.5.3.
Programmer's Guide
6.5.4.
Interface and Registers
6.5.5.
Device Interface Functions
6.5.6.
Checklist
6.6.
Analog Sensor Top
❱
6.6.1.
Interfaces
6.7.
Clock Manager
❱
6.7.1.
Theory of Operation
6.7.2.
Design Verification
❱
6.7.2.1.
Testplan
6.7.3.
Programmer's Guide
6.7.4.
Hardware Interfaces
6.7.5.
Registers
6.7.6.
Device Interface Functions
6.7.7.
Checklist
6.8.
Flash Controller
❱
6.8.1.
Theory of Operation
6.8.2.
Design Verification
❱
6.8.2.1.
Testplan
6.8.3.
Programmer's Guide
6.8.4.
Hardware Interfaces
6.8.5.
Registers
6.8.6.
Device Interface Functions
6.8.7.
Checklist
6.9.
GPIO
❱
6.9.1.
Theory of Operation
6.9.2.
Design Verification
❱
6.9.2.1.
Testplan
6.9.3.
Programmer's Guide
6.9.4.
Hardware Interfaces
6.9.5.
Registers
6.9.6.
Device Interface Functions
6.9.7.
Checklist
6.10.
Ibex RISC-V Core Wrapper
❱
6.10.1.
Theory of Operation
6.10.2.
Design Verification
6.10.3.
Programmer's Guide
6.10.4.
Hardware Interfaces
6.10.5.
Registers
6.10.6.
Checklist
6.11.
Interrupt Controller
❱
6.11.1.
Theory of Operation
6.11.2.
Design Verification
❱
6.11.2.1.
Testplan
6.11.3.
Programmer's Guide
6.11.4.
Interface and Registers
6.11.5.
Device Interface Functions
6.11.6.
Checklist
6.12.
OTP Controller
❱
6.12.1.
Theory of Operation
6.12.2.
Design Verification
❱
6.12.2.1.
Testplan
6.12.3.
Programmer's Guide
6.12.4.
Hardware Interfaces
6.12.5.
Registers
6.12.6.
Device Interface Functions
6.12.7.
Checklist
6.13.
Pinmux
❱
6.13.1.
Theory of Operation
6.13.2.
Design Verification
❱
6.13.2.1.
Testplan
6.13.3.
Programmer's Guide
6.13.4.
Hardware Interfaces
6.13.5.
Registers
6.13.6.
Device Interface Functions
6.13.7.
Checklist
6.14.
Power Management
❱
6.14.1.
Theory of Operation
6.14.2.
Design Verification
❱
6.14.2.1.
Testplan
6.14.3.
Programmer's Guide
6.14.4.
Hardware Interfaces
6.14.5.
Registers
6.14.6.
Device Interface Functions
6.14.7.
Checklist
6.15.
Pulse Width Modulator
❱
6.15.1.
Theory of Operation
6.15.2.
Design Verification
❱
6.15.2.1.
Testplan
6.15.3.
Programmer's Guide
6.15.4.
Hardware Interfaces
6.15.5.
Registers
6.15.6.
Device Interface Functions
6.15.7.
Checklist
6.16.
Reset Manager
❱
6.16.1.
Theory of Operation
6.16.2.
Design Verification
❱
6.16.2.1.
Testplan
6.16.3.
Programmer's Guide
6.16.4.
Hardware Interfaces
6.16.5.
Registers
6.16.6.
Device Interface Functions
6.16.7.
Checklist
6.17.
Sensor Control
❱
6.17.1.
Theory of Operation
6.17.2.
Programmer's Guide
6.17.3.
Hardware Interfaces
6.17.4.
Registers
6.17.5.
Device Interface Functions
6.17.6.
Checklist
6.18.
TL-UL Checklist
7.
Top Darjeeling
❱
7.1.
Datasheet
7.2.
Pinout / Pinmux Tables
❱
7.2.1.
ASIC
7.2.2.
CW310
7.3.
AC Range Check
❱
7.3.1.
Theory of Operation
7.3.2.
Design Verification
❱
7.3.2.1.
Testplan
7.3.3.
Hardware Interfaces
7.3.4.
Registers
7.3.5.
Checklist
7.4.
Alert Handler
❱
7.4.1.
Theory of Operation
7.4.2.
Design Verification
❱
7.4.2.1.
Testplan
7.4.3.
Programmer's Guide
7.4.4.
Interface and Registers
7.4.5.
Device Interface Functions
7.4.6.
Checklist
7.5.
Clock Manager
❱
7.5.1.
Theory of Operation
7.5.2.
Design Verification
❱
7.5.2.1.
Testplan
7.5.3.
Programmer's Guide
7.5.4.
Hardware Interfaces
7.5.5.
Registers
7.5.6.
Device Interface Functions
7.5.7.
Checklist
7.6.
GPIO
❱
7.6.1.
Theory of Operation
7.6.2.
Design Verification
❱
7.6.2.1.
Testplan
7.6.3.
Programmer's Guide
7.6.4.
Hardware Interfaces
7.6.5.
Registers
7.6.6.
Device Interface Functions
7.6.7.
Checklist
7.7.
Ibex RISC-V Core Wrapper
❱
7.7.1.
Theory of Operation
7.7.2.
Design Verification
7.7.3.
Programmer's Guide
7.7.4.
Hardware Interfaces
7.7.5.
Registers
7.7.6.
Checklist
7.8.
Interrupt Controller
❱
7.8.1.
Theory of Operation
7.8.2.
Design Verification
❱
7.8.2.1.
Testplan
7.8.3.
Programmer's Guide
7.8.4.
Interface and Registers
7.8.5.
Device Interface Functions
7.9.
OTP Controller
❱
7.9.1.
Theory of Operation
7.9.2.
Design Verification
❱
7.9.2.1.
Testplan
7.9.3.
Programmer's Guide
7.9.4.
Hardware Interfaces
7.9.5.
Registers
7.9.6.
Device Interface Functions
7.9.7.
Checklist
7.10.
Pinmux
❱
7.10.1.
Theory of Operation
7.10.2.
Design Verification
❱
7.10.2.1.
Testplan
7.10.3.
Programmer's Guide
7.10.4.
Hardware Interfaces
7.10.5.
Registers
7.10.6.
Device Interface Functions
7.10.7.
Checklist
7.11.
Power Management
❱
7.11.1.
Theory of Operation
7.11.2.
Design Verification
❱
7.11.2.1.
Testplan
7.11.3.
Programmer's Guide
7.11.4.
Hardware Interfaces
7.11.5.
Registers
7.11.6.
Device Interface Functions
7.11.7.
Checklist
7.12.
RACL Control
❱
7.12.1.
RACL Configuration
7.12.2.
Hardware Interfaces
7.12.3.
Registers
7.13.
Reset Manager
❱
7.13.1.
Theory of Operation
7.13.2.
Design Verification
❱
7.13.2.1.
Testplan
7.13.3.
Programmer's Guide
7.13.4.
Hardware Interfaces
7.13.5.
Registers
7.13.6.
Device Interface Functions
7.13.7.
Checklist
8.
Cores
❱
8.1.
Ibex RISC-V Core Wrapper
❱
8.1.1.
Theory of Operation
8.1.2.
Design Verification
8.1.3.
Programmer's Guide
8.1.4.
Hardware Interfaces
8.1.5.
Registers
8.1.6.
Checklist
8.2.
OTBN
❱
8.2.1.
Theory of Operation
8.2.2.
Introduction to OTBN
8.2.3.
Developing OTBN
8.2.4.
ISA Guide
8.2.5.
Design Verification
❱
8.2.5.1.
Random Instruction Generator
❱
8.2.5.1.1.
Internals
8.2.5.1.2.
Configuration
8.2.5.2.
memutil wrapper
8.2.5.3.
OTBN Simulation Software
8.2.5.4.
Tracer
8.2.5.5.
Formal Masking Verification Using Alma
8.2.6.
Functional Coverage
8.2.7.
Programmer's Guide
8.2.8.
Hardware Interfaces
8.2.9.
Registers
8.2.10.
Checklist
9.
Hardware IP Blocks
❱
9.1.
Analog to Digital Converter Control
❱
9.1.1.
Theory of Operation
9.1.2.
Design Verification
❱
9.1.2.1.
Testplan
9.1.3.
Programmer's Guide
9.1.4.
Hardware Interfaces
9.1.5.
Registers
9.1.6.
Checklist
9.2.
AES
❱
9.2.1.
Theory of Operation
9.2.2.
Design Verification
❱
9.2.2.1.
Testplan
9.2.3.
Programmer's Guide
9.2.4.
Hardware Interfaces
9.2.5.
Registers
9.2.6.
Device Interface Functions
9.2.7.
Checklist
9.3.
AON Timer
❱
9.3.1.
Theory of Operation
9.3.2.
Design Verification
❱
9.3.2.1.
Testplan
9.3.3.
Programmer's Guide
9.3.4.
Hardware Interfaces
9.3.5.
Registers
9.3.6.
Device Interface Functions
9.3.7.
Checklist
9.4.
Ascon
❱
9.4.1.
Background
9.4.2.
Theory of Operation
9.4.3.
Programmer's Guide
9.4.4.
Hardware Interfaces
9.4.5.
Registers
9.4.6.
Checklist
9.5.
CSRNG
❱
9.5.1.
Theory of Operation
9.5.2.
Design Verification
❱
9.5.2.1.
Testplan
9.5.3.
Programmer's Guide
9.5.4.
Hardware Interfaces
9.5.5.
Registers
9.5.6.
Device Interface Functions
9.5.7.
Checklist
9.6.
DMA
❱
9.6.1.
Theory of Operation
9.6.2.
Design Verification
❱
9.6.2.1.
Testplan
9.6.3.
Programmer's Guide
9.6.4.
Hardware Interfaces
9.6.5.
Registers
9.6.6.
Device Interface Functions
9.6.7.
Checklist
9.7.
EDN
❱
9.7.1.
Theory of Operation
9.7.2.
Design Verification
❱
9.7.2.1.
Testplan
9.7.3.
Programmer's Guide
9.7.4.
Hardware Interfaces
9.7.5.
Registers
9.7.6.
Device Interface Functions
9.7.7.
Checklist
9.8.
Entropy Source
❱
9.8.1.
Theory of Operation
9.8.2.
Design Verification
❱
9.8.2.1.
Testplan
9.8.3.
Programmer's Guide
9.8.4.
Hardware Interfaces
9.8.5.
Registers
9.8.6.
Device Interface Functions
9.8.7.
Checklist
9.9.
Flash Controller
❱
9.9.1.
Theory of Operation
9.9.2.
Design Verification
❱
9.9.2.1.
Testplan
9.9.3.
Programmer's Guide
9.9.4.
Hardware Interfaces
9.9.5.
Registers
9.9.6.
Device Interface Functions
9.9.7.
Checklist
9.10.
HMAC
❱
9.10.1.
Theory of Operation
9.10.2.
Design Verification
❱
9.10.2.1.
Testplan
9.10.3.
Programmer's Guide
9.10.4.
Hardware Interfaces
9.10.5.
Registers
9.10.6.
Device Interface Functions
9.10.7.
Checklist
9.11.
I2C
❱
9.11.1.
Theory of Operation
9.11.2.
Design Verification
❱
9.11.2.1.
Testplan
9.11.3.
Programmer's Guide
9.11.4.
Hardware Interfaces
9.11.5.
Registers
9.11.6.
Device Interface Functions
9.11.7.
Checklist
9.12.
Key Manager
❱
9.12.1.
Theory of Operation
9.12.2.
Design Verification
❱
9.12.2.1.
Testplan
9.12.3.
Programmer's Guide
9.12.4.
Hardware Interfaces
9.12.5.
Registers
9.12.6.
Device Interface Functions
9.12.7.
Checklist
9.13.
Key Manager DPE
❱
9.13.1.
Theory of Operation
9.13.2.
Design Verification
❱
9.13.2.1.
Testplan
9.13.3.
Programmer's Guide
9.13.4.
Hardware Interfaces
9.13.5.
Registers
9.13.6.
Device Interface Functions
9.13.7.
Checklist
9.14.
KMAC
❱
9.14.1.
Theory of Operation
9.14.2.
Design Verification
❱
9.14.2.1.
Testplan
9.14.3.
Programmer's Guide
9.14.4.
Hardware Interfaces
9.14.5.
Registers
9.14.6.
Device Interface Functions
9.14.7.
Checklist
9.15.
Life Cycle Controller
❱
9.15.1.
Theory of Operation
9.15.2.
Design Verification
❱
9.15.2.1.
Testplan
9.15.3.
Programmer's Guide
9.15.4.
Hardware Interfaces
9.15.5.
Registers
9.15.6.
Device Interface Functions
9.15.7.
Checklist
9.16.
Mailbox
❱
9.16.1.
Theory of Operation
9.16.2.
Design Verification
❱
9.16.2.1.
Testplan
9.16.3.
Programmer's Guide
9.16.4.
Hardware Interfaces
9.16.5.
Registers
9.16.6.
Device Interface Functions
9.16.7.
Checklist
9.17.
Pattern Generator
❱
9.17.1.
Theory of Operation
9.17.2.
Design Verification
❱
9.17.2.1.
Testplan
9.17.3.
Programmer's Guide
9.17.4.
Hardware Interfaces
9.17.5.
Registers
9.17.6.
Device Interface Functions
9.17.7.
Checklist
9.18.
ROM Control
❱
9.18.1.
Theory of Operation
9.18.2.
Design Verification
❱
9.18.2.1.
Testplan
9.18.3.
Programmer's Guide
9.18.4.
Hardware Interfaces
9.18.5.
Registers
9.18.6.
Device Interface Functions
9.18.7.
Checklist
9.19.
RISC-V Debug Manager
❱
9.19.1.
Theory of Operation
9.19.2.
Design Verification
❱
9.19.2.1.
Testplan
9.19.3.
Programmer's Guide
9.19.4.
Hardware Interfaces
9.19.5.
Registers
9.19.6.
Checklist
9.20.
SoC Debug Access Control
❱
9.20.1.
Theory of Operation
9.20.2.
Design Verification
❱
9.20.2.1.
Testplan
9.20.3.
Programmer's Guide
9.20.4.
Hardware Interfaces
9.20.5.
Registers
9.20.6.
Checklist
9.21.
SPI Device
❱
9.21.1.
Theory of Operation
9.21.2.
Design Verification
❱
9.21.2.1.
Testplan
9.21.3.
Programmer's Guide
9.21.4.
Hardware Interfaces
9.21.5.
Registers
9.21.6.
Device Interface Functions
9.21.7.
Checklist
9.22.
SPI Host
❱
9.22.1.
Theory of Operation
9.22.2.
Design Verification
❱
9.22.2.1.
Testplan
9.22.3.
Programmer's Guide
9.22.4.
Hardware Interfaces
9.22.5.
Registers
9.22.6.
Device Interface Functions
9.22.7.
Checklist
9.23.
SRAM Controller
❱
9.23.1.
Theory of Operation
9.23.2.
Design Verification
❱
9.23.2.1.
Testplan
9.23.3.
Programmer's Guide
9.23.4.
Hardware Interfaces
9.23.5.
Registers
9.23.6.
Device Interface Functions
9.23.7.
Checklist
9.24.
System Reset Controller
❱
9.24.1.
Theory of Operation
9.24.2.
Design Verification
❱
9.24.2.1.
Testplan
9.24.3.
Hardware Interfaces
9.24.4.
Registers
9.24.5.
Device Interface Functions
9.24.6.
Checklist
9.25.
Timer
❱
9.25.1.
Theory of Operation
9.25.2.
Design Verification
❱
9.25.2.1.
Testplan
9.25.3.
Programmer's Guide
9.25.4.
Hardware Interfaces
9.25.5.
Registers
9.25.6.
Device Interface Functions
9.25.7.
Checklist
9.26.
TL-UL Bus
❱
9.26.1.
Design Verification
❱
9.26.1.1.
Testplan
9.26.1.2.
Protocol Checker
9.27.
UART
❱
9.27.1.
Theory of Operation
9.27.2.
Design Verification
❱
9.27.2.1.
Testplan
9.27.3.
Programmer's Guide
9.27.4.
Hardware Interfaces
9.27.5.
Registers
9.27.6.
Device Interface Functions
9.27.7.
Checklist
9.28.
USB 2.0
❱
9.28.1.
Theory of Operation
9.28.2.
Design Verification
❱
9.28.2.1.
Testplan
9.28.3.
Programmer's Guide
9.28.4.
Suspending and Resuming
9.28.5.
Hardware Interfaces
9.28.6.
Registers
9.28.7.
Device Interface Functions
9.28.8.
Checklist
10.
lowRISC Hardware Primitives
❱
10.1.
Flash Wrapper
10.2.
Keccak Permutation
10.3.
Linear Feedback Shift Register
10.4.
Packer
10.5.
Packer FIFO
10.6.
Present Scrambler
10.7.
Prince Scrambler
10.8.
Pseudo Random Number Generator
10.9.
SRAM Scrambler
11.
Common SystemVerilog and UVM Components
❱
11.1.
ALERT_ESC Agent
11.2.
Bus Params Package
11.3.
Comportable IP Testbench Architecture
11.4.
Common Interfaces
11.5.
CSR Utils
11.6.
CSRNG Agent
11.7.
DV Library Classes
11.8.
DV Utils
11.9.
FLASH_PHY_PRIM Agent
11.10.
I2C Agent
11.11.
JTAG Agent
11.12.
JTAG DMI Agent
11.13.
JTAG RISCV Agent
11.14.
KEY_SIDELOAD Agent
11.15.
KMAC_APP Agent
11.16.
Memory Backdoor Scoreboard
11.17.
Memory Backdoor Utility
11.18.
Memory Model
11.19.
PATTGEN Agent
11.20.
PUSH_PULL Agent
11.21.
PWM Monitor
11.22.
RNG Agent
11.23.
Scoreboard
11.24.
Simulation SRAM
11.25.
SPI Agent
11.26.
String Utils
11.27.
Test Vectors
11.28.
Tile Link Agent
11.29.
UART Agent
11.30.
USB20 Agent
Software
12.
Introduction
13.
Build Software
❱
13.1.
External dependencies
13.2.
RISC-V toolchain
14.
Device Software
❱
14.1.
Build & Test Rules
❱
14.1.1.
Top selection
❱
14.1.1.1.
Creating a new top
14.1.2.
FPGA Bitstreams
14.2.
Device Libraries
❱
14.2.1.
DIF Library
❱
14.2.1.1.
ADC Checklist
14.2.1.2.
AES Checklist
14.2.1.3.
Alert Handler Checklist
14.2.1.4.
Always-On Timer Checklist
14.2.1.5.
Clock Manager Checklist
14.2.1.6.
CSRNG Checklist
14.2.1.7.
DMA Checklist
14.2.1.8.
EDN Checklist
14.2.1.9.
Entropy Source Checklist
14.2.1.10.
Flash Controller Checklist
14.2.1.11.
GPIO Checklist
14.2.1.12.
HMAC Checklist
14.2.1.13.
I2C Checklist
14.2.1.14.
Key Manager Checklist
14.2.1.15.
Key Manager DPE Checklist
14.2.1.16.
KMAC Checklist
14.2.1.17.
Lifecycle Checklist
14.2.1.18.
Mailbox Checklist
14.2.1.19.
OTBN Checklist
14.2.1.20.
OTP Controller Checklist
14.2.1.21.
Pattern Generator Checklist
14.2.1.22.
Pin Multiplexer Checklist
14.2.1.23.
PWM Checklist
14.2.1.24.
Power Manager Checklist
14.2.1.25.
ROM Checklist
14.2.1.26.
Reset Manager Checklist
14.2.1.27.
RV Core Ibex Checklist
14.2.1.28.
PLIC Checklist
14.2.1.29.
RV Timer Checklist
14.2.1.30.
Sensor Controller Checklist
14.2.1.31.
SPI Device Checklist
14.2.1.32.
SPI Host Checklist
14.2.1.33.
SRAM Controller Checklist
14.2.1.34.
System Reset Controller Checklist
14.2.1.35.
UART Checklist
14.2.1.36.
USB Checklist
14.2.2.
Top-Level Test Libraries
❱
14.2.2.1.
On-Device Test Framework
14.2.3.
OpenTitan Standard Library
❱
14.2.3.1.
Freestanding C Headers
14.3.
Silicon Creator Software
❱
14.3.1.
Manufacturing Firmware
❱
14.3.1.1.
Test Plan
14.3.2.
ROM
❱
14.3.2.1.
ROM Specification
14.3.2.2.
Bootstrap
14.3.2.3.
Memory Protection
14.3.2.4.
E2E tests
14.3.2.5.
Root Keys
14.3.2.6.
Signature Verification
14.3.2.7.
Test Plan
14.3.2.8.
Signoff Test Plan
14.3.2.9.
Shutdown Specification
14.3.3.
ROM_EXT
❱
14.3.3.1.
ROM_EXT for Silicon Validation
14.3.3.2.
ROM_EXT Ownership Transfer
14.3.3.3.
ROM_EXT Rescue Protocol
14.3.4.
Manifest Format
14.3.5.
Boot Log
14.4.
Top-Level Tests
❱
14.4.1.
Manufacturer Test Hooks
14.4.2.
Cryptotest
14.5.
Silicon Validation
❱
14.5.1.
Developer Guide
15.
Host Software
❱
15.1.
OpenTitanLib
15.2.
OpenTitanTool
15.3.
OpenTitanSession
15.4.
OpenTitan Certificate Generator
15.5.
Hardware Security Module (HSM) tool
❱
15.5.1.
Requirements
15.5.2.
Signing Guide
15.6.
TPM2 Test Server
Tooling
16.
Tools Overview
17.
Design-Related Tooling
18.
dvsim
❱
18.1.
Design Document
18.2.
Testplanner
18.3.
Glossary
19.
fpvgen: Initial FPV Testbench Generation
20.
reggen & regtool: Register Generator
❱
20.1.
Setup and use of regtool
21.
ralgen: FuseSoC UVM RAL Generator
22.
uvmdvgen: Initial Testbench Auto-generation
23.
tlgen: Crossbar Generation
24.
ipgen: Generate IP Blocks from IP Templates
25.
topgen: Top Generator
26.
vendor: Vendoring In Tool
27.
i2csvg: Generate SVGs of I2C Commands
28.
dtgen: Generate Device Tables
Contributing
29.
Contributing
❱
29.1.
Detailed Contribution Guide
29.2.
Directory Structure
29.3.
Contributing to Documentation
❱
29.3.1.
An Example IP Block's Documentation
29.4.
Continuous Integration
29.5.
Top-Level Design and Targets
29.6.
GitHub Notes
29.7.
Bazel Notes
29.8.
Using the Container
30.
Contributing to Hardware
❱
30.1.
Comportability
30.2.
RACL
30.3.
Hardware Design
30.4.
Design Methodology
30.5.
Vendoring in Hardware
30.6.
Linting
30.7.
Synthesis Flow
31.
Contributing to Verification
❱
31.1.
Verification Methodology
31.2.
Security Countermeasure Verification Framework
31.3.
Assertions
32.
Contributing to Software
❱
32.1.
Device Interface Functions
32.2.
Writing and Building Software for OTBN
33.
Style Guides
❱
33.1.
HJSON
33.2.
Python
33.3.
C & C++
33.4.
Markdown
33.5.
RISC-V Assembly
33.6.
OTBN Assembly
33.7.
Guidance for Volatile
34.
Developing on an FPGA
❱
34.1.
Get a Board
34.2.
FPGA Reference Manual
34.3.
Debugging with an ILA
Project Governance
35.
Introduction
36.
Committers
37.
RFC Process
38.
Generalized Priority Definitions
39.
Generalized Project Milestone Definitions
40.
OpenTitan Technical Committee
41.
Hardware Development Stages
42.
Signoff Checklist
Security
43.
Security
44.
Cryptography Library
❱
44.1.
API Documentation
44.2.
Contributing
45.
Implementation Guidelines
❱
45.1.
Secure Hardware Design Guidelines
45.2.
Reset vs. Non-Reset Flops
46.
Logical Security Model
47.
Security Model Specification
❱
47.1.
Device Attestation
47.2.
Device Life Cycle
47.3.
Device Provisioning
47.4.
Firmware Update
47.5.
Identities and Root Keys
47.6.
Ownership Transfer
47.7.
Secure Boot
48.
Lightweight Threat Model
Use Cases
49.
Use Cases
50.
Platform Integrity Module
51.
Trusted Platform Module
52.
Universal 2nd-Factor Security Key
Rust for C Developers
53.
Rust for Embedded C Programmers
Appendix
54.
Glossary