1.
About OpenTitan
❱
1.1.
Introduction
1.2.
Why Open Source?
1.3.
OpenTitan News
1.4.
Product Architecture
1.5.
History
1.6.
OpenTitan updates - RFCs
1.7.
lowRISC CIC
1.8.
Glossary
2.
Governance and Policies
❱
2.1.
Introduction
2.2.
Governing Board
2.3.
Technical Committee
2.4.
Working Groups
2.5.
User accounts
2.6.
Trademarks
2.7.
Code of Conduct
2.8.
Communication Policy
3.
Use Cases
❱
3.1.
Introduction
3.2.
Platform Integrity Module
3.3.
Trusted Platform Module
3.4.
Universal 2nd-Factor Security Key
4.
Hardware
❱
4.1.
Introduction
4.2.
Top Earlgrey
❱
4.2.1.
Datasheet
4.2.2.
Memory Map
4.2.3.
Design
4.2.4.
Pinout / Pinmux Tables
❱
4.2.4.1.
ASIC
4.2.4.2.
CW310
4.2.4.3.
CW340
4.2.5.
Design Verification
❱
4.2.5.1.
Chip Testplan
4.2.6.
Alert Handler
❱
4.2.6.1.
Theory of Operation
4.2.6.2.
Design Verification
❱
4.2.6.2.1.
Testplan
4.2.6.3.
Programmer's Guide
4.2.6.4.
Interface and Registers
4.2.6.5.
Device Interface Functions
4.2.6.6.
Checklist
4.2.7.
Analog Sensor Top
❱
4.2.7.1.
Interfaces
4.2.8.
Clock Manager
❱
4.2.8.1.
Theory of Operation
4.2.8.2.
Design Verification
❱
4.2.8.2.1.
Testplan
4.2.8.3.
Programmer's Guide
4.2.8.4.
Hardware Interfaces
4.2.8.5.
Registers
4.2.8.6.
Device Interface Functions
4.2.8.7.
Checklist
4.2.9.
Flash Controller
❱
4.2.9.1.
Theory of Operation
4.2.9.2.
Design Verification
❱
4.2.9.2.1.
Testplan
4.2.9.3.
Programmer's Guide
4.2.9.4.
Hardware Interfaces
4.2.9.5.
Registers
4.2.9.6.
Device Interface Functions
4.2.9.7.
Checklist
4.2.10.
GPIO
❱
4.2.10.1.
Theory of Operation
4.2.10.2.
Design Verification
❱
4.2.10.2.1.
Testplan
4.2.10.3.
Programmer's Guide
4.2.10.4.
Hardware Interfaces
4.2.10.5.
Registers
4.2.10.6.
Device Interface Functions
4.2.10.7.
Checklist
4.2.11.
Ibex RISC-V Core Wrapper
❱
4.2.11.1.
Theory of Operation
4.2.11.2.
Boot, ROM execution and Patching
4.2.11.3.
Design Verification
4.2.11.4.
Programmer's Guide
4.2.11.5.
Hardware Interfaces
4.2.11.6.
Registers
4.2.11.7.
Checklist
4.2.12.
Interrupt Controller
❱
4.2.12.1.
Theory of Operation
4.2.12.2.
Design Verification
❱
4.2.12.2.1.
Testplan
4.2.12.3.
Programmer's Guide
4.2.12.4.
Interface and Registers
4.2.12.5.
Device Interface Functions
4.2.12.6.
Checklist
4.2.13.
OTP Controller
❱
4.2.13.1.
Theory of Operation
4.2.13.2.
Design Verification
❱
4.2.13.2.1.
Testplan
4.2.13.3.
Programmer's Guide
4.2.13.4.
Hardware Interfaces
4.2.13.5.
Registers
4.2.13.6.
Device Interface Functions
4.2.13.7.
Checklist
4.2.14.
Pinmux
❱
4.2.14.1.
Theory of Operation
4.2.14.2.
Design Verification
❱
4.2.14.2.1.
Testplan
4.2.14.3.
Programmer's Guide
4.2.14.4.
Hardware Interfaces
4.2.14.5.
Registers
4.2.14.6.
Device Interface Functions
4.2.14.7.
Checklist
4.2.15.
Power Management
❱
4.2.15.1.
Theory of Operation
4.2.15.2.
Design Verification
❱
4.2.15.2.1.
Testplan
4.2.15.3.
Programmer's Guide
4.2.15.4.
Hardware Interfaces
4.2.15.5.
Registers
4.2.15.6.
Device Interface Functions
4.2.15.7.
Checklist
4.2.16.
Pulse Width Modulator
❱
4.2.16.1.
Theory of Operation
4.2.16.2.
Design Verification
❱
4.2.16.2.1.
Testplan
4.2.16.3.
Programmer's Guide
4.2.16.4.
Hardware Interfaces
4.2.16.5.
Registers
4.2.16.6.
Device Interface Functions
4.2.16.7.
Checklist
4.2.17.
Reset Manager
❱
4.2.17.1.
Theory of Operation
4.2.17.2.
Design Verification
❱
4.2.17.2.1.
Testplan
4.2.17.3.
Programmer's Guide
4.2.17.4.
Hardware Interfaces
4.2.17.5.
Registers
4.2.17.6.
Device Interface Functions
4.2.17.7.
Checklist
4.2.18.
Sensor Control
❱
4.2.18.1.
Theory of Operation
4.2.18.2.
Programmer's Guide
4.2.18.3.
Hardware Interfaces
4.2.18.4.
Registers
4.2.18.5.
Device Interface Functions
4.2.18.6.
Checklist
4.2.19.
TL-UL Checklist
4.3.
Top Darjeeling
❱
4.3.1.
Datasheet
4.3.2.
Memory Map
4.3.3.
Pinout / Pinmux Tables
❱
4.3.3.1.
ASIC
4.3.4.
AC Range Check
❱
4.3.4.1.
Theory of Operation
4.3.4.2.
Design Verification
❱
4.3.4.2.1.
Testplan
4.3.4.3.
Hardware Interfaces
4.3.4.4.
Registers
4.3.4.5.
Checklist
4.3.5.
Alert Handler
❱
4.3.5.1.
Theory of Operation
4.3.5.2.
Design Verification
❱
4.3.5.2.1.
Testplan
4.3.5.3.
Programmer's Guide
4.3.5.4.
Interface and Registers
4.3.5.5.
Device Interface Functions
4.3.5.6.
Checklist
4.3.6.
Clock Manager
❱
4.3.6.1.
Theory of Operation
4.3.6.2.
Design Verification
❱
4.3.6.2.1.
Testplan
4.3.6.3.
Programmer's Guide
4.3.6.4.
Hardware Interfaces
4.3.6.5.
Registers
4.3.6.6.
Device Interface Functions
4.3.6.7.
Checklist
4.3.7.
GPIO
❱
4.3.7.1.
Theory of Operation
4.3.7.2.
Design Verification
❱
4.3.7.2.1.
Testplan
4.3.7.3.
Programmer's Guide
4.3.7.4.
Hardware Interfaces
4.3.7.5.
Registers
4.3.7.6.
Device Interface Functions
4.3.7.7.
Checklist
4.3.8.
Ibex RISC-V Core Wrapper
❱
4.3.8.1.
Theory of Operation
4.3.8.2.
Boot, ROM execution and Patching
4.3.8.3.
Design Verification
4.3.8.4.
Programmer's Guide
4.3.8.5.
Hardware Interfaces
4.3.8.6.
Registers
4.3.8.7.
Checklist
4.3.9.
Interrupt Controller
❱
4.3.9.1.
Theory of Operation
4.3.9.2.
Design Verification
❱
4.3.9.2.1.
Testplan
4.3.9.3.
Programmer's Guide
4.3.9.4.
Interface and Registers
4.3.9.5.
Device Interface Functions
4.3.10.
OTP Controller
❱
4.3.10.1.
Theory of Operation
4.3.10.2.
Design Verification
❱
4.3.10.2.1.
Testplan
4.3.10.3.
Programmer's Guide
4.3.10.4.
Hardware Interfaces
4.3.10.5.
Registers
4.3.10.6.
Device Interface Functions
4.3.10.7.
Checklist
4.3.11.
Pinmux
❱
4.3.11.1.
Theory of Operation
4.3.11.2.
Design Verification
❱
4.3.11.2.1.
Testplan
4.3.11.3.
Programmer's Guide
4.3.11.4.
Hardware Interfaces
4.3.11.5.
Registers
4.3.11.6.
Device Interface Functions
4.3.11.7.
Checklist
4.3.12.
Power Management
❱
4.3.12.1.
Theory of Operation
4.3.12.2.
Design Verification
❱
4.3.12.2.1.
Testplan
4.3.12.3.
Programmer's Guide
4.3.12.4.
Hardware Interfaces
4.3.12.5.
Registers
4.3.12.6.
Device Interface Functions
4.3.12.7.
Checklist
4.3.13.
RACL Control
❱
4.3.13.1.
RACL Configuration
4.3.13.2.
Hardware Interfaces
4.3.13.3.
Registers
4.3.14.
Reset Manager
❱
4.3.14.1.
Theory of Operation
4.3.14.2.
Design Verification
❱
4.3.14.2.1.
Testplan
4.3.14.3.
Programmer's Guide
4.3.14.4.
Hardware Interfaces
4.3.14.5.
Registers
4.3.14.6.
Device Interface Functions
4.3.14.7.
Checklist
4.4.
Cores
❱
4.4.1.
Ibex RISC-V Core Wrapper
❱
4.4.1.1.
Theory of Operation
4.4.1.2.
Boot, ROM execution and Patching
4.4.1.3.
Design Verification
4.4.1.4.
Programmer's Guide
4.4.1.5.
Hardware Interfaces
4.4.1.6.
Registers
4.4.1.7.
Checklist
4.4.2.
OTBN
❱
4.4.2.1.
Theory of Operation
4.4.2.2.
Introduction to OTBN
4.4.2.3.
Developing OTBN
4.4.2.4.
ISA Guide
4.4.2.5.
Design Verification
4.4.2.6.
Random Instruction Generator
❱
4.4.2.6.1.
Internals
4.4.2.6.2.
Configuration
4.4.2.7.
memutil wrapper
4.4.2.8.
OTBN Simulation Software
4.4.2.9.
Tracer
4.4.2.10.
Formal Masking Verification Using Alma
4.4.2.11.
Functional Coverage
4.4.2.12.
Programmer's Guide
4.4.2.13.
Hardware Interfaces
4.4.2.14.
Registers
4.4.2.15.
Checklist
4.5.
Hardware IP Blocks
❱
4.5.1.
Analog to Digital Converter Control
❱
4.5.1.1.
Theory of Operation
4.5.1.2.
Design Verification
4.5.1.3.
Testplan
4.5.1.4.
Programmer's Guide
4.5.1.5.
Hardware Interfaces
4.5.1.6.
Registers
4.5.1.7.
Checklist
4.5.2.
AES
❱
4.5.2.1.
Theory of Operation
4.5.2.2.
Design Verification
4.5.2.3.
Testplan
4.5.2.4.
Programmer's Guide
4.5.2.5.
Hardware Interfaces
4.5.2.6.
Registers
4.5.2.7.
Device Interface Functions
4.5.2.8.
Checklist
4.5.3.
AON Timer
❱
4.5.3.1.
Theory of Operation
4.5.3.2.
Design Verification
4.5.3.3.
Testplan
4.5.3.4.
Programmer's Guide
4.5.3.5.
Hardware Interfaces
4.5.3.6.
Registers
4.5.3.7.
Device Interface Functions
4.5.3.8.
Checklist
4.5.4.
Ascon
❱
4.5.4.1.
Background
4.5.4.2.
Theory of Operation
4.5.4.3.
Programmer's Guide
4.5.4.4.
Hardware Interfaces
4.5.4.5.
Registers
4.5.4.6.
Checklist
4.5.5.
CSRNG
❱
4.5.5.1.
Theory of Operation
4.5.5.2.
Design Verification
4.5.5.3.
Testplan
4.5.5.4.
Programmer's Guide
4.5.5.5.
Hardware Interfaces
4.5.5.6.
Registers
4.5.5.7.
Device Interface Functions
4.5.5.8.
Checklist
4.5.6.
DMA
❱
4.5.6.1.
Theory of Operation
4.5.6.2.
Design Verification
4.5.6.3.
Testplan
4.5.6.4.
Programmer's Guide
4.5.6.5.
Hardware Interfaces
4.5.6.6.
Registers
4.5.6.7.
Device Interface Functions
4.5.6.8.
Checklist
4.5.7.
EDN
❱
4.5.7.1.
Theory of Operation
4.5.7.2.
Design Verification
4.5.7.3.
Testplan
4.5.7.4.
Programmer's Guide
4.5.7.5.
Hardware Interfaces
4.5.7.6.
Registers
4.5.7.7.
Device Interface Functions
4.5.7.8.
Checklist
4.5.8.
Entropy Source
❱
4.5.8.1.
Theory of Operation
4.5.8.2.
Design Verification
4.5.8.3.
Testplan
4.5.8.4.
Programmer's Guide
4.5.8.5.
Hardware Interfaces
4.5.8.6.
Registers
4.5.8.7.
Device Interface Functions
4.5.8.8.
Checklist
4.5.9.
Flash Controller
❱
4.5.9.1.
Theory of Operation
4.5.9.2.
Design Verification
4.5.9.3.
Testplan
4.5.9.4.
Programmer's Guide
4.5.9.5.
Hardware Interfaces
4.5.9.6.
Registers
4.5.9.7.
Device Interface Functions
4.5.9.8.
Checklist
4.5.10.
HMAC
❱
4.5.10.1.
Theory of Operation
4.5.10.2.
Design Verification
4.5.10.3.
Testplan
4.5.10.4.
Programmer's Guide
4.5.10.5.
Hardware Interfaces
4.5.10.6.
Registers
4.5.10.7.
Device Interface Functions
4.5.10.8.
Checklist
4.5.11.
I2C
❱
4.5.11.1.
Theory of Operation
4.5.11.2.
Design Verification
4.5.11.3.
Testplan
4.5.11.4.
Programmer's Guide
4.5.11.5.
Hardware Interfaces
4.5.11.6.
Registers
4.5.11.7.
Device Interface Functions
4.5.11.8.
Checklist
4.5.12.
Key Manager
❱
4.5.12.1.
Theory of Operation
4.5.12.2.
Design Verification
4.5.12.3.
Testplan
4.5.12.4.
Programmer's Guide
4.5.12.5.
Hardware Interfaces
4.5.12.6.
Registers
4.5.12.7.
Device Interface Functions
4.5.12.8.
Checklist
4.5.13.
Key Manager DPE
❱
4.5.13.1.
Theory of Operation
4.5.13.2.
Design Verification
4.5.13.3.
Testplan
4.5.13.4.
Programmer's Guide
4.5.13.5.
Hardware Interfaces
4.5.13.6.
Registers
4.5.13.7.
Device Interface Functions
4.5.13.8.
Checklist
4.5.14.
KMAC
❱
4.5.14.1.
Theory of Operation
4.5.14.2.
Design Verification
4.5.14.3.
Testplan
4.5.14.4.
Programmer's Guide
4.5.14.5.
Hardware Interfaces
4.5.14.6.
Registers
4.5.14.7.
Device Interface Functions
4.5.14.8.
Checklist
4.5.15.
Life Cycle Controller
❱
4.5.15.1.
Theory of Operation
4.5.15.2.
Design Verification
4.5.15.3.
Testplan
4.5.15.4.
Programmer's Guide
4.5.15.5.
Hardware Interfaces
4.5.15.6.
Registers
4.5.15.7.
Device Interface Functions
4.5.15.8.
Checklist
4.5.16.
Mailbox
❱
4.5.16.1.
Theory of Operation
4.5.16.2.
Design Verification
4.5.16.3.
Testplan
4.5.16.4.
Programmer's Guide
4.5.16.5.
Hardware Interfaces
4.5.16.6.
Registers
4.5.16.7.
Device Interface Functions
4.5.16.8.
Checklist
4.5.17.
Pattern Generator
❱
4.5.17.1.
Theory of Operation
4.5.17.2.
Design Verification
4.5.17.3.
Testplan
4.5.17.4.
Programmer's Guide
4.5.17.5.
Hardware Interfaces
4.5.17.6.
Registers
4.5.17.7.
Device Interface Functions
4.5.17.8.
Checklist
4.5.18.
ROM Control
❱
4.5.18.1.
Theory of Operation
4.5.18.2.
Design Verification
4.5.18.3.
Testplan
4.5.18.4.
Programmer's Guide
4.5.18.5.
Hardware Interfaces
4.5.18.6.
Registers
4.5.18.7.
Device Interface Functions
4.5.18.8.
Checklist
4.5.19.
RISC-V Debug Manager
❱
4.5.19.1.
Theory of Operation
4.5.19.2.
Design Verification
4.5.19.3.
Testplan
4.5.19.4.
Programmer's Guide
4.5.19.5.
Hardware Interfaces
4.5.19.6.
Registers
4.5.19.7.
Checklist
4.5.20.
SoC Debug Access Control
❱
4.5.20.1.
Theory of Operation
4.5.20.2.
Design Verification
4.5.20.3.
Testplan
4.5.20.4.
Programmer's Guide
4.5.20.5.
Hardware Interfaces
4.5.20.6.
Registers
4.5.20.7.
Checklist
4.5.21.
SPI Device
❱
4.5.21.1.
Theory of Operation
4.5.21.2.
Design Verification
4.5.21.3.
Testplan
4.5.21.4.
Programmer's Guide
4.5.21.5.
Hardware Interfaces
4.5.21.6.
Registers
4.5.21.7.
Device Interface Functions
4.5.21.8.
Checklist
4.5.22.
SPI Host
❱
4.5.22.1.
Theory of Operation
4.5.22.2.
Design Verification
4.5.22.3.
Testplan
4.5.22.4.
Programmer's Guide
4.5.22.5.
Hardware Interfaces
4.5.22.6.
Registers
4.5.22.7.
Device Interface Functions
4.5.22.8.
Checklist
4.5.23.
SRAM Controller
❱
4.5.23.1.
Theory of Operation
4.5.23.2.
Design Verification
4.5.23.3.
Testplan
4.5.23.4.
Programmer's Guide
4.5.23.5.
Hardware Interfaces
4.5.23.6.
Registers
4.5.23.7.
Device Interface Functions
4.5.23.8.
Checklist
4.5.24.
System Reset Controller
❱
4.5.24.1.
Theory of Operation
4.5.24.2.
Design Verification
4.5.24.3.
Testplan
4.5.24.4.
Hardware Interfaces
4.5.24.5.
Registers
4.5.24.6.
Device Interface Functions
4.5.24.7.
Checklist
4.5.25.
Timer
❱
4.5.25.1.
Theory of Operation
4.5.25.2.
Design Verification
4.5.25.3.
Testplan
4.5.25.4.
Programmer's Guide
4.5.25.5.
Hardware Interfaces
4.5.25.6.
Registers
4.5.25.7.
Device Interface Functions
4.5.25.8.
Checklist
4.5.26.
TL-UL Bus
❱
4.5.26.1.
Design Verification
4.5.26.2.
Testplan
4.5.26.3.
Protocol Checker
4.5.27.
UART
❱
4.5.27.1.
Theory of Operation
4.5.27.2.
Design Verification
4.5.27.3.
Testplan
4.5.27.4.
Programmer's Guide
4.5.27.5.
Hardware Interfaces
4.5.27.6.
Registers
4.5.27.7.
Device Interface Functions
4.5.27.8.
Checklist
4.5.28.
USB 2.0
❱
4.5.28.1.
Theory of Operation
4.5.28.2.
Design Verification
4.5.28.3.
Testplan
4.5.28.4.
Programmer's Guide
4.5.28.5.
Suspending and Resuming
4.5.28.6.
Hardware Interfaces
4.5.28.7.
Registers
4.5.28.8.
Device Interface Functions
4.5.28.9.
Checklist
4.6.
lowRISC Hardware Primitives
❱
4.6.1.
Flash Wrapper
4.6.2.
Keccak Permutation
4.6.3.
Linear Feedback Shift Register
4.6.4.
Packer
4.6.5.
Packer FIFO
4.6.6.
Present Scrambler
4.6.7.
Prince Scrambler
4.6.8.
Pseudo Random Number Generator
4.6.9.
SRAM Scrambler
4.7.
Common SystemVerilog and UVM Components
❱
4.7.1.
ALERT_ESC Agent
4.7.2.
Bus Params Package
4.7.3.
Comportable IP Testbench Architecture
4.7.4.
Common Interfaces
4.7.5.
CSR Utils
4.7.6.
CSRNG Agent
4.7.7.
DV Library Classes
4.7.8.
DV Utils
4.7.9.
FLASH_PHY_PRIM Agent
4.7.10.
I2C Agent
4.7.11.
JTAG Agent
4.7.12.
JTAG DMI Agent
4.7.13.
JTAG RISCV Agent
4.7.14.
KEY_SIDELOAD Agent
4.7.15.
KMAC_APP Agent
4.7.16.
Memory Backdoor Scoreboard
4.7.17.
Memory Backdoor Utility
4.7.18.
Memory Model
4.7.19.
PATTGEN Agent
4.7.20.
PUSH_PULL Agent
4.7.21.
PWM Monitor
4.7.22.
RNG Agent
4.7.23.
Scoreboard
4.7.24.
Simulation SRAM
4.7.25.
SPI Agent
4.7.26.
String Utils
4.7.27.
Test Vectors
4.7.28.
Tile Link Agent
4.7.29.
UART Agent
4.7.30.
USB20 Agent
5.
Security
❱
5.1.
Introduction
5.2.
Cryptography Library
❱
5.2.1.
API Documentation
5.2.2.
Security Hardening
5.2.3.
Contributing
5.3.
Implementation Guidelines
❱
5.3.1.
Secure Hardware Design Guidelines
5.3.2.
Reset vs. Non-Reset Flops
5.4.
Logical Security Model
5.5.
Security Model Specification
❱
5.5.1.
Device Attestation
5.5.2.
Device Life Cycle
5.5.3.
Device Provisioning
5.5.4.
Firmware Update
5.5.5.
Identities and Root Keys
5.5.6.
Ownership Transfer
5.5.7.
Secure Boot
5.6.
Lightweight Threat Model
6.
Software
❱
6.1.
Introduction
6.2.
Build Software
❱
6.2.1.
External dependencies
6.2.2.
RISC-V toolchain
6.2.3.
Build & Test Rules
6.2.4.
Top selection
6.2.5.
Creating a new top
6.2.6.
FPGA Bitstreams
6.3.
Device Software
❱
6.3.1.
Device Libraries
❱
6.3.1.1.
DIF Library
❱
6.3.1.1.1.
ADC Checklist
6.3.1.1.2.
AES Checklist
6.3.1.1.3.
Alert Handler Checklist
6.3.1.1.4.
Always-On Timer Checklist
6.3.1.1.5.
Clock Manager Checklist
6.3.1.1.6.
CSRNG Checklist
6.3.1.1.7.
DMA Checklist
6.3.1.1.8.
EDN Checklist
6.3.1.1.9.
Entropy Source Checklist
6.3.1.1.10.
Flash Controller Checklist
6.3.1.1.11.
GPIO Checklist
6.3.1.1.12.
HMAC Checklist
6.3.1.1.13.
I2C Checklist
6.3.1.1.14.
Key Manager Checklist
6.3.1.1.15.
Key Manager DPE Checklist
6.3.1.1.16.
KMAC Checklist
6.3.1.1.17.
Lifecycle Checklist
6.3.1.1.18.
Mailbox Checklist
6.3.1.1.19.
OTBN Checklist
6.3.1.1.20.
OTP Controller Checklist
6.3.1.1.21.
Pattern Generator Checklist
6.3.1.1.22.
Pin Multiplexer Checklist
6.3.1.1.23.
PWM Checklist
6.3.1.1.24.
Power Manager Checklist
6.3.1.1.25.
ROM Checklist
6.3.1.1.26.
Reset Manager Checklist
6.3.1.1.27.
RV Core Ibex Checklist
6.3.1.1.28.
PLIC Checklist
6.3.1.1.29.
RV Timer Checklist
6.3.1.1.30.
Sensor Controller Checklist
6.3.1.1.31.
SPI Device Checklist
6.3.1.1.32.
SPI Host Checklist
6.3.1.1.33.
SRAM Controller Checklist
6.3.1.1.34.
System Reset Controller Checklist
6.3.1.1.35.
UART Checklist
6.3.1.1.36.
USB Checklist
6.3.1.2.
OpenTitan Standard Library
❱
6.3.1.2.1.
Freestanding C Headers
6.3.1.3.
Top-Level Test Libraries
6.3.2.
Silicon Creator Software
❱
6.3.2.1.
Manufacturing Firmware
❱
6.3.2.1.1.
Test Plan
6.3.2.2.
ROM
❱
6.3.2.2.1.
ROM Specification
6.3.2.2.2.
Bootstrap
6.3.2.2.3.
Memory Protection
6.3.2.2.4.
E2E tests
6.3.2.2.5.
Root Keys
6.3.2.2.6.
Signature Verification
6.3.2.2.7.
Test Plan
6.3.2.2.8.
Signoff Test Plan
6.3.2.2.9.
Shutdown Specification
6.3.2.3.
ROM_EXT
❱
6.3.2.3.1.
ROM_EXT for Silicon Validation
6.3.2.3.2.
ROM_EXT Ownership Transfer
6.3.2.3.3.
ROM_EXT Rescue Protocol
6.3.2.3.4.
Manifest Format
6.3.2.4.
Boot Log
6.3.3.
Top-Level Tests
❱
6.3.3.1.
On-Device Test Framework
6.3.3.2.
Manufacturer Test Hooks
6.3.3.3.
Cryptotest
6.3.3.4.
Silicon Validation
❱
6.3.3.4.1.
Developer Guide
6.4.
Host Software
❱
6.4.1.
OpenTitanLib
❱
6.4.1.1.
Bitbanging
6.4.2.
OpenTitanTool
6.4.3.
OpenTitanSession
6.4.4.
OpenTitan Certificate Generator
6.4.5.
Hardware Security Module (HSM) tool
6.4.6.
Requirements
6.4.7.
Signing Guide
6.4.8.
TPM2 Test Server
7.
Working as a contributor
❱
7.1.
Getting Started
❱
7.1.1.
Workflows
7.1.2.
Design Verification
7.1.3.
Formal Verification
7.1.4.
Building (and Testing) Software
7.1.5.
Building Documentation
7.1.6.
Using OpenOCD
7.1.7.
Tools Setup
7.1.8.
FPGA Setup
7.1.9.
Verilator Setup
7.1.10.
Installing Vivado
7.1.11.
Unofficial Guides
7.1.12.
RedHat/Fedora
7.2.
Contributing
❱
7.2.1.
Detailed Contribution Guide
7.2.2.
Directory Structure
7.2.3.
Contributing to Documentation
❱
7.2.3.1.
An Example IP Block's Documentation
7.2.4.
Continuous Integration
7.2.5.
Top-Level Design and Targets
7.2.6.
GitHub Notes
7.2.7.
Bazel Notes
7.2.8.
Using the Container
7.2.9.
Contributing to Hardware
7.2.10.
Comportability
7.2.11.
RACL
7.2.12.
Hardware Design
7.2.13.
Design Methodology
7.2.14.
Vendoring in Hardware
7.2.15.
Linting
7.2.16.
Synthesis Flow
7.2.17.
Contributing to Verification
7.2.18.
Verification Methodology
7.2.19.
Security Countermeasure Verification Framework
7.2.20.
Assertions
7.2.21.
Contributing to Software
7.2.22.
Device Interface Functions
7.2.23.
Writing and Building Software for OTBN
7.2.24.
Committers
7.2.25.
RFC Process
7.3.
Contributor Guides
❱
7.3.1.
HJSON
7.3.2.
Python
7.3.3.
C & C++
7.3.4.
Markdown
7.3.5.
RISC-V Assembly
7.3.6.
OTBN Assembly
7.3.7.
Guidance for Volatile
7.3.8.
Developing on an FPGA
7.3.9.
Get a Board
7.3.10.
FPGA Reference Manual
7.3.11.
Debugging with an ILA
7.3.12.
Generalized Priority Definitions
7.3.13.
Generalized Project Milestone Definitions
7.3.14.
Hardware Development Stages
7.3.15.
Signoff Checklist
7.3.16.
Rust for Embedded C Programmers
7.4.
Tooling
❱
7.4.1.
Design-Related Tooling
7.4.2.
dvsim
7.4.3.
Design Document
7.4.4.
Testplanner
7.4.5.
Glossary
7.4.6.
fpvgen: Initial FPV Testbench Generation
7.4.7.
reggen & regtool: Register Generator
7.4.8.
Setup and use of regtool
7.4.9.
ralgen: FuseSoC UVM RAL Generator
7.4.10.
uvmdvgen: Initial Testbench Auto-generation
7.4.11.
tlgen: Crossbar Generation
7.4.12.
ipgen: Generate IP Blocks from IP Templates
7.4.13.
topgen: Top Generator
7.4.14.
vendor: Vendoring In Tool
7.4.15.
i2csvg: Generate SVGs of I2C Commands
7.4.16.
dtgen: Generate Device Tables
8.
Update this documentation
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