Testpoints
Stage | Name | Tests | Description |
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V1 | smoke | spi_host_smoke | SPI_HOST smoke test in which random (rd/wr) transactions are sent to the DUT and received asynchronously with scoreboard checks. Stimulus:
Checking:
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V1 | csr_hw_reset | spi_host_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
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V1 | csr_rw | spi_host_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
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V1 | csr_bit_bash | spi_host_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
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V1 | csr_aliasing | spi_host_csr_aliasing | Verify no aliasing within the CSR address space.
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V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
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V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw spi_host_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V1 | mem_walk | spi_host_mem_walk | Verify accessibility of all memories in the design.
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V1 | mem_partial_access | spi_host_mem_partial_access | Verify partial-accessibility of all memories in the design.
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V2 | performance | spi_host_performance | Send/receive transactions at max bandwidth Stimulus:
Checking:
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V2 | error_event_intr | spi_host_overflow_underflow spi_host_error_cmd spi_host_event | This test includes multi tasks which verify error/event interrupt assertion (except TX OVERFLOW error interrupt is verified in separate test) Stimulus:
Checking:
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V2 | clock_rate | spi_host_speed | Stimulus:
Checking:
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V2 | speed | spi_host_speed | Stimulus:
Checking:
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V2 | chip_select_timing | spi_host_speed | Stimulus:
Checking:
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V2 | sw_reset | spi_host_sw_reset | verify software reset behavior Stimulus:
Checking:
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V2 | passthrough_mode | spi_host_passthrough_mode |
Stimulus:
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V2 | cpol_cpha | spi_host_speed | Stimulus:
Checking:
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V2 | full_cycle | spi_host_speed | Stimulus:
Checking:
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V2 | duplex | spi_host_smoke | Stimulus:
Checking:
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V2 | tx_rx_only | spi_host_smoke | Stimulus:
Checking:
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V2 | stress_all | spi_host_stress_all | Support vseq (context) switching with random reset in between. Stimulus:
Checking:
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V2 | spien | spi_host_spien | Check that with mid-transaction writes to CONTROL.SPIEN, the block behaves according to the documentation.
Stimulus:
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V2 | stall | spi_host_status_stall | Stimulus:
Checking:
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V2 | Idlecsbactive | spi_host_idlecsbactive | Stimulus:
Checking:
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V2 | alert_test | spi_host_alert_test | Verify common
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V2 | intr_test | spi_host_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
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V2 | tl_d_oob_addr_access | spi_host_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | spi_host_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec
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V2 | tl_d_outstanding_access | spi_host_csr_hw_reset spi_host_csr_rw spi_host_csr_aliasing spi_host_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | spi_host_csr_hw_reset spi_host_csr_rw spi_host_csr_aliasing spi_host_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | spi_host_tl_intg_err spi_host_sec_cm | Verify that the data integrity check violation generates an alert.
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V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | Verify the countermeasure(s) BUS.INTEGRITY. |
V3 | winbond | Replace SPI agent with the Winbond Flash model Stimulus:
Checking:
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V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers. |
Covergroups
Name | Description |
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cdc_cg | Collect coverage on the relationship between the core_clk and the spi_sck to verify that both scenarios with both a slow spi_sck, a very fast spi_sck (2x core_clk) and where the two clocks are very close has been tested |
command_cg | Collect coverage that different commant settings, important cross:
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config_opts_cg | Collect coverage on the config opts register, some important crosses:
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control_cg | Collect coverage on the control register to make sure all options are excercised
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csid_cg | Collect coverage that different IDs are used. |
different_ch_settings_cg |
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duplex_cg | Collect coverage that we verified both duplex and half duplex |
error_en_cg | Collect coverage that all possible errors was enabled |
error_status_cg | Collect coverage that all possible errors was seen |
event_en_cg | Collect coverage that all events was enabled and seen |
interrupt_cg |
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interrupts_cg | Collect coverage that all types of interrupt was seen |
long_commands_cg | Collect coverage to verify that both a read and write command longer than 4 bytes was seen |
num_segment_cg |
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passthrough_cg | Check that the pass through data is transmitted instead of the data in the tx fifo.
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regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
rx_fifo_underflow_cg | Collect coverage to verify that an attempt was made to underflow the RX FIFO by attempting to read from an empty FIFO |
segment_speed_cg |
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stall_cg |
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status_cg | Collect coverage on the status register to make sure all scenarios are checked |
tl_errors_cg | Cover the following error cases on TL-UL bus:
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tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |
tx_fifo_overflow_cg | Collect coverage to verify that an attempt was made to overflow the TX FIFO by attempting to write to a full FIFO |
unaligned_data_cg | Collect coverage the alignment of writes to the data window to verify that all possible alignments was seen |