OpenTitan Documentation

SPI_HOST smoke test in which random (rd/wr) transactions are sent to the DUT and received asynchronously with scoreboard checks.

Stimulus:

• Enable spi_host ip
• Write data in standard mode - and read it back

Checking:

• Ensure transactions are transmitted/received correctly

Verify the reset values as indicated in the RAL specification.

• Write all CSRs with a random value.
• Apply reset to the DUT as well as the RAL model.
• Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify accessibility of CSRs as indicated in the RAL specification.

• Loop through each CSR to write it with a random value.
• Read the CSR back and check for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within individual bits of a CSR.

• Walk a 1 through each CSR by flipping 1 bit at a time.
• Read the CSR back and check for correctness while adhering to its access policies.
• This verify that writing a specific bit within the CSR did not affect any of the other bits.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within the CSR address space.

• Loop through each CSR to write it with a random value
• Shuffle and read ALL CSRs back.
• All CSRs except for the one that was written in this iteration should read back the previous value.
• The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify random reset during CSR/memory access.

• Run csr_rw sequence to randomly access CSRs
• If memory exists, run mem_partial_access in parallel with csr_rw
• Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.

Verify regwen CSR and its corresponding lockable CSRs.

• Randomly access all CSRs
• Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

• If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
• If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

Verify accessibility of all memories in the design.

• Run the standard UVM mem walk sequence on all memories in the RAL model.
• It is mandatory to run this test from all available interfaces the memories are accessible from.

Verify partial-accessibility of all memories in the design.

• Do partial reads and writes into the memories and verify the outcome for correctness.
• Also test outstanding access on memories

Send/receive transactions at max bandwidth

Stimulus:

• Program the content of timing fields of CONFIGOPTS to the min values
• Programming TX1_CNT and TXN_CNT to issue read/write back-to-back transactions
• Read/write rx_fifo/tx_fifo as soon as possible (avoid stalling transactions)

Checking:

• Ensure transactions are transmitted/received correctly

This test includes multi tasks which verify error/event interrupt assertion (except TX OVERFLOW error interrupt is verified in separate test)

Stimulus:

• Program ERROR_ENABLE/EVENT_ENABLE register to enable corresponding error/event interrupt assertion
• Program transaction with proper constraints to assert error/event interrupts

Checking:

• Ensure transactions are transmitted/received correctly
• Ensure the matching between the bit-field values of ERROR_STATUS and ERROR_ENABLE respectively once the error interrupt pin is asserted
• Ensure the matching between the bit-field values of ERROR_ENABLE once the event interrupt pin is asserted

Stimulus:

• select different settings for:

• CONFIGOPTS_0.CSNIDLE_0
• CONFIGOPTS_0.CSNLEAD_0
• CONFIGOPTS_0.CSNTRAIL_0

Checking:

• verify that merging of commands work correctly
• verify that the DUT can handle different sck -> cs_n timings

Stimulus:

• randomly select the DUT to run single/dual/quad mode

Checking:

• verify that all speeds are supported

Stimulus:

• Randomly select a setting for the 16bit clock divider

Checking:

• Check that the DUT operates correctly under different SPI clock speeds

verify software reset behavior

Stimulus:

• Reset the spi_host randomly after a random number of data shows up on fifos

Checking:

• Ensure that reads to RXDATA register yield 0s after the rx_fifo is reset
• Ensure that transactions are dropped in both the scoreboard and spi_agent monitor after the tx_fifo or spi_fsm is reset

• Verify the function of spi_host in passthrough_mode

Stimulus:

• Enable Passthrough Mode Checking:
• Ensure Host to Device and Device to Host paths are switched to Passthrough ports

Stimulus:

• Randomly chip select for different polarity / phase

Checking:

• Check that the DUT operates correctly under different cs_n settings

Stimulus:

• randomly select FULLCYC to be set

Checking:

• Check that the data can be read one full cycle after the data was asserted

Stimulus:

• in standard mode set the DUT to run full duplex

Checking:

• verify that the DUT support both half and full duplex in standard mode.

Stimulus:

• in standard mode enable tx only and have the env send garbage back
• in standard mode enable rx only and have the env ignore the incoming data

Checking:

• verify that the DUT ignores rx line when in tx only mode
• verify that the DUT does not drain the tx fifo in rx only mode

Support vseq (context) switching with random reset in between.

Stimulus:

• Combine the above sequences in one test to run sequentially except csr sequence and (requires zero_delays)
• Randomly add reset between each sequence

Checking:

• Ensure transactions are transmitted/received correctly
• Ensure reset is handled correctly

Check that with mid-transaction writes to CONTROL.SPIEN, the block behaves according to the documentation.

• Writing a zero to this register temporarily suspends any previously submitted transactions.
• If the block is re-enabled by writing a one to CONTROL.SPIEN, any previously executing commands will continue from wherever they left off.

Stimulus:

• Issue a transaction
• De-assert CONTROL.SPIEN after the command byte is receieved
• Re-assert after a randomized delay Checking:
• Ensure transactions are transmitted/received correctly, even with a large temporary suspension in the middle.

Stimulus:

• Ongoing transaction has stalled due to lack of available space in the RX FIFO and continues when RX fifo is cleared
• Ongoing transaction has stalled due to lack of data in the TX FIFO and continues when data is provided in TX FIFO

Checking:

• Ensure Rxstall occurs and recovers
• Ensure Txstall occurs and recovers

Stimulus:

• Pause next segment availability and idly wait for next command

Checking:

• Ensure transactions goes through even with a segment pause and idle wait in the state IdleCsbActive

Verify common alert_test CSR that allows SW to mock-inject alert requests.

• Enable a random set of alert requests by writing random value to alert_test CSR.
• Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
• During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
• Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
• Repeat the above steps a bunch of times.

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

• Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
• Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
• Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
• Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
• Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
• Repeat the above steps a bunch of times.

Access out of bounds address and verify correctness of response / behavior

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec

• TL-UL protocol error cases
  • invalid opcode
  • some mask bits not set when opcode is PutFullData
  • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
  • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
  • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
  • size is greater than 2
• OpenTitan defined error cases
  • access unmapped address, expect d_error = 1 when devmode_i == 1
  • write a CSR with unaligned address, e.g. a_address[1:0] != 0
  • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
  • write a memory with a_mask != '1 when it doesn't support partial accesses
  • read a WO (write-only) memory
  • write a RO (read-only) memory
  • write with instr_type = True

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Verify that the data integrity check violation generates an alert.

• Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
• Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs

Verify the countermeasure(s) BUS.INTEGRITY.

Replace SPI agent with the Winbond Flash model

Stimulus:

• constraint the Sequence to create welformed transactions that the model understands

Checking:

• Verify the DUT against the WindBond bfm by making the spi agent passive to verify that we comply with the spi targeted for opentitan

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Collect coverage on the relationship between the core_clk and the spi_sck to verify that both scenarios with both a slow spi_sck, a very fast spi_sck (2x core_clk) and where the two clocks are very close has been tested

Collect coverage that different commant settings, important cross:

• Direction and SPEED
• CSAAT and SPEED

Collect coverage on the config opts register, some important crosses:

• CPOL and CPHA, check all 4 combinations are tested
• CSNLEAD, CSNTRAIL and CSNIDLE

Collect coverage on the control register to make sure all options are excercised

• Tx and RX water mark should have a bin for min value, max value and one for everything in between

Collect coverage that different IDs are used.

• Check that multiple end points was running at different speeds concurrently.
• Collect coverage that multiple SPI endpoints was run with different config opts

Collect coverage that we verified both duplex and half duplex

Collect coverage that all possible errors was enabled

Collect coverage that all possible errors was seen

Collect coverage that all events was enabled and seen

• check that we see all scenarios that can cause an interrupt and that the interrupts is fired.
• also check we can clear the interrupt

Collect coverage that all types of interrupt was seen

Collect coverage to verify that both a read and write command longer than 4 bytes was seen

• Check that the DUT only transmits what is in a command even if more segments are in the TX FIFO

Check that the pass through data is transmitted instead of the data in the tx fifo.

• Cover that passthrough is activated when a normal transaction is in progress.
• Cover that data on the passthrough interface is ignored while passthroug disabled.

Cover each lockable reg field with these 2 cases:

• When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
• When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

Collect coverage to verify that an attempt was made to underflow the RX FIFO by attempting to read from an empty FIFO

• Check that we test with transactions that uses different speeds i.e first segment in standard mode, followed by segments in dual or quad mode

• Check that the DUT stalls if a command is configured to transmit data but the tx fifo is empty
• check that the data is transmitted when written to the TX fifo after a stall

Collect coverage on the status register to make sure all scenarios are checked

Cover the following error cases on TL-UL bus:

• TL-UL protocol error cases.
• OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.

Collect coverage to verify that an attempt was made to overflow the TX FIFO by attempting to write to a full FIFO

Collect coverage the alignment of writes to the data window to verify that all possible alignments was seen