Testpoints
Stage | Name | Tests | Description |
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V1 | smoke | hmac_smoke | HMAC smoke test performs a few round of HMAC or SHA256-ONLY transactions with the prodecures below:
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V1 | csr_hw_reset | hmac_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
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V1 | csr_rw | hmac_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
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V1 | csr_bit_bash | hmac_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
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V1 | csr_aliasing | hmac_csr_aliasing | Verify no aliasing within the CSR address space.
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V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
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V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw hmac_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | long_msg | hmac_long_msg | Long_msg test is based on the smoke test. The message length is between 0 and 10,000 bytes. |
V2 | back_pressure | hmac_back_pressure | Back_pressure test is based on the long_msg test. The test disabled all the protocol delays to make sure to have high chance of hitting the FIFO_FULL status. |
V2 | test_vectors | hmac_test_sha_vectors hmac_test_hmac_vectors | From NIST and IETF websites, this test intends to use HMAC and SHA test vectors to check if the reference model predicts correct data, and check if DUT returns correct data. |
V2 | burst_wr | hmac_burst_wr | Burst_wr test is based on the long_msg test. The test intends to test burst write a pre-defined size of message without any status or interrupt checking. |
V2 | datapath_stress | hmac_datapath_stress | Datapath_stress test is based on the long_msg test. It enabled HMAC and message length is set to N*64+1 in order to stress the datapath. |
V2 | error | hmac_error | This error case runs sequences that will cause interrupt bit hmac_err to set. This sequence includes:
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V2 | wipe_secret | hmac_wipe_secret | This test issues wipe_secret on hmac process datapath. Based on the smoke sequence, this sequence increases the message length, and randomly issues wipe_secret in one of the following scenarios:
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V2 | stress_all | hmac_stress_all | Stress_all test is a random mix of all the test above except csr tests. |
V2 | alert_test | hmac_alert_test | Verify common
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V2 | intr_test | hmac_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
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V2 | tl_d_oob_addr_access | hmac_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | hmac_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec
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V2 | tl_d_outstanding_access | hmac_csr_hw_reset hmac_csr_rw hmac_csr_aliasing hmac_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | hmac_csr_hw_reset hmac_csr_rw hmac_csr_aliasing hmac_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | hmac_tl_intg_err hmac_sec_cm | Verify that the data integrity check violation generates an alert.
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V2S | sec_cm_bus_integrity | hmac_tl_intg_err | Verify the countermeasure(s) BUS.INTEGRITY. |
V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | Change config registers and secret keys during msg write, make sure access is blocked. |
V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers. |
Covergroups
Name | Description |
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cfg_cg | Covers the cfg configurations below and their cross:
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err_code_cg | Covers the error scenarios below:
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msg_len_cg | Covers the length of the streamed in message. |
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
status_cg | Covers the status bits below and cross them with different configurations above:
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tl_errors_cg | Cover the following error cases on TL-UL bus:
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tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |