Testplan

Testpoints

Stage V1 Testpoints

smoke

Test: hmac_smoke

HMAC smoke test performs a few round of HMAC or SHA256-ONLY transactions with the prodecures below:

  • Set configuration register to randomly enable SHA256, hmac, endian_swap, and digest_swap
  • Set interrupt enable register to randomly enable fifo_full, hmac_done, and err_code interupts
  • Randomly read previous digest result
  • Write key
  • Trigger HMAC hash_start
  • Write HMAC message fifo with message length between 0 and 64 bytes
  • check status and interrupt
  • Trigger HMAC hash_process
  • After hmac_done interrupt, read and check digest data

csr_hw_reset

Test: hmac_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_rw

Test: hmac_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_bit_bash

Test: hmac_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_aliasing

Test: hmac_csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_mem_rw_with_rand_reset

Test: hmac_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.

regwen_csr_and_corresponding_lockable_csr

Tests:

  • hmac_csr_rw
  • hmac_csr_aliasing

Verify regwen CSR and its corresponding lockable CSRs.

  • Randomly access all CSRs
  • Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

  • If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
  • If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

Stage V2 Testpoints

long_msg

Test: hmac_long_msg

Long_msg test is based on the smoke test. The message length is between 0 and 10,000 bytes.

back_pressure

Test: hmac_back_pressure

Back_pressure test is based on the long_msg test. The test disabled all the protocol delays to make sure to have high chance of hitting the FIFO_FULL status.

test_vectors

Tests:

  • hmac_test_sha_vectors
  • hmac_test_hmac_vectors

From NIST and IETF websites, this test intends to use HMAC and SHA test vectors to check if the reference model predicts correct data, and check if DUT returns correct data.

burst_wr

Test: hmac_burst_wr

Burst_wr test is based on the long_msg test. The test intends to test burst write a pre-defined size of message without any status or interrupt checking.

datapath_stress

Test: hmac_datapath_stress

Datapath_stress test is based on the long_msg test. It enabled HMAC and message length is set to N*64+1 in order to stress the datapath.

error

Test: hmac_error

This error case runs sequences that will cause interrupt bit hmac_err to set. This sequence includes:

  • Write msg_fifo or set hash_start when sha is disabled
  • Update secret key when hash is in process
  • Set hash_start when hash is active
  • Write msg before hash_start is set

wipe_secret

Test: hmac_wipe_secret

This test issues wipe_secret on hmac process datapath. Based on the smoke sequence, this sequence increases the message length, and randomly issues wipe_secret in one of the following scenarios:

  • Before entering HMAC secret keys. This scenario represents wiping secrets when HMAC is idle.
  • Before issuing HMAC start command. This scenario represents wiping secrets when HMAC entered secret keys.
  • Before issuing HMAC process command. This scenario represents wiping secrets when HMAC is streaming in message data.
  • Before HMAC finishes hashing process. This scenario represents wiping secrets when HMAC is hashing messages and keys. Checks: The scoreboard will check if digest data are corrupted.

stress_all

Test: hmac_stress_all

Stress_all test is a random mix of all the test above except csr tests.

alert_test

Test: hmac_alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

  • Enable a random set of alert requests by writing random value to alert_test CSR.
  • Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
  • During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
  • Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
  • Repeat the above steps a bunch of times.

intr_test

Test: hmac_intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly “turn on” interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.

tl_d_oob_addr_access

Test: hmac_tl_errors

Access out of bounds address and verify correctness of response / behavior

tl_d_illegal_access

Test: hmac_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec

  • TL-UL protocol error cases
    • invalid opcode
    • some mask bits not set when opcode is PutFullData
    • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
    • address and size aren’t aligned, e.g. a_address = 0x01, a_size != 0
    • size is greater than 2
  • OpenTitan defined error cases
    • access unmapped address, expect d_error = 1 when devmode_i == 1
    • write a CSR with unaligned address, e.g. a_address[1:0] != 0
    • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • write a memory with a_mask != '1 when it doesn’t support partial accesses
    • read a WO (write-only) memory
    • write a RO (read-only) memory
    • write with instr_type = True

tl_d_outstanding_access

Tests:

  • hmac_csr_hw_reset
  • hmac_csr_rw
  • hmac_csr_aliasing
  • hmac_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

tl_d_partial_access

Tests:

  • hmac_csr_hw_reset
  • hmac_csr_rw
  • hmac_csr_aliasing
  • hmac_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Stage V2S Testpoints

tl_intg_err

Tests:

  • hmac_tl_intg_err
  • hmac_sec_cm

Verify that the data integrity check violation generates an alert.

  • Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
  • Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs

sec_cm_bus_integrity

Test: hmac_tl_intg_err

Verify the countermeasure(s) BUS.INTEGRITY.

Stage V3 Testpoints

write_config_and_secret_key_during_msg_wr

Test: hmac_smoke

Change config registers and secret keys during msg write, make sure access is blocked.

stress_all_with_rand_reset

Test: hmac_stress_all_with_rand_reset

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Covergroups

cfg_cg

Covers the cfg configurations below and their cross:

  • hmac_en
  • endian_swap
  • digest_swap

err_code_cg

Covers the error scenarios below:

  • No error.
  • Push message when sha is disabled.
  • Hash starts when sha is disabled.
  • Update secret key when hash is in progress.
  • Issue hash start again when hash in progress.
  • Push message when hmac is idle.

msg_len_cg

Covers the length of the streamed in message.

regwen_val_when_new_value_written_cg

Cover each lockable reg field with these 2 cases:

  • When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
  • When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

status_cg

Covers the status bits below and cross them with different configurations above:

  • fifo_empty
  • fifo_full
  • fifo_depth

tl_errors_cg

Cover the following error cases on TL-UL bus:

  • TL-UL protocol error cases.
  • OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.