Registers

Summary

INTR_STATE

Interrupt State Register

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "gpio", "bits": 32, "attr": ["rw1c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_ENABLE

Interrupt Enable Register

• Offset: 0x4
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "gpio", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_TEST

Interrupt Test Register

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "gpio", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ALERT_TEST

Alert Test Register

• Offset: 0xc
• Reset default: 0x80000000
• Reset mask: 0x80000001

Fields

{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}, {"name": "regwen", "bits": 1, "attr": ["rw0c"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

DATA_IN

GPIO Input data read value

• Offset: 0x10
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "DATA_IN", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DIRECT_OUT

GPIO direct output data write value

• Offset: 0x14
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "DIRECT_OUT", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MASKED_OUT_LOWER

GPIO write data lower with mask.

Masked write for DATA_OUT[15:0].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OUT[15:0] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OUT[15:0].

• Offset: 0x18
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MASKED_OUT_UPPER

GPIO write data upper with mask.

Masked write for DATA_OUT[31:16].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OUT[31:16] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OUT[31:16].

• Offset: 0x1c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DIRECT_OE

GPIO Output Enable.

Setting direct_oe[i] to 1 enables output mode for GPIO[i]

• Offset: 0x20
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "DIRECT_OE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MASKED_OE_LOWER

GPIO write Output Enable lower with mask.

Masked write for DATA_OE[15:0], the register that controls output mode for GPIO pins [15:0].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OE[15:0] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OE[15:0].

• Offset: 0x24
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MASKED_OE_UPPER

GPIO write Output Enable upper with mask.

Masked write for DATA_OE[31:16], the register that controls output mode for GPIO pins [31:16].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OE[31:16] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OE[31:16].

• Offset: 0x28
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_CTRL_EN_RISING

GPIO interrupt enable for GPIO, rising edge.

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_RISING[i] enables rising-edge interrupt detection on GPIO[i].

• Offset: 0x2c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "INTR_CTRL_EN_RISING", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_CTRL_EN_FALLING

GPIO interrupt enable for GPIO, falling edge.

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_FALLING[i] enables falling-edge interrupt detection on GPIO[i].

• Offset: 0x30
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "INTR_CTRL_EN_FALLING", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_CTRL_EN_LVLHIGH

GPIO interrupt enable for GPIO, level high.

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_LVLHIGH[i] enables level high interrupt detection on GPIO[i].

• Offset: 0x34
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "INTR_CTRL_EN_LVLHIGH", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_CTRL_EN_LVLLOW

GPIO interrupt enable for GPIO, level low.

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_LVLLOW[i] enables level low interrupt detection on GPIO[i].

• Offset: 0x38
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "INTR_CTRL_EN_LVLLOW", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CTRL_EN_INPUT_FILTER

filter enable for GPIO input bits.

If CTRL_EN_INPUT_FILTER[i] is true, a value of input bit [i] must be stable for 16 cycles before transitioning.

• Offset: 0x3c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "CTRL_EN_INPUT_FILTER", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

HW_STRAPS_DATA_IN_VALID

Indicates whether the data in HW_STRAPS_DATA_IN is valid.

• Offset: 0x40
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "HW_STRAPS_DATA_IN_VALID", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}

HW_STRAPS_DATA_IN

GPIO input data that was sampled as straps at most once after the block came out of reset.

The behavior of this register depends on the GpioAsHwStrapsEn parameter.

• If the parameter is false then the register reads as zero.
• If the parameter is true then GPIO input data is sampled after reset on the first cycle where the strap_en_i input is high. The sampled data is then stored in this register.
• Offset: 0x44
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "HW_STRAPS_DATA_IN", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_IO

Per-pin view of the output and input data of one GPIO.

This register aliases bit i of DIRECT_OUT and DATA_IN for GPIO[i]. Writing it updates only DATA_OUT[i], without affecting the other GPIOs.

• Reset default: 0x0
• Reset mask: 0x101

Instances

Fields

{"reg": [{"name": "data_out", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "data_in", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}

PER_PIN_OE_0

Per-pin view of the output enable of GPIO[0].

This register aliases bit 0 of DIRECT_OE. Writing it updates only DATA_OE[0], without affecting the other GPIOs.

• Offset: 0x200
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_0

Per-pin view of the interrupt control and input filter configuration of GPIO[0].

This register aliases bit 0 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[0], without affecting the other GPIOs. It is separate from PER_PIN_OE_0, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x204
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_1

Per-pin view of the output enable of GPIO[1].

This register aliases bit 1 of DIRECT_OE. Writing it updates only DATA_OE[1], without affecting the other GPIOs.

• Offset: 0x208
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_1

Per-pin view of the interrupt control and input filter configuration of GPIO[1].

This register aliases bit 1 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[1], without affecting the other GPIOs. It is separate from PER_PIN_OE_1, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x20c
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_2

Per-pin view of the output enable of GPIO[2].

This register aliases bit 2 of DIRECT_OE. Writing it updates only DATA_OE[2], without affecting the other GPIOs.

• Offset: 0x210
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_2

Per-pin view of the interrupt control and input filter configuration of GPIO[2].

This register aliases bit 2 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[2], without affecting the other GPIOs. It is separate from PER_PIN_OE_2, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x214
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_3

Per-pin view of the output enable of GPIO[3].

This register aliases bit 3 of DIRECT_OE. Writing it updates only DATA_OE[3], without affecting the other GPIOs.

• Offset: 0x218
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_3

Per-pin view of the interrupt control and input filter configuration of GPIO[3].

This register aliases bit 3 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[3], without affecting the other GPIOs. It is separate from PER_PIN_OE_3, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x21c
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_4

Per-pin view of the output enable of GPIO[4].

This register aliases bit 4 of DIRECT_OE. Writing it updates only DATA_OE[4], without affecting the other GPIOs.

• Offset: 0x220
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_4

Per-pin view of the interrupt control and input filter configuration of GPIO[4].

This register aliases bit 4 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[4], without affecting the other GPIOs. It is separate from PER_PIN_OE_4, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x224
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_5

Per-pin view of the output enable of GPIO[5].

This register aliases bit 5 of DIRECT_OE. Writing it updates only DATA_OE[5], without affecting the other GPIOs.

• Offset: 0x228
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_5

Per-pin view of the interrupt control and input filter configuration of GPIO[5].

This register aliases bit 5 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[5], without affecting the other GPIOs. It is separate from PER_PIN_OE_5, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x22c
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_6

Per-pin view of the output enable of GPIO[6].

This register aliases bit 6 of DIRECT_OE. Writing it updates only DATA_OE[6], without affecting the other GPIOs.

• Offset: 0x230
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_6

Per-pin view of the interrupt control and input filter configuration of GPIO[6].

This register aliases bit 6 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[6], without affecting the other GPIOs. It is separate from PER_PIN_OE_6, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x234
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_7

Per-pin view of the output enable of GPIO[7].

This register aliases bit 7 of DIRECT_OE. Writing it updates only DATA_OE[7], without affecting the other GPIOs.

• Offset: 0x238
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_7

Per-pin view of the interrupt control and input filter configuration of GPIO[7].

This register aliases bit 7 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[7], without affecting the other GPIOs. It is separate from PER_PIN_OE_7, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x23c
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_8

Per-pin view of the output enable of GPIO[8].

This register aliases bit 8 of DIRECT_OE. Writing it updates only DATA_OE[8], without affecting the other GPIOs.

• Offset: 0x240
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_8

Per-pin view of the interrupt control and input filter configuration of GPIO[8].

This register aliases bit 8 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[8], without affecting the other GPIOs. It is separate from PER_PIN_OE_8, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x244
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_9

Per-pin view of the output enable of GPIO[9].

This register aliases bit 9 of DIRECT_OE. Writing it updates only DATA_OE[9], without affecting the other GPIOs.

• Offset: 0x248
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_9

Per-pin view of the interrupt control and input filter configuration of GPIO[9].

This register aliases bit 9 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[9], without affecting the other GPIOs. It is separate from PER_PIN_OE_9, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x24c
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_10

Per-pin view of the output enable of GPIO[10].

This register aliases bit 10 of DIRECT_OE. Writing it updates only DATA_OE[10], without affecting the other GPIOs.

• Offset: 0x250
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_10

Per-pin view of the interrupt control and input filter configuration of GPIO[10].

This register aliases bit 10 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[10], without affecting the other GPIOs. It is separate from PER_PIN_OE_10, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x254
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_11

Per-pin view of the output enable of GPIO[11].

This register aliases bit 11 of DIRECT_OE. Writing it updates only DATA_OE[11], without affecting the other GPIOs.

• Offset: 0x258
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_11

Per-pin view of the interrupt control and input filter configuration of GPIO[11].

This register aliases bit 11 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[11], without affecting the other GPIOs. It is separate from PER_PIN_OE_11, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x25c
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_12

Per-pin view of the output enable of GPIO[12].

This register aliases bit 12 of DIRECT_OE. Writing it updates only DATA_OE[12], without affecting the other GPIOs.

• Offset: 0x260
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_12

Per-pin view of the interrupt control and input filter configuration of GPIO[12].

This register aliases bit 12 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[12], without affecting the other GPIOs. It is separate from PER_PIN_OE_12, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x264
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_13

Per-pin view of the output enable of GPIO[13].

This register aliases bit 13 of DIRECT_OE. Writing it updates only DATA_OE[13], without affecting the other GPIOs.

• Offset: 0x268
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_13

Per-pin view of the interrupt control and input filter configuration of GPIO[13].

This register aliases bit 13 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[13], without affecting the other GPIOs. It is separate from PER_PIN_OE_13, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x26c
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_14

Per-pin view of the output enable of GPIO[14].

This register aliases bit 14 of DIRECT_OE. Writing it updates only DATA_OE[14], without affecting the other GPIOs.

• Offset: 0x270
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_14

Per-pin view of the interrupt control and input filter configuration of GPIO[14].

This register aliases bit 14 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[14], without affecting the other GPIOs. It is separate from PER_PIN_OE_14, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x274
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_15

Per-pin view of the output enable of GPIO[15].

This register aliases bit 15 of DIRECT_OE. Writing it updates only DATA_OE[15], without affecting the other GPIOs.

• Offset: 0x278
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_15

Per-pin view of the interrupt control and input filter configuration of GPIO[15].

This register aliases bit 15 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[15], without affecting the other GPIOs. It is separate from PER_PIN_OE_15, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x27c
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_16

Per-pin view of the output enable of GPIO[16].

This register aliases bit 16 of DIRECT_OE. Writing it updates only DATA_OE[16], without affecting the other GPIOs.

• Offset: 0x280
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_16

Per-pin view of the interrupt control and input filter configuration of GPIO[16].

This register aliases bit 16 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[16], without affecting the other GPIOs. It is separate from PER_PIN_OE_16, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x284
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_17

Per-pin view of the output enable of GPIO[17].

This register aliases bit 17 of DIRECT_OE. Writing it updates only DATA_OE[17], without affecting the other GPIOs.

• Offset: 0x288
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_17

Per-pin view of the interrupt control and input filter configuration of GPIO[17].

This register aliases bit 17 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[17], without affecting the other GPIOs. It is separate from PER_PIN_OE_17, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x28c
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_18

Per-pin view of the output enable of GPIO[18].

This register aliases bit 18 of DIRECT_OE. Writing it updates only DATA_OE[18], without affecting the other GPIOs.

• Offset: 0x290
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_18

Per-pin view of the interrupt control and input filter configuration of GPIO[18].

This register aliases bit 18 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[18], without affecting the other GPIOs. It is separate from PER_PIN_OE_18, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x294
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_19

Per-pin view of the output enable of GPIO[19].

This register aliases bit 19 of DIRECT_OE. Writing it updates only DATA_OE[19], without affecting the other GPIOs.

• Offset: 0x298
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_19

Per-pin view of the interrupt control and input filter configuration of GPIO[19].

This register aliases bit 19 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[19], without affecting the other GPIOs. It is separate from PER_PIN_OE_19, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x29c
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_20

Per-pin view of the output enable of GPIO[20].

This register aliases bit 20 of DIRECT_OE. Writing it updates only DATA_OE[20], without affecting the other GPIOs.

• Offset: 0x2a0
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_20

Per-pin view of the interrupt control and input filter configuration of GPIO[20].

This register aliases bit 20 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[20], without affecting the other GPIOs. It is separate from PER_PIN_OE_20, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x2a4
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_21

Per-pin view of the output enable of GPIO[21].

This register aliases bit 21 of DIRECT_OE. Writing it updates only DATA_OE[21], without affecting the other GPIOs.

• Offset: 0x2a8
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_21

Per-pin view of the interrupt control and input filter configuration of GPIO[21].

This register aliases bit 21 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[21], without affecting the other GPIOs. It is separate from PER_PIN_OE_21, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x2ac
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_22

Per-pin view of the output enable of GPIO[22].

This register aliases bit 22 of DIRECT_OE. Writing it updates only DATA_OE[22], without affecting the other GPIOs.

• Offset: 0x2b0
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_22

Per-pin view of the interrupt control and input filter configuration of GPIO[22].

This register aliases bit 22 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[22], without affecting the other GPIOs. It is separate from PER_PIN_OE_22, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x2b4
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_23

Per-pin view of the output enable of GPIO[23].

This register aliases bit 23 of DIRECT_OE. Writing it updates only DATA_OE[23], without affecting the other GPIOs.

• Offset: 0x2b8
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_23

Per-pin view of the interrupt control and input filter configuration of GPIO[23].

This register aliases bit 23 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[23], without affecting the other GPIOs. It is separate from PER_PIN_OE_23, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x2bc
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_24

Per-pin view of the output enable of GPIO[24].

This register aliases bit 24 of DIRECT_OE. Writing it updates only DATA_OE[24], without affecting the other GPIOs.

• Offset: 0x2c0
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_24

Per-pin view of the interrupt control and input filter configuration of GPIO[24].

This register aliases bit 24 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[24], without affecting the other GPIOs. It is separate from PER_PIN_OE_24, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x2c4
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_25

Per-pin view of the output enable of GPIO[25].

This register aliases bit 25 of DIRECT_OE. Writing it updates only DATA_OE[25], without affecting the other GPIOs.

• Offset: 0x2c8
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_25

Per-pin view of the interrupt control and input filter configuration of GPIO[25].

This register aliases bit 25 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[25], without affecting the other GPIOs. It is separate from PER_PIN_OE_25, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x2cc
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_26

Per-pin view of the output enable of GPIO[26].

This register aliases bit 26 of DIRECT_OE. Writing it updates only DATA_OE[26], without affecting the other GPIOs.

• Offset: 0x2d0
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_26

Per-pin view of the interrupt control and input filter configuration of GPIO[26].

This register aliases bit 26 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[26], without affecting the other GPIOs. It is separate from PER_PIN_OE_26, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x2d4
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_27

Per-pin view of the output enable of GPIO[27].

This register aliases bit 27 of DIRECT_OE. Writing it updates only DATA_OE[27], without affecting the other GPIOs.

• Offset: 0x2d8
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_27

Per-pin view of the interrupt control and input filter configuration of GPIO[27].

This register aliases bit 27 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[27], without affecting the other GPIOs. It is separate from PER_PIN_OE_27, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x2dc
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_28

Per-pin view of the output enable of GPIO[28].

This register aliases bit 28 of DIRECT_OE. Writing it updates only DATA_OE[28], without affecting the other GPIOs.

• Offset: 0x2e0
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_28

Per-pin view of the interrupt control and input filter configuration of GPIO[28].

This register aliases bit 28 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[28], without affecting the other GPIOs. It is separate from PER_PIN_OE_28, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x2e4
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_29

Per-pin view of the output enable of GPIO[29].

This register aliases bit 29 of DIRECT_OE. Writing it updates only DATA_OE[29], without affecting the other GPIOs.

• Offset: 0x2e8
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_29

Per-pin view of the interrupt control and input filter configuration of GPIO[29].

This register aliases bit 29 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[29], without affecting the other GPIOs. It is separate from PER_PIN_OE_29, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x2ec
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_30

Per-pin view of the output enable of GPIO[30].

This register aliases bit 30 of DIRECT_OE. Writing it updates only DATA_OE[30], without affecting the other GPIOs.

• Offset: 0x2f0
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_30

Per-pin view of the interrupt control and input filter configuration of GPIO[30].

This register aliases bit 30 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[30], without affecting the other GPIOs. It is separate from PER_PIN_OE_30, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x2f4
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PER_PIN_OE_31

Per-pin view of the output enable of GPIO[31].

This register aliases bit 31 of DIRECT_OE. Writing it updates only DATA_OE[31], without affecting the other GPIOs.

• Offset: 0x2f8
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PER_PIN_INTR_CTRL_31

Per-pin view of the interrupt control and input filter configuration of GPIO[31].

This register aliases bit 31 of INTR_CTRL_EN_RISING, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVLHIGH, INTR_CTRL_EN_LVLLOW and CTRL_EN_INPUT_FILTER. Writing it updates only the configuration of GPIO[31], without affecting the other GPIOs. It is separate from PER_PIN_OE_31, so access to the output enable and to the interrupt configuration of a GPIO can be controlled independently.

• Offset: 0x2fc
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "intr_ctrl_en_rising", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_falling", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvlhigh", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "intr_ctrl_en_lvllow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ctrl_en_input_filter", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}