Registers

Summary

NameOffsetLengthDescription
uart.INTR_STATE0x04Interrupt State Register
uart.INTR_ENABLE0x44Interrupt Enable Register
uart.INTR_TEST0x84Interrupt Test Register
uart.ALERT_TEST0xc4Alert Test Register
uart.CTRL0x104UART control register
uart.STATUS0x144UART live status register
uart.RDATA0x184UART read data
uart.WDATA0x1c4UART write data
uart.FIFO_CTRL0x204UART FIFO control register
uart.FIFO_STATUS0x244UART FIFO status register
uart.OVRD0x284TX pin override control. Gives direct SW control over TX pin state
uart.VAL0x2c4UART oversampled values
uart.TIMEOUT_CTRL0x304UART RX timeout control

INTR_STATE

Interrupt State Register

  • Offset: 0x0
  • Reset default: 0x101
  • Reset mask: 0x1ff

Fields

{"reg": [{"name": "tx_watermark", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_watermark", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "tx_done", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_frame_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_break_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_timeout", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_parity_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "tx_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
BitsTypeResetNameDescription
31:9Reserved
8ro0x1tx_emptyraised if the transmit FIFO is empty.
7rw1c0x0rx_parity_errraised if the receiver has detected a parity error.
6rw1c0x0rx_timeoutraised if RX FIFO has characters remaining in the FIFO without being retrieved for the programmed time period.
5rw1c0x0rx_break_errraised if break condition has been detected on receive.
4rw1c0x0rx_frame_errraised if a framing error has been detected on receive.
3rw1c0x0rx_overflowraised if the receive FIFO has overflowed.
2rw1c0x0tx_doneraised if the transmit FIFO has emptied and no transmit is ongoing.
1ro0x0rx_watermarkraised if the receive FIFO is past the high-water mark.
0ro0x1tx_watermarkraised if the transmit FIFO is past the high-water mark.

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x1ff

Fields

{"reg": [{"name": "tx_watermark", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_watermark", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_frame_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_break_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_timeout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_parity_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_empty", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
BitsTypeResetNameDescription
31:9Reserved
8rw0x0tx_emptyEnable interrupt when INTR_STATE.tx_empty is set.
7rw0x0rx_parity_errEnable interrupt when INTR_STATE.rx_parity_err is set.
6rw0x0rx_timeoutEnable interrupt when INTR_STATE.rx_timeout is set.
5rw0x0rx_break_errEnable interrupt when INTR_STATE.rx_break_err is set.
4rw0x0rx_frame_errEnable interrupt when INTR_STATE.rx_frame_err is set.
3rw0x0rx_overflowEnable interrupt when INTR_STATE.rx_overflow is set.
2rw0x0tx_doneEnable interrupt when INTR_STATE.tx_done is set.
1rw0x0rx_watermarkEnable interrupt when INTR_STATE.rx_watermark is set.
0rw0x0tx_watermarkEnable interrupt when INTR_STATE.tx_watermark is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0x1ff

Fields

{"reg": [{"name": "tx_watermark", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_watermark", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_done", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_frame_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_break_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_timeout", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_parity_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_empty", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
BitsTypeResetNameDescription
31:9Reserved
8wo0x0tx_emptyWrite 1 to force INTR_STATE.tx_empty to 1.
7wo0x0rx_parity_errWrite 1 to force INTR_STATE.rx_parity_err to 1.
6wo0x0rx_timeoutWrite 1 to force INTR_STATE.rx_timeout to 1.
5wo0x0rx_break_errWrite 1 to force INTR_STATE.rx_break_err to 1.
4wo0x0rx_frame_errWrite 1 to force INTR_STATE.rx_frame_err to 1.
3wo0x0rx_overflowWrite 1 to force INTR_STATE.rx_overflow to 1.
2wo0x0tx_doneWrite 1 to force INTR_STATE.tx_done to 1.
1wo0x0rx_watermarkWrite 1 to force INTR_STATE.rx_watermark to 1.
0wo0x0tx_watermarkWrite 1 to force INTR_STATE.tx_watermark to 1.

ALERT_TEST

Alert Test Register

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
BitsTypeResetNameDescription
31:1Reserved
0wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.

CTRL

UART control register

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0xffff03f7

Fields

{"reg": [{"name": "TX", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RX", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "NF", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "SLPBK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LLPBK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PARITY_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PARITY_ODD", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RXBLVL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 6}, {"name": "NCO", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
BitsTypeResetName
31:16rw0x0NCO
15:10Reserved
9:8rw0x0RXBLVL
7rw0x0PARITY_ODD
6rw0x0PARITY_EN
5rw0x0LLPBK
4rw0x0SLPBK
3Reserved
2rw0x0NF
1rw0x0RX
0rw0x0TX

CTRL . NCO

BAUD clock rate control.

CTRL . RXBLVL

Trigger level for RX break detection. Sets the number of character times the line must be low to detect a break.

ValueNameDescription
0x0break22 characters
0x1break44 characters
0x2break88 characters
0x3break1616 characters

CTRL . PARITY_ODD

If PARITY_EN is true, this determines the type, 1 for odd parity, 0 for even.

CTRL . PARITY_EN

If true, parity is enabled in both RX and TX directions.

CTRL . LLPBK

Line loopback enable.

If this bit is turned on, incoming bits are forwarded to TX for testing purpose. See Block Diagram. Note that the internal design sees RX value as 1 always if line loopback is enabled.

CTRL . SLPBK

System loopback enable.

If this bit is turned on, any outgoing bits to TX are received through RX. See Block Diagram. Note that the TX line goes 1 if System loopback is enabled.

CTRL . NF

RX noise filter enable. If the noise filter is enabled, RX line goes through the 3-tap repetition code. It ignores single IP clock period noise.

CTRL . RX

RX enable

CTRL . TX

TX enable

STATUS

UART live status register

  • Offset: 0x14
  • Reset default: 0x3c
  • Reset mask: 0x3f

Fields

{"reg": [{"name": "TXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
BitsTypeResetNameDescription
31:6Reserved
5ro0x1RXEMPTYRX FIFO is empty
4ro0x1RXIDLERX is idle
3ro0x1TXIDLETX FIFO is empty and all bits have been transmitted
2ro0x1TXEMPTYTX FIFO is empty
1roxRXFULLRX buffer is full
0roxTXFULLTX buffer is full

RDATA

UART read data

  • Offset: 0x18
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

{"reg": [{"name": "RDATA", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:8Reserved
7:0roxRDATA

WDATA

UART write data

  • Offset: 0x1c
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

{"reg": [{"name": "WDATA", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:8Reserved
7:0wo0x0WDATA

FIFO_CTRL

UART FIFO control register

  • Offset: 0x20
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

{"reg": [{"name": "RXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "TXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RXILVL", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "TXILVL", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:8Reserved
7:5rw0x0TXILVL
4:2rw0x0RXILVL
1wo0x0TXRST
0wo0x0RXRST

FIFO_CTRL . TXILVL

Trigger level for TX interrupts. If the FIFO depth is less than the setting, it raises tx_watermark interrupt.

ValueNameDescription
0x0txlvl11 character
0x1txlvl22 characters
0x2txlvl44 characters
0x3txlvl88 characters
0x4txlvl1616 characters

Other values are reserved.

FIFO_CTRL . RXILVL

Trigger level for RX interrupts. If the FIFO depth is greater than or equal to the setting, it raises rx_watermark interrupt.

ValueNameDescription
0x0rxlvl11 character
0x1rxlvl22 characters
0x2rxlvl44 characters
0x3rxlvl88 characters
0x4rxlvl1616 characters
0x5rxlvl3232 characters
0x6rxlvl6262 characters

Other values are reserved.

FIFO_CTRL . TXRST

TX fifo reset. Write 1 to the register resets TX_FIFO. Read returns 0

FIFO_CTRL . RXRST

RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0

FIFO_STATUS

UART FIFO status register

  • Offset: 0x24
  • Reset default: 0x0
  • Reset mask: 0xff00ff

Fields

{"reg": [{"name": "TXLVL", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 8}, {"name": "RXLVL", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:24Reserved
23:16roxRXLVLCurrent fill level of RX fifo
15:8Reserved
7:0roxTXLVLCurrent fill level of TX fifo

OVRD

TX pin override control. Gives direct SW control over TX pin state

  • Offset: 0x28
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

{"reg": [{"name": "TXEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TXVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:2Reserved
1rw0x0TXVALWrite to set the value of the TX pin
0rw0x0TXENEnable TX pin override control

VAL

UART oversampled values

  • Offset: 0x2c
  • Reset default: 0x0
  • Reset mask: 0xffff

Fields

{"reg": [{"name": "RX", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16Reserved
15:0roxRXLast 16 oversampled values of RX. Most recent bit is bit 0, oldest 15.

TIMEOUT_CTRL

UART RX timeout control

  • Offset: 0x30
  • Reset default: 0x0
  • Reset mask: 0x80ffffff

Fields

{"reg": [{"name": "VAL", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 7}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31rw0x0ENEnable RX timeout feature
30:24Reserved
23:0rw0x0VALRX timeout value in UART bit times