OpenTitan Earl Grey (Discrete Chip) Datasheet


Top Level Block Diagram

The OpenTitan Earl Grey chip is a low-power secure microcontroller that is designed for several use cases requiring hardware security. The block diagram is shown above and shows the system configuration, including the Ibex processor and all of the memories and comportable IPs.

As can be seen in the block diagram, the system is split into a fast processor core domain that runs on a 100MHz jittery clock, and a peripheral domain that runs at 24MHz. Further, a portion of the peripheral domain, the analog sensor top and the padring can stay always-on. The rest of the system can be shut off as part of the sleep mode.

The OpenTitan Earl Grey chip provides the following features:

OpenTitan Earl Grey Features
  • RV32IMCB RISC-V "Ibex" core:
    • 3-stage pipeline, single-cycle multiplier
    • Support for the full ratified bit manipulation extension and some unratified subsets
    • 4KiB instruction cache with 2 ways
    • RISC-V compliant JTAG DM (debug module)
    • PLIC (platform level interrupt controller)
    • U/M (user/machine) execution modes
    • Enhanced Physical Memory Protection (ePMP)
    • Security features:
      • Low-latency memory scrambling on the icache
      • Dual-core lockstep configuration
      • Data independent timing
      • Dummy instruction insertion
      • Bus and register file integrity
      • Hardened PC

  • Security peripherals:
    • AES-128/192/256 with ECB/CBC/CFB/OFB/CTR modes
    • HMAC / SHA2-256
    • KMAC / SHA3-224, 256, 384, 512, [c]SHAKE-128, 256
    • Programmable big number accelerator for RSA and ECC (OTBN)
    • NIST-compliant cryptographically secure random number generator (CSRNG)
    • Digital wrapper for analog entropy source with FIPS and CC-compliant health checks
    • Key manager with DICE support
    • Manufacturing life cycle manager
    • Alert handler for handling critical security events
    • OTP controller with access controls and memory scrambling
    • Flash controller with access controls and memory scrambling
    • ROM and SRAM controllers with low-latency memory scrambling
  • Memory:
    • 2x512KiB banks eFlash
    • 128KiB main SRAM
    • 4KiB Always ON (AON) retention SRAM
    • 32KiB ROM
    • 2KiB (=16kibit) OTP

  • IO peripherals:
    • 47x multiplexable IO pads with pad control
    • 32x GPIO (using multiplexable IO)
    • 4x UART (using multiplexable IO)
    • 3x I2C with host and device modes (using multiplexable IO)
    • SPI device (using fixed IO) with TPM, generic, flash and passthrough modes
    • 2x SPI host (using both fixed and multiplexable IO)
    • USB device at full speed

  • Other peripherals:
    • Clock, reset and power management
    • Fixed-frequency timer
    • Always ON (AON) timer
    • Pulse-width modulator (PWM)
    • Pattern Generator

  • Software:
    • Boot ROM code implementing secure boot and chip configuration
    • Bare metal top-level tests
    • OpenTitan Crypto Library with OTBN accelerated standard algorithms for
      • RSA 2K, 3K, 4K
      • ECC with NIST P256/P384, Brainpool P256r1 or X25519/Ed25519
      • SHA2-256, 384, 512
    • SPHINCS+ PQ-secure boot using a stateless hash-based signatures scheme

Detailed Specification

For more detailed documentation including the pinout and system address map, see OpenTitan Earl Grey Chip Specification. The OpenTitan Earl Grey Chip DV Document describes the chip-level DV environment and contains the chip-level test plan.