Testplan

Testpoints

Stage V1 Testpoints

`smoke`

Test: alert_handler_smoke

Alert_handler smoke test with one class configured that escalates through all phases after one alert has been triggered
Check interrupt pins, alert cause CSR values, escalation pings, and crashdump_o output values
Support both synchronous and asynchronous settings

`csr_hw_reset`

Test: alert_handler_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

Write all CSRs with a random value.
Apply reset to the DUT as well as the RAL model.
Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_rw`

Test: alert_handler_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

Loop through each CSR to write it with a random value.
Read the CSR back and check for correctness while adhering to its access policies.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_bit_bash`

Test: alert_handler_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

Walk a 1 through each CSR by flipping 1 bit at a time.
Read the CSR back and check for correctness while adhering to its access policies.
This verify that writing a specific bit within the CSR did not affect any of the other bits.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_aliasing`

Test: alert_handler_csr_aliasing

Verify no aliasing within the CSR address space.

Loop through each CSR to write it with a random value
Shuffle and read ALL CSRs back.
All CSRs except for the one that was written in this iteration should read back the previous value.
The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_mem_rw_with_rand_reset`

Test: alert_handler_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

Run csr_rw sequence to randomly access CSRs
If memory exists, run mem_partial_access in parallel with csr_rw
Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
It is mandatory to run this test for all available interfaces the CSRs are accessible from.

`regwen_csr_and_corresponding_lockable_csr`

Tests:

alert_handler_csr_rw
alert_handler_csr_aliasing

Verify regwen CSR and its corresponding lockable CSRs.

Randomly access all CSRs
Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

Stage V2 Testpoints

`esc_accum`

Test: alert_handler_esc_alert_accum

Based on the smoke test, this test will focus on testing the escalation accumulation feature. So all the escalations in the test will be triggered by alert accumulation.

`esc_timeout`

Test: alert_handler_esc_intr_timeout

Based on the smoke test, this test will focus on testing the escalation timeout feature. So all the escalations in the test will be triggered by interrupt timeout.

`entropy`

Test: alert_handler_entropy

Based on the smoke test, this test enables ping testing, and check if the ping feature correctly pings all devices within certain period of time.

`sig_int_fail`

Test: alert_handler_sig_int_fail

This test will randomly inject differential pair failures on alert tx/rx pairs and the escalator tx/rx pairs. Then check if integrity failure alert is triggered and escalated.

`clk_skew`

Test: alert_handler_smoke

This test will randomly inject clock skew within the differential pairs. Then check no alert is raised.

`random_alerts`

Test: alert_handler_random_alerts

Input random alerts and randomly write phase cycles.

`random_classes`

Test: alert_handler_random_classes

Based on random_alerts test, this test will also randomly enable interrupt classes.

`ping_timeout`

Test: alert_handler_ping_timeout

Based on entropy test, this test request alert_sender and esc_receiver drivers to randomly create ping requests timeout stimulus.

Checks:

Verify interrupt pin and states.
Verify alert and local alert causes.
Verify escalation states and counts.

`lpg`

Tests:

alert_handler_lpg
alert_handler_lpg_stub_clk

Test alert_handler low_power_group(lpg) request.

Stimulus:

Randomly enabled alert_receivers’ alert_en but disable their ping response.
Turn on their low-power control by either set lpg_cg_en_i or lpg_rst_en_i. Or pause the alert_handler’s clk input for a random period of time.
Enable alert ping timeout local alert.
Run alert_handler_entropy_vseq.

Checks:

Expect no ping timeout error because the alert_receivers are disabled via low-power group, or because alert_handler’s clk input is paused due to sleep mode.

`stress_all`

Test: alert_handler_stress_all

Combine above sequences in one test to run sequentially with the following exclusions:

CSR sequences: scoreboard disabled
Ping_corner_cases sequence: included reset in the sequence

`alert_handler_entropy_stress_test`

Test: alert_handler_entropy_stress

Stress the alert_handler’s entropy request and make sure there is no spurious alert.

Stimulus:

Randomly force the wait_cyc_mask_i to a legal value to stress the ping requests.
Wait for all alerts at least being pinged for a few times. Checks:
Check alert_cause and loc_alert_cause registers to make sure there is no spurious alert being fired.

`alert_handler_alert_accum_saturation`

Test: alert_handler_alert_accum_saturation

This sequence forces all four alert classes’ accumulate counters to a large value that is close to the max saturation value. Then the sequence triggers alerts until the count saturates.

Checks:

Check accum_cnt register does not overflow, but stays at the max value.
Check the correct interrupt fires if even the count saturates.

`intr_test`

Test: alert_handler_intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
Randomly “turn on” interrupts by writing random value(s) to intr_test CSR(s).
Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
Repeat the above steps a bunch of times.

`tl_d_oob_addr_access`

Test: alert_handler_tl_errors

Access out of bounds address and verify correctness of response / behavior

`tl_d_illegal_access`

Test: alert_handler_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec

TL-UL protocol error cases
- invalid opcode
- some mask bits not set when opcode is PutFullData
- mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
- mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
- address and size aren’t aligned, e.g. a_address = 0x01, a_size != 0
- size is greater than 2
OpenTitan defined error cases
- access unmapped address, expect d_error = 1
- write a CSR with unaligned address, e.g. a_address[1:0] != 0
- write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
- write a memory with a_mask != '1 when it doesn’t support partial accesses
- read a WO (write-only) memory
- write a RO (read-only) memory
- write with instr_type = True

`tl_d_outstanding_access`

Tests:

alert_handler_csr_hw_reset
alert_handler_csr_rw
alert_handler_csr_aliasing
alert_handler_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

`tl_d_partial_access`

Tests:

alert_handler_csr_hw_reset
alert_handler_csr_rw
alert_handler_csr_aliasing
alert_handler_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Stage V2S Testpoints

`shadow_reg_update_error`

Test: alert_handler_shadow_reg_errors

Verify shadowed registers’ update error.

Randomly pick a shadowed register in the DUT.
Write it twice with different values.
Verify that the update error alert is triggered and the register value remains unchanged.
Verify the update_error status register field is set to 1.
Repeat the above steps a bunch of times.

`shadow_reg_read_clear_staged_value`

Test: alert_handler_shadow_reg_errors

Verify reading a shadowed register will clear its staged value.

Randomly pick a shadowed register in the DUT.
Write it once and read it back to clear the staged value.
Then write it twice with the same new value (but different from the previous step).
Read it back to verify the new value and ensure that the update error alert did not trigger.
Verify the update_error status register field remains the same value.
Repeat the above steps a bunch of times.

`shadow_reg_storage_error`

Test: alert_handler_shadow_reg_errors

Verify shadowed registers’ storage error.

Randomly pick a shadowed register in the DUT.
Backdoor write to shadowed or committed flops to create a storage fatal alert.
Check if fatal alert continuously fires until reset.
Verify that all other frontdoor write attempts are blocked during the storage error.
Verify that storage_error status register field is set to 1.
Reset the DUT.
Read all CSRs to ensure the DUT is properly reset.
Repeat the above steps a bunch of times.

`shadowed_reset_glitch`

Test: alert_handler_shadow_reg_errors

Verify toggle shadowed_rst_n pin can trigger storage error.

Randomly drive shadowed_rst_n pin to low or rst_n pin to low.
check if any registers have been written before the reset. If so check if storage error fatal alert is triggered.
Check status register.
Drive shadowed_rst_n pin or rst_n pin back to high.
If fatal alert is triggered, reset the DUT.
Read all CSRs to ensure the DUT is properly reset.
Repeat the above steps a bunch of times.

`shadow_reg_update_error_with_csr_rw`

Test: alert_handler_shadow_reg_errors_with_csr_rw

Run shadow_reg_update_error sequence in parallel with csr_rw sequence.

Randomly select one of the above sequences.
Apply csr_rw sequence in parallel but disable the csr_access_abort to ensure all shadowed registers’ write/read to be executed without aborting.
Repeat the above steps a bunch of times.

`tl_intg_err`

Tests:

alert_handler_tl_intg_err
alert_handler_sec_cm

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs

`sec_cm_ping_timer_lfsr_redun`

Test: alert_handler_sec_cm

Verify the countermeasure(s) PING_TIMER.LFSR.REDUN.

Stage V3 Testpoints

`stress_all_with_rand_reset`

Test: alert_handler_stress_all_with_rand_reset

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Covergroups

accum_cnt_cg

Covers escalation due to accumulated alerts.

Collect the threshold of accumulated alerts.
Collect which alert_class exceeds the accumulated count.
Cross the above coverpoints.

alert_cause_cg

Covers alert_cause register and related items.

Collect which alert causes the alert_cause register to set.
Collect the alert_class that this alert belongs to.
Cross the above coverpoints.

alert_class_regwen_cg

Covers if regwen is locked for alert_class registers.

alert_en_regwen_cg

Covers if regwen is locked for alert_en registers.

alert_handshake_complete_cg

Cover if the alert handshake completes.

alert_loc_alert_cause_cg

Covers loc_alert_cause register regarding alert.

Collect two loc_alert causes: alert_ping_fail and alert_integrity_fail.
Collect which alert triggers this loc_alert.
Collect the alert_class that this local alert belongs to.
Cross the first coverpoint with the rest of the coverpoints.

alert_lpg_cg

Covers alert lpg status during an alert request.

Cover if its lower-power-group (lpg) is enabled or disabled during an alert request.

alert_ping_with_lpg_wrap_cg

Covers ping requests are initiated with LPG enabled or disabled.

alert_trans_cg

Cover if the transaction is a ping request or an actual alert request.

class_accum_thresh_regwen_cg

Covers if regwen is locked for class_accum_thresh registers.

class_clr_regwen_cg

Covers if regwen is locked for class_clr registers.

class_crashdump_trigger_regwen_cg

Covers if regwen is locked for class_crashdump_trigger registers.

class_ctrl_regwen_cg

Covers if regwen is locked for class_ctrl registers.

class_phase_cyc_regwen_cg

Covers if regwen is locked for class_phase_cyc registers.

class_timeout_cyc_regwen_cg

Covers if regwen is locked for class_timeout_cyc registers.

clear_esc_cnt_cg

Covers escalation counter being cleared by class_clr_shadowed register.

clear_intr_cnt_cg

Covers interrupt counter being cleared by class_clr_shadowed register.

crashdump_trigger_cg

Covers which phase triggers crashdump.

cycles_bwtween_pings_cg

Covers how many cycles are there between two ping requests.

esc_handshake_complete_cg

Cover if the escalation handshake completes.

esc_loc_alert_cause_cg

Covers loc_alert_cause register regarding escalation.

Collect two loc_alert causes: esc_ping_fail and esc_integrity_fail.
Collect which escalation triggers this loc_alert.
Collect the alert_class that this local alert belongs to.
Cross the first coverpoint with the rest of the coverpoints.

esc_sig_length_cg

Covers escalation signal length for each escalation signal.

esc_trans_cg

Cover if the transaction is a ping request or an actual escalation request.

intr_timeout_cnt_cg

Covers escalation due to interrupt timeout.

Collect the threshold of interrupt timeout cycles.
Collect which alert_class exceeds the timeout threshold.
Cross the above coverpoints.

loc_alert_class_regwen_cg

Covers if regwen is locked for loc_alert_class registers.

loc_alert_en_regwen_cg

Covers if regwen is locked for loc_alert_en registers.

num_checked_pings_cg

Covers if simulation runs long enough to capture more than twenty ping requests.

num_edn_reqs_cg

Covers if simulation runs long enough to capture more than five EDN requests.

regwen_val_when_new_value_written_cg

Cover each lockable reg field with these 2 cases:

When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

shadow_field_errs_cg

Cover all shadow register errors for each register field.

For all register fields within the shadowed register, this coverpoint covers the following errors:

Update error
Storage error

tl_errors_cg

Cover the following error cases on TL-UL bus:

TL-UL protocol error cases.
OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.