Testpoints
Stage | Name | Tests | Description |
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V1 | smoke | alert_handler_smoke |
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V1 | csr_hw_reset | alert_handler_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
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V1 | csr_rw | alert_handler_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
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V1 | csr_bit_bash | alert_handler_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
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V1 | csr_aliasing | alert_handler_csr_aliasing | Verify no aliasing within the CSR address space.
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V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
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V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw alert_handler_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | esc_accum | alert_handler_esc_alert_accum | Based on the smoke test, this test will focus on testing the escalation accumulation feature. So all the escalations in the test will be triggered by alert accumulation. |
V2 | esc_timeout | alert_handler_esc_intr_timeout | Based on the smoke test, this test will focus on testing the escalation timeout feature. So all the escalations in the test will be triggered by interrupt timeout. |
V2 | entropy | alert_handler_entropy | Based on the smoke test, this test enables ping testing, and check if the ping feature correctly pings all devices within certain period of time. |
V2 | sig_int_fail | alert_handler_sig_int_fail | This test will randomly inject differential pair failures on alert tx/rx pairs and the escalator tx/rx pairs. Then check if integrity failure alert is triggered and escalated. |
V2 | clk_skew | alert_handler_smoke | This test will randomly inject clock skew within the differential pairs. Then check no alert is raised. |
V2 | random_alerts | alert_handler_random_alerts | Input random alerts and randomly write phase cycles. |
V2 | random_classes | alert_handler_random_classes | Based on random_alerts test, this test will also randomly enable interrupt classes. |
V2 | ping_timeout | alert_handler_ping_timeout | Based on entropy test, this test request alert_sender and esc_receiver drivers to randomly create ping requests timeout stimulus. Checks:
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V2 | lpg | alert_handler_lpg alert_handler_lpg_stub_clk | Test alert_handler low_power_group(lpg) request. Stimulus:
Checks:
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V2 | stress_all | alert_handler_stress_all | Combine above sequences in one test to run sequentially with the following exclusions:
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V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | Stress the alert_handler's entropy request and make sure there is no spurious alert. Stimulus:
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V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | This sequence forces all four alert classes' accumulate counters to a large value that is close to the max saturation value. Then the sequence triggers alerts until the count saturates. Checks:
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V2 | intr_test | alert_handler_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
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V2 | tl_d_oob_addr_access | alert_handler_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | alert_handler_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec
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V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset alert_handler_csr_rw alert_handler_csr_aliasing alert_handler_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | alert_handler_csr_hw_reset alert_handler_csr_rw alert_handler_csr_aliasing alert_handler_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | Verify shadowed registers' update error.
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V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | Verify reading a shadowed register will clear its staged value.
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V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | Verify shadowed registers' storage error.
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V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | Verify toggle shadowed_rst_n pin can trigger storage error.
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V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | Run shadow_reg_update_error sequence in parallel with csr_rw sequence.
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V2S | tl_intg_err | alert_handler_tl_intg_err alert_handler_sec_cm | Verify that the data integrity check violation generates an alert.
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V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | Verify the countermeasure(s) BUS.INTEGRITY. |
V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | Verify the countermeasure(s) CONFIG.SHADOW. |
V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | Verify the countermeasure(s) PING_TIMER.CONFIG.REGWEN. |
V2S | sec_cm_alert_config_regwen | alert_handler_smoke | Verify the countermeasure(s) ALERT.CONFIG.REGWEN. |
V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | Verify the countermeasure(s) ALERT_LOC.CONFIG.REGWEN. |
V2S | sec_cm_class_config_regwen | alert_handler_smoke | Verify the countermeasure(s) CLASS.CONFIG.REGWEN. |
V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | Verify the countermeasure(s) ALERT.INTERSIG.DIFF. |
V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | Verify the countermeasure(s) LPG.INTERSIG.MUBI. |
V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | Verify the countermeasure(s) ESC.INTERSIG.DIFF. |
V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | Verify the countermeasure(s) ALERT_RX.INTERSIG.BKGN_CHK. |
V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | Verify the countermeasure(s) ESC_TX.INTERSIG.BKGN_CHK. |
V2S | sec_cm_esc_rx_intersig_bkgn_chk | N/A | Verify the countermeasure(s) ESC_RX.INTERSIG.BKGN_CHK. |
V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | Verify the countermeasure(s) ESC_TIMER.FSM.SPARSE. |
V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | Verify the countermeasure(s) PING_TIMER.FSM.SPARSE. |
V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | Verify the countermeasure(s) ESC_TIMER.FSM.LOCAL_ESC. |
V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | Verify the countermeasure(s) PING_TIMER.FSM.LOCAL_ESC. |
V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | Verify the countermeasure(s) ESC_TIMER.FSM.GLOBAL_ESC. |
V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | Verify the countermeasure(s) ACCU.CTR.REDUN. |
V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | Verify the countermeasure(s) ESC_TIMER.CTR.REDUN. |
V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | Verify the countermeasure(s) PING_TIMER.CTR.REDUN. |
V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | Verify the countermeasure(s) PING_TIMER.LFSR.REDUN. |
V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers. |
Covergroups
Name | Description |
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accum_cnt_cg | Covers escalation due to accumulated alerts.
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alert_cause_cg | Covers alert_cause register and related items.
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alert_class_regwen_cg | Covers if regwen is locked for alert_class registers. |
alert_en_regwen_cg | Covers if regwen is locked for alert_en registers. |
alert_handshake_complete_cg | Cover if the alert handshake completes. |
alert_loc_alert_cause_cg | Covers loc_alert_cause register regarding alert.
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alert_lpg_cg | Covers alert lpg status during an alert request. Cover if its lower-power-group (lpg) is enabled or disabled during an alert request. |
alert_ping_with_lpg_wrap_cg | Covers ping requests are initiated with LPG enabled or disabled. |
alert_trans_cg | Cover if the transaction is a ping request or an actual alert request. |
class_accum_thresh_regwen_cg | Covers if regwen is locked for class_accum_thresh registers. |
class_clr_regwen_cg | Covers if regwen is locked for class_clr registers. |
class_crashdump_trigger_regwen_cg | Covers if regwen is locked for class_crashdump_trigger registers. |
class_ctrl_regwen_cg | Covers if regwen is locked for class_ctrl registers. |
class_phase_cyc_regwen_cg | Covers if regwen is locked for class_phase_cyc registers. |
class_timeout_cyc_regwen_cg | Covers if regwen is locked for class_timeout_cyc registers. |
clear_esc_cnt_cg | Covers escalation counter being cleared by class_clr_shadowed register. |
clear_intr_cnt_cg | Covers interrupt counter being cleared by class_clr_shadowed register. |
crashdump_trigger_cg | Covers which phase triggers crashdump. |
cycles_bwtween_pings_cg | Covers how many cycles are there between two ping requests. |
esc_handshake_complete_cg | Cover if the escalation handshake completes. |
esc_loc_alert_cause_cg | Covers loc_alert_cause register regarding escalation.
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esc_sig_length_cg | Covers escalation signal length for each escalation signal. |
esc_trans_cg | Cover if the transaction is a ping request or an actual escalation request. |
intr_timeout_cnt_cg | Covers escalation due to interrupt timeout.
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loc_alert_class_regwen_cg | Covers if regwen is locked for loc_alert_class registers. |
loc_alert_en_regwen_cg | Covers if regwen is locked for loc_alert_en registers. |
num_checked_pings_cg | Covers if simulation runs long enough to capture more than twenty ping requests. |
num_edn_reqs_cg | Covers if simulation runs long enough to capture more than five EDN requests. |
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
shadow_field_errs_cg | Cover all shadow register errors for each register field. For all register fields within the shadowed register, this coverpoint covers the following errors:
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tl_errors_cg | Cover the following error cases on TL-UL bus:
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tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |