Registers

Summary

NameOffsetLengthDescription
i2c.INTR_STATE0x04Interrupt State Register
i2c.INTR_ENABLE0x44Interrupt Enable Register
i2c.INTR_TEST0x84Interrupt Test Register
i2c.ALERT_TEST0xc4Alert Test Register
i2c.CTRL0x104I2C Control Register
i2c.STATUS0x144I2C Live Status Register for Host and Target modes
i2c.RDATA0x184I2C Read Data
i2c.FDATA0x1c4I2C Host Format Data
i2c.FIFO_CTRL0x204I2C FIFO control register
i2c.HOST_FIFO_CONFIG0x244Host mode FIFO configuration
i2c.TARGET_FIFO_CONFIG0x284Target mode FIFO configuration
i2c.HOST_FIFO_STATUS0x2c4Host mode FIFO status register
i2c.TARGET_FIFO_STATUS0x304Target mode FIFO status register
i2c.OVRD0x344I2C Override Control Register
i2c.VAL0x384Oversampled RX values
i2c.TIMING00x3c4Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
i2c.TIMING10x404Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
i2c.TIMING20x444Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
i2c.TIMING30x484Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).
i2c.TIMING40x4c4Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).
i2c.TIMEOUT_CTRL0x504I2C clock stretching timeout control.
i2c.TARGET_ID0x544I2C target address and mask pairs
i2c.ACQDATA0x584I2C target acquired data
i2c.TXDATA0x5c4I2C target transmit data
i2c.HOST_TIMEOUT_CTRL0x604I2C host clock generation timeout value (in units of input clock frequency).
i2c.TARGET_TIMEOUT_CTRL0x644I2C target internal stretching timeout control.
i2c.TARGET_NACK_COUNT0x684Number of times the I2C target has NACK’ed a new transaction since the last read of this register.
i2c.TARGET_ACK_CTRL0x6c4Controls for mid-transfer (N)ACK phase handling
i2c.ACQ_FIFO_NEXT_DATA0x704The data byte pending to be written to the ACQ FIFO.
i2c.HOST_NACK_HANDLER_TIMEOUT0x744Timeout in Host-Mode for an unhandled NACK before hardware automatically ends the transaction.
i2c.CONTROLLER_EVENTS0x784Latched events that explain why the controller halted.

INTR_STATE

Interrupt State Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x7fff

Fields

{"reg": [{"name": "fmt_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "acq_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "controller_halt", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "scl_interference", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sda_interference", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "stretch_timeout", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sda_unstable", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "cmd_complete", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "tx_stretch", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "tx_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "acq_stretch", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "unexp_stop", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "host_timeout", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
BitsTypeResetNameDescription
31:15Reserved
14rw1c0x0host_timeouttarget mode interrupt: raised if the host stops sending the clock during an ongoing transaction.
13rw1c0x0unexp_stoptarget mode interrupt: raised if STOP is received without a preceding NACK during an external host read.
12ro0x0acq_stretchtarget mode interrupt: raised if the target is stretching clocks due to full ACQ FIFO or zero count in TARGET_ACK_CTRL.NBYTES (if enabled). This is a level status interrupt.
11ro0x0tx_thresholdtarget mode interrupt: asserted whilst the TX FIFO level is below the low threshold. This is a level status interrupt.
10ro0x0tx_stretchtarget mode interrupt: raised if the target is stretching clocks for a read command. This is a level status interrupt.
9rw1c0x0cmd_completehost and target mode interrupt. In host mode, raised if the host issues a repeated START or terminates the transaction by issuing STOP. In target mode, raised if the external host issues a STOP or repeated START.
8rw1c0x0sda_unstablehost mode interrupt: raised if the target does not assert a constant value of SDA during transmission.
7rw1c0x0stretch_timeouthost mode interrupt: raised if target stretches the clock beyond the allowed timeout period
6rw1c0x0sda_interferencehost mode interrupt: raised if the SDA line goes low when host is trying to assert high
5rw1c0x0scl_interferencehost mode interrupt: raised if the SCL line drops early (not supported without clock synchronization).
4ro0x0controller_halthost mode interrupt: raised if the controller FSM is halted, such as on an unexpected NACK. Check CONTROLLER_EVENTS for the reason. The interrupt will be released when the bits in CONTROLLER_EVENTS are cleared.
3rw1c0x0rx_overflowhost mode interrupt: raised if the RX FIFO has overflowed.
2ro0x0acq_thresholdtarget mode interrupt: asserted whilst the ACQ FIFO level is above the high threshold. This is a level status interrupt.
1ro0x0rx_thresholdhost mode interrupt: asserted whilst the RX FIFO level is above the high threshold. This is a level status interrupt.
0ro0x0fmt_thresholdhost mode interrupt: asserted whilst the FMT FIFO level is below the low threshold. This is a level status interrupt.

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x7fff

Fields

{"reg": [{"name": "fmt_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "acq_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "controller_halt", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "scl_interference", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "sda_interference", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "stretch_timeout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "sda_unstable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "cmd_complete", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_stretch", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "acq_stretch", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "unexp_stop", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "host_timeout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
BitsTypeResetNameDescription
31:15Reserved
14rw0x0host_timeoutEnable interrupt when INTR_STATE.host_timeout is set.
13rw0x0unexp_stopEnable interrupt when INTR_STATE.unexp_stop is set.
12rw0x0acq_stretchEnable interrupt when INTR_STATE.acq_stretch is set.
11rw0x0tx_thresholdEnable interrupt when INTR_STATE.tx_threshold is set.
10rw0x0tx_stretchEnable interrupt when INTR_STATE.tx_stretch is set.
9rw0x0cmd_completeEnable interrupt when INTR_STATE.cmd_complete is set.
8rw0x0sda_unstableEnable interrupt when INTR_STATE.sda_unstable is set.
7rw0x0stretch_timeoutEnable interrupt when INTR_STATE.stretch_timeout is set.
6rw0x0sda_interferenceEnable interrupt when INTR_STATE.sda_interference is set.
5rw0x0scl_interferenceEnable interrupt when INTR_STATE.scl_interference is set.
4rw0x0controller_haltEnable interrupt when INTR_STATE.controller_halt is set.
3rw0x0rx_overflowEnable interrupt when INTR_STATE.rx_overflow is set.
2rw0x0acq_thresholdEnable interrupt when INTR_STATE.acq_threshold is set.
1rw0x0rx_thresholdEnable interrupt when INTR_STATE.rx_threshold is set.
0rw0x0fmt_thresholdEnable interrupt when INTR_STATE.fmt_threshold is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0x7fff

Fields

{"reg": [{"name": "fmt_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "acq_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "controller_halt", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "scl_interference", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "sda_interference", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "stretch_timeout", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "sda_unstable", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "cmd_complete", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_stretch", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "acq_stretch", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "unexp_stop", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "host_timeout", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
BitsTypeResetNameDescription
31:15Reserved
14wo0x0host_timeoutWrite 1 to force INTR_STATE.host_timeout to 1.
13wo0x0unexp_stopWrite 1 to force INTR_STATE.unexp_stop to 1.
12wo0x0acq_stretchWrite 1 to force INTR_STATE.acq_stretch to 1.
11wo0x0tx_thresholdWrite 1 to force INTR_STATE.tx_threshold to 1.
10wo0x0tx_stretchWrite 1 to force INTR_STATE.tx_stretch to 1.
9wo0x0cmd_completeWrite 1 to force INTR_STATE.cmd_complete to 1.
8wo0x0sda_unstableWrite 1 to force INTR_STATE.sda_unstable to 1.
7wo0x0stretch_timeoutWrite 1 to force INTR_STATE.stretch_timeout to 1.
6wo0x0sda_interferenceWrite 1 to force INTR_STATE.sda_interference to 1.
5wo0x0scl_interferenceWrite 1 to force INTR_STATE.scl_interference to 1.
4wo0x0controller_haltWrite 1 to force INTR_STATE.controller_halt to 1.
3wo0x0rx_overflowWrite 1 to force INTR_STATE.rx_overflow to 1.
2wo0x0acq_thresholdWrite 1 to force INTR_STATE.acq_threshold to 1.
1wo0x0rx_thresholdWrite 1 to force INTR_STATE.rx_threshold to 1.
0wo0x0fmt_thresholdWrite 1 to force INTR_STATE.fmt_threshold to 1.

ALERT_TEST

Alert Test Register

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
BitsTypeResetNameDescription
31:1Reserved
0wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.

CTRL

I2C Control Register

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0x1f

Fields

{"reg": [{"name": "ENABLEHOST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ENABLETARGET", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LLPBK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "NACK_ADDR_AFTER_TIMEOUT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ACK_CTRL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
BitsTypeResetName
31:5Reserved
4rw0x0ACK_CTRL_EN
3rw0x0NACK_ADDR_AFTER_TIMEOUT
2rw0x0LLPBK
1rw0x0ENABLETARGET
0rw0x0ENABLEHOST

CTRL . ACK_CTRL_EN

Enable I2C Target ACK Control Mode.

ACK Control Mode works together with TARGET_ACK_CTRL.NBYTES to allow software to control upper-layer protocol (N)ACKing (e.g. as in SMBus). This bit enables the mode when 1, and TARGET_ACK_CTRL.NBYTES limits how many bytes may be automatically ACK’d while the ACQ FIFO has space. If it is 0, the decision to ACK or NACK is made only from stretching timeouts and CTRL.NACK_ADDR_AFTER_TIMEOUT.

CTRL . NACK_ADDR_AFTER_TIMEOUT

Enable NACKing the address on a stretch timeout.

This is a Target mode feature. If enabled (1), a stretch timeout will cause the device to NACK the address byte. If disabled (0), a stretch timeout will cause the device to ACK the address byte. SMBus requires that devices always ACK their address, even for read commands. However, non-SMBus protocols may have a different approach and can choose to NACK instead.

Note that both cases handle data bytes the same way. For writes, the Target module will NACK all subsequent data bytes until it receives a Stop. For reads, the Target module will release SDA, causing 0xff to be returned for all data bytes until it receives a Stop.

CTRL . LLPBK

Enable I2C line loopback test If line loopback is enabled, the internal design sees ACQ and RX data as “1”

CTRL . ENABLETARGET

Enable Target I2C functionality

CTRL . ENABLEHOST

Enable Host I2C functionality

STATUS

I2C Live Status Register for Host and Target modes

  • Offset: 0x14
  • Reset default: 0x33c
  • Reset mask: 0x7ff

Fields

{"reg": [{"name": "FMTFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FMTEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "HOSTIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TARGETIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACQFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACQEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACK_CTRL_STRETCH", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
BitsTypeResetNameDescription
31:11Reserved
10roxACK_CTRL_STRETCHTarget mode stretching at (N)ACK phase due to zero count in TARGET_ACK_CTRL.NBYTES
9ro0x1ACQEMPTYTarget mode receive FIFO is empty
8ro0x1TXEMPTYTarget mode TX FIFO is empty
7roxACQFULLTarget mode receive FIFO is full
6roxTXFULLTarget mode TX FIFO is full
5ro0x1RXEMPTYHost mode RX FIFO is empty
4ro0x1TARGETIDLETarget functionality is idle. No Target transaction is in progress
3ro0x1HOSTIDLEHost functionality is idle. No Host transaction is in progress
2ro0x1FMTEMPTYHost mode FMT FIFO is empty
1roxRXFULLHost mode RX FIFO is full
0roxFMTFULLHost mode FMT FIFO is full

RDATA

I2C Read Data

  • Offset: 0x18
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

{"reg": [{"name": "RDATA", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:8Reserved
7:0roxRDATA

FDATA

I2C Host Format Data

  • Offset: 0x1c
  • Reset default: 0x0
  • Reset mask: 0x1fff

Fields

{"reg": [{"name": "FBYTE", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "READB", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RCONT", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "NAKOK", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:13Reserved
12wo0x0NAKOKDo not signal an exception if the current byte is not ACK’d
11wo0x0RCONTDo not NACK the last byte read, let the read operation continue
10wo0x0READBRead BYTE bytes from I2C. (256 if BYTE==0)
9wo0x0STOPIssue a STOP condition after this operation
8wo0x0STARTIssue a START condition before transmitting BYTE.
7:0wo0x0FBYTEFormat Byte. Directly transmitted if no flags are set.

FIFO_CTRL

I2C FIFO control register

  • Offset: 0x20
  • Reset default: 0x0
  • Reset mask: 0x183

Fields

{"reg": [{"name": "RXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "FMTRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 5}, {"name": "ACQRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "TXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:9Reserved
8wo0x0TXRSTTX FIFO reset. Write 1 to the register resets it. Read returns 0
7wo0x0ACQRSTACQ FIFO reset. Write 1 to the register resets it. Read returns 0
6:2Reserved
1wo0x0FMTRSTFMT fifo reset. Write 1 to the register resets FMT_FIFO. Read returns 0
0wo0x0RXRSTRX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0

HOST_FIFO_CONFIG

Host mode FIFO configuration

  • Offset: 0x24
  • Reset default: 0x0
  • Reset mask: 0xfff0fff

Fields

{"reg": [{"name": "RX_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}, {"name": "FMT_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:28Reserved
27:16rw0x0FMT_THRESHThreshold level for FMT interrupts. Whilst the number of used entries in the FMT FIFO is below this setting, the fmt_threshold interrupt will be asserted.
15:12Reserved
11:0rw0x0RX_THRESHThreshold level for RX interrupts. Whilst the level of data in the RX FIFO is above this setting, the rx_threshold interrupt will be asserted.

TARGET_FIFO_CONFIG

Target mode FIFO configuration

  • Offset: 0x28
  • Reset default: 0x0
  • Reset mask: 0xfff8fff

Fields

{"reg": [{"name": "TX_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "TXRST_ON_COND", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ACQ_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
BitsTypeResetNameDescription
31:28Reserved
27:16rw0x0ACQ_THRESHThreshold level for ACQ interrupts. Whilst the level of data in the ACQ FIFO is above this setting, the acq_threshold interrupt will be asserted.
15rw0x0TXRST_ON_CONDIf set, automatically reset the TX FIFO (TXRST) upon seeing a RSTART/STOP condition during an active transaction in Target Mode. This may be useful if the remaining data in the TX FIFO becomes no longer applicable to the next transaction.
14:12Reserved
11:0rw0x0TX_THRESHThreshold level for TX interrupts. Whilst the number of used entries in the TX FIFO is below this setting, the tx_threshold interrupt will be asserted.

HOST_FIFO_STATUS

Host mode FIFO status register

  • Offset: 0x2c
  • Reset default: 0x0
  • Reset mask: 0xfff0fff

Fields

{"reg": [{"name": "FMTLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "RXLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:28Reserved
27:16roxRXLVLCurrent fill level of RX fifo
15:12Reserved
11:0roxFMTLVLCurrent fill level of FMT fifo

TARGET_FIFO_STATUS

Target mode FIFO status register

  • Offset: 0x30
  • Reset default: 0x0
  • Reset mask: 0xfff0fff

Fields

{"reg": [{"name": "TXLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "ACQLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:28Reserved
27:16roxACQLVLCurrent fill level of ACQ fifo
15:12Reserved
11:0roxTXLVLCurrent fill level of TX fifo

OVRD

I2C Override Control Register

  • Offset: 0x34
  • Reset default: 0x0
  • Reset mask: 0x7

Fields

{"reg": [{"name": "TXOVRDEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SCLVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SDAVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
BitsTypeResetNameDescription
31:3Reserved
2rw0x0SDAVALValue for SDA Override. Set to 0 to drive TX Low, and set to 1 for high-Z
1rw0x0SCLVALValue for SCL Override. Set to 0 to drive TX Low, and set to 1 for high-Z
0rw0x0TXOVRDENOverride the SDA and SCL TX signals.

VAL

Oversampled RX values

  • Offset: 0x38
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "SCL_RX", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "SDA_RX", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16roxSDA_RXLast 16 oversampled values of SDA. Most recent bit is bit 16, oldest 31.
15:0roxSCL_RXLast 16 oversampled values of SCL. Most recent bit is bit 0, oldest 15.

TIMING0

Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period. These must be greater than 2 in order for the change in SCL to propagate to the input of the FSM so that acknowledgements are detected correctly.

  • Offset: 0x3c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "THIGH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TLOW", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16rw0x0TLOWThe actual time to hold SCL low between any two SCL pulses
15:0rw0x0THIGHThe actual time to hold SCL high in a given pulse: in host mode, when there is no stretching this value is 3 cycles longer as tracked in issue #18962

TIMING1

Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period.

  • Offset: 0x40
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "T_R", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "T_F", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16rw0x0T_FThe nominal fall time to anticipate for the bus (influences SDA hold times): this is currently counted twice in host mode as tracked in issue #18958
15:0rw0x0T_RThe nominal rise time to anticipate for the bus (depends on capacitance)

TIMING2

Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period.

  • Offset: 0x44
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "TSU_STA", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "THD_STA", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16rw0x0THD_STAActual hold time for start signals
15:0rw0x0TSU_STAActual setup time for repeated start signals

TIMING3

Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification). All values are expressed in units of the input clock period.

  • Offset: 0x48
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "TSU_DAT", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "THD_DAT", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16rw0x0THD_DATActual hold time for data (or ack) bits (Note, where required, the parameters TVD_DAT is taken to be THD_DAT+T_F)
15:0rw0x0TSU_DATActual setup time for data (or ack) bits

TIMING4

Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification). All values are expressed in units of the input clock period.

  • Offset: 0x4c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "TSU_STO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "T_BUF", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16rw0x0T_BUFActual time between each STOP signal and the following START signal
15:0rw0x0TSU_STOActual setup time for stop signals

TIMEOUT_CTRL

I2C clock stretching timeout control. This is used in I2C host mode to detect whether a connected target is stretching for too long.

  • Offset: 0x50
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "VAL", "bits": 31, "attr": ["rw"], "rotate": 0}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31rw0x0ENEnable timeout feature
30:0rw0x0VALClock stretching timeout value (in units of input clock frequency)

TARGET_ID

I2C target address and mask pairs

  • Offset: 0x54
  • Reset default: 0x0
  • Reset mask: 0xfffffff

Fields

{"reg": [{"name": "ADDRESS0", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "MASK0", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "ADDRESS1", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "MASK1", "bits": 7, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:28Reserved
27:21rw0x0MASK1I2C target mask number 1
20:14rw0x0ADDRESS1I2C target address number 1
13:7rw0x0MASK0I2C target mask number 0
6:0rw0x0ADDRESS0I2C target address number 0

ACQDATA

I2C target acquired data

  • Offset: 0x58
  • Reset default: 0x0
  • Reset mask: 0x7ff

Fields

{"reg": [{"name": "ABYTE", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "SIGNAL", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:11Reserved
10:8roxSIGNAL
7:0roxABYTE

ACQDATA . SIGNAL

Indicates any control symbols associated with the ABYTE.

For the STOP symbol, a stretch timeout will cause a NACK_STOP to appear in the ACQ FIFO. If the ACQ FIFO doesn’t have enough space to record a START and a STOP, the transaction will be dropped entirely on a stretch timeout. In that case, the START byte will not appear (neither as START nor NACK_START), but a standalone NACK_STOP may, if there was space. Software can discard any standalone NACK_STOP that appears.

See the associated values for more information about the contents.

ValueNameDescription
0x0NONEABYTE contains an ordinary data byte that was received and ACK’d.
0x1STARTA START condition preceded the ABYTE to start a new transaction. ABYTE contains the 7-bit I2C address plus R/W command bit in the order received on the bus, MSB first.
0x2STOPA STOP condition was received for a transaction including a transfer that addressed this Target. No transfers addressing this Target in that transaction were NACK’d. ABYTE contains no data.
0x3RESTARTA repeated START condition preceded the ABYTE, extending the current transaction with a new transfer. ABYTE contains the 7-bit I2C address plus R/W command bit in the order received on the bus, MSB first.
0x4NACKABYTE contains an ordinary data byte that was received and NACK’d.
0x5NACK_STARTA START condition preceded the ABYTE (including repeated START) that was part of a NACK’d transer. The ABYTE contains the matching I2C address and command bit. The ABYTE was ACK’d, but the rest of the transaction was NACK’ed.
0x6NACK_STOPA STOP condition was received for a transaction including a transfer that addressed this Target. A transfer addressing this Target was NACK’d. ABYTE contains no data.

Other values are reserved.

ACQDATA . ABYTE

Address for accepted transaction or acquired byte

TXDATA

I2C target transmit data

  • Offset: 0x5c
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

{"reg": [{"name": "TXDATA", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:8Reserved
7:0wo0x0TXDATA

HOST_TIMEOUT_CTRL

I2C host clock generation timeout value (in units of input clock frequency).

In an active transaction in Target-Mode, if the Controller ceases to send SCL pulses for this number of cycles then the “host_timeout” interrupt will be asserted.

Set this CSR to 0 to disable this behaviour.

  • Offset: 0x60
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "HOST_TIMEOUT_CTRL", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0HOST_TIMEOUT_CTRL

TARGET_TIMEOUT_CTRL

I2C target internal stretching timeout control. When the target has stretched beyond this time it will send a NACK for incoming data bytes or release SDA for outgoing data bytes. The behavior for the address byte is configurable via CTRL.ACK_ADDR_AFTER_TIMEOUT. Note that the count accumulates stretching time over the course of a transaction. In other words, this is equivalent to the SMBus cumulative target clock extension time.

  • Offset: 0x64
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "VAL", "bits": 31, "attr": ["rw"], "rotate": 0}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31rw0x0ENEnable timeout feature and send NACK once the timeout has been reached
30:0rw0x0VALClock stretching timeout value (in units of input clock frequency)

TARGET_NACK_COUNT

Number of times the I2C target has NACK’ed a new transaction since the last read of this register. Reading this register clears it. This is useful because when the ACQ FIFO is full the software know that a NACK has occurred, but without this register would not know how many transactions it missed. When it reaches its maximum value it will stay at that value.

  • Offset: 0x68
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

{"reg": [{"name": "TARGET_NACK_COUNT", "bits": 8, "attr": ["rc"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
BitsTypeResetNameDescription
31:8Reserved
7:0rc0x0TARGET_NACK_COUNT

TARGET_ACK_CTRL

Controls for mid-transfer (N)ACK phase handling

  • Offset: 0x6c
  • Reset default: 0x0
  • Reset mask: 0x800001ff

Fields

{"reg": [{"name": "NBYTES", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 22}, {"name": "NACK", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31woxNACK
30:9Reserved
8:0rwxNBYTES

TARGET_ACK_CTRL . NACK

When the Target module stretches on the (N)ACK phase of a Write due to TARGET_ACK_CTRL.NBYTES being 0, writing a 1 here will cause it to send a NACK.

If software chooses to NACK, note that the NACKing behavior is the same as if a stretch timeout occurred. The rest of the transaction will be NACK’d, including subsequent transfers. For the address byte, the (N)ACK phase of subsequent transfers will follow the behavior specified by CTRL.NACK_ADDR_AFTER_TIMEOUT.

Automatically clears to 0.

TARGET_ACK_CTRL . NBYTES

Remaining number of bytes the Target module may ACK automatically.

If CTRL.ACK_CTRL_EN is set to 1, the Target module will stretch the clock at the (N)ACK phase of a byte if this CSR is 0, awaiting software’s instructions.

At the beginning of each Write transfer, this byte count is reset to 0. Writes to this CSR also are only accepted while the Target module is stretching the clock. The Target module will always ACK its address if the ACQ FIFO has space. For data bytes afterwards, it will stop at the (N)ACK phase and stretch the clock when this CSR is 0. For each data byte that is ACK’d in a transaction, the byte count will decrease by 1.

Note that a full ACQ FIFO can still cause the Target module to halt at the beginning of a new byte. The ACK Control Mode provides an additional synchronization point, during the (N)ACK phase instead of after. For both cases, TARGET_TIMEOUT_CTRL applies, and stretching past the timeout will produce an automatic NACK.

This mode can be used to implement the mid-transfer (N)ACK responses required by various SMBus protocols.

ACQ_FIFO_NEXT_DATA

The data byte pending to be written to the ACQ FIFO.

This CSR is only valid while the Target module is stretching in the (N)ACK phase, indicated by STATUS.ACK_CTRL_STRETCH . It is intended to be used with ACK Control Mode, so software may check the current byte.

  • Offset: 0x70
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

{"reg": [{"name": "ACQ_FIFO_NEXT_DATA", "bits": 8, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
BitsTypeResetNameDescription
31:8Reserved
7:0roxACQ_FIFO_NEXT_DATA

HOST_NACK_HANDLER_TIMEOUT

Timeout in Host-Mode for an unhandled NACK before hardware automatically ends the transaction. (in units of input clock frequency)

If an active Controller-Transmitter transfer receives a NACK from the Target, the CONTROLLER_EVENTS.NACK bit is set. In turn, this causes the Controller FSM to halt awaiting software intervention, and the ‘controller_halt’ interrupt may assert. Software must clear the CONTROLLER_EVENTS.NACK bit to allow the state machine to continue, typically after clearing out the FMTFIFO to start a new transfer. While halted, the active transaction is not ended (no STOP (P) condition is created), and the block asserts SCL and leaves SDA released.

This timeout can be used to automatically produce a STOP condition, whether as a backstop for slow software responses (longer timeout) or as a convenience (short timeout). If the timeout expires, the Controller FSM will issue a STOP (P) condition on the bus to end the active transaction. Additionally, the CONTROLLER_EVENTS.UNHANDLED_NACK_TIMEOUT bit is set to alert software, and the FSM will return to the idle state and halt until the bit is cleared.

The enable bit must be set for this feature to operate.

  • Offset: 0x74
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "VAL", "bits": 31, "attr": ["rw"], "rotate": 0}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31rw0x0ENTimeout enable
30:0rw0x0VALUnhandled NAK timeout value (in units of input clock frequency)

CONTROLLER_EVENTS

Latched events that explain why the controller halted.

Any bits that are set must be written (with a 1) to clear the CONTROLLER_HALT interrupt.

  • Offset: 0x78
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

{"reg": [{"name": "NACK", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "UNHANDLED_NACK_TIMEOUT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}
BitsTypeResetNameDescription
31:2Reserved
1rw1c0x0UNHANDLED_NACK_TIMEOUTA Host-Mode active transaction has been ended by the HOST_NACK_HANDLER_TIMEOUT mechanism.
0rw1c0x0NACKReceived an unexpected NACK