OTBN Checklist

This checklist is for Hardware Stage transitions for the OTBN peripheral. All checklist items refer to the content in the Checklist.

Design Checklist

D1

TypeItemResolutionNote/Collaterals
DocumentationSPEC_COMPLETEDoneOTBN Design Spec. The specification is feature-complete, we were able to successfully run larger chunks of crypto code with the described feature set. At the same time, the specification has (known and unknown) issues, such as incomplete or buggy descriptions of individual instructions. These issues are being worked on as they are discovered while the design is in the D1 stage.
DocumentationCSR_DEFINEDDone
RTLCLKRST_CONNECTEDDone
RTLIP_TOPDone
RTLIP_INSTANTIABLEDone
RTLPHYSICAL_MACROS_DEFINED_80DoneThe instruction and data memories make up the majority of the memories and are instantiated. The register files are planned to be implemented in registers.
RTLFUNC_IMPLEMENTEDDone
RTLASSERT_KNOWN_ADDEDDone
Code QualityLINT_SETUPDone

D2

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURESDoneNew features are Key Sideload, Private OTBN DMem, XoShiRo PRNG and Prefetch Stage
DocumentationBLOCK_DIAGRAMDone
DocumentationDOC_INTERFACEDone
DocumentationDOC_INTEGRATION_GUIDEWaivedThis checklist item has been added retrospectively.
DocumentationMISSING_FUNCDoneAll non security features are documented
DocumentationFEATURE_FROZENDone
RTLFEATURE_COMPLETEDoneExcluding security hardening features
RTLPORT_FROZENDone
RTLARCHITECTURE_FROZENDone
RTLREVIEW_TODODone
RTLSTYLE_XDone
RTLCDC_SYNCMACRODone
Code QualityLINT_PASSDone
Code QualityCDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityRDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityAREA_CHECKDone
Code QualityTIMING_CHECKDone
SecuritySEC_CM_DOCUMENTEDDoneTwo things are not yet documented, this will be done as part of D2S: Blanking, specifying exactly what is blanked. Loop stack hardening, there are a couple of options to discuss.

D2S

TypeItemResolutionNote/Collaterals
SecuritySEC_CM_ASSETS_LISTEDDone
SecuritySEC_CM_IMPLEMENTEDDone
SecuritySEC_CM_RND_CNSTDone
SecuritySEC_CM_NON_RESET_FLOPSDone
SecuritySEC_CM_SHADOW_REGSDone
SecuritySEC_CM_RTL_REVIEWEDDone
SecuritySEC_CM_COUNCIL_REVIEWEDDone

D3

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURES_D3Not Started
RTLTODO_COMPLETENot Started
Code QualityLINT_COMPLETENot Started
Code QualityCDC_COMPLETENot Started
Code QualityRDC_COMPLETENot Started
ReviewREVIEW_RTLNot Started
ReviewREVIEW_DELETED_FFNot Started
ReviewREVIEW_SW_CHANGENot Started
ReviewREVIEW_SW_ERRATANot Started
ReviewReviewer(s)Not Started
ReviewSignoff dateNot Started

Verification Checklist

V1

TypeItemResolutionNote/Collaterals
DocumentationDV_DOC_DRAFT_COMPLETEDDoneOTBN DV document
DocumentationTESTPLAN_COMPLETEDDoneOTBN Testplan
TestbenchTB_TOP_CREATEDDone
TestbenchPRELIMINARY_ASSERTION_CHECKS_ADDEDDone
TestbenchSIM_TB_ENV_CREATEDDone
TestbenchSIM_RAL_MODEL_GEN_AUTOMATEDDone
TestbenchCSR_CHECK_GEN_AUTOMATEDDone
TestbenchTB_GEN_AUTOMATEDN/A
TestsSIM_SMOKE_TEST_PASSINGDone
TestsSIM_CSR_MEM_TEST_SUITE_PASSINGDone
TestsFPV_MAIN_ASSERTIONS_PROVENN/A
Tool SetupSIM_ALT_TOOL_SETUPDoneAlt tool: xcelium
RegressionSIM_SMOKE_REGRESSION_SETUPDone
RegressionSIM_NIGHTLY_REGRESSION_SETUPDone
RegressionFPV_REGRESSION_SETUPN/A
CoverageSIM_COVERAGE_MODEL_ADDEDDone
Code QualityTB_LINT_SETUPDone
IntegrationPRE_VERIFIED_SUB_MODULES_V1N/A
ReviewDESIGN_SPEC_REVIEWEDDone
ReviewTESTPLAN_REVIEWEDDone
ReviewSTD_TEST_CATEGORIES_PLANNEDDoneException (Debug)
ReviewV2_CHECKLIST_SCOPEDDone

V2

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V2Not Started
DocumentationDV_DOC_COMPLETEDNot Started
TestbenchFUNCTIONAL_COVERAGE_IMPLEMENTEDNot Started
TestbenchALL_INTERFACES_EXERCISEDNot Started
TestbenchALL_ASSERTION_CHECKS_ADDEDNot Started
TestbenchSIM_TB_ENV_COMPLETEDNot Started
TestsSIM_ALL_TESTS_PASSINGNot Started
TestsFPV_ALL_ASSERTIONS_WRITTENNot Started
TestsFPV_ALL_ASSUMPTIONS_REVIEWEDNot Started
TestsSIM_FW_SIMULATEDNot Started
RegressionSIM_NIGHTLY_REGRESSION_V2Not Started
CoverageSIM_CODE_COVERAGE_V2Not Started
CoverageSIM_FUNCTIONAL_COVERAGE_V2Not Started
CoverageFPV_CODE_COVERAGE_V2Not Started
CoverageFPV_COI_COVERAGE_V2Not Started
IntegrationPRE_VERIFIED_SUB_MODULES_V2Not Started
IssuesNO_HIGH_PRIORITY_ISSUES_PENDINGNot Started
IssuesALL_LOW_PRIORITY_ISSUES_ROOT_CAUSEDNot Started
ReviewDV_DOC_TESTPLAN_REVIEWEDNot Started
ReviewV3_CHECKLIST_SCOPEDNot Started

V2S

TypeItemResolutionNote/Collaterals
DocumentationSEC_CM_TESTPLAN_COMPLETEDDone
TestsFPV_SEC_CM_VERIFIEDDone
TestsSIM_SEC_CM_VERIFIEDDone
CoverageSIM_COVERAGE_REVIEWEDDone
ReviewSEC_CM_DV_REVIEWEDDone11 Oct 2022

V3

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V3Not Started
TestsX_PROP_ANALYSIS_COMPLETEDNot Started
TestsFPV_ASSERTIONS_PROVEN_AT_V3Not Started
RegressionSIM_NIGHTLY_REGRESSION_AT_V3Not Started
CoverageSIM_CODE_COVERAGE_AT_100Not Started
CoverageSIM_FUNCTIONAL_COVERAGE_AT_100Not Started
CoverageFPV_CODE_COVERAGE_AT_100Not Started
CoverageFPV_COI_COVERAGE_AT_100Not Started
Code QualityALL_TODOS_RESOLVEDNot Started
Code QualityNO_TOOL_WARNINGS_THROWNNot Started
Code QualityTB_LINT_COMPLETENot Started
IntegrationPRE_VERIFIED_SUB_MODULES_V3Not Started
IssuesNO_ISSUES_PENDINGNot Started
ReviewReviewer(s)Not Started
ReviewSignoff dateNot Started