OTBN Checklist

This checklist is for Hardware Stage transitions for the OTBN peripheral. All checklist items refer to the content in the Checklist.

Design Checklist

Type	Item	Resolution	Note/Collaterals
Documentation	SPEC_COMPLETE	Done	OTBN Design Spec. The specification is feature-complete, we were able to successfully run larger chunks of crypto code with the described feature set. At the same time, the specification has (known and unknown) issues, such as incomplete or buggy descriptions of individual instructions. These issues are being worked on as they are discovered while the design is in the D1 stage.
Documentation	CSR_DEFINED	Done
RTL	CLKRST_CONNECTED	Done
RTL	IP_TOP	Done
RTL	IP_INSTANTIABLE	Done
RTL	PHYSICAL_MACROS_DEFINED_80	Done	The instruction and data memories make up the majority of the memories and are instantiated. The register files are planned to be implemented in registers.
RTL	FUNC_IMPLEMENTED	Done
RTL	ASSERT_KNOWN_ADDED	Done
Code Quality	LINT_SETUP	Done

Type	Item	Resolution	Note/Collaterals
Documentation	NEW_FEATURES	Done	New features are Key Sideload, Private OTBN DMem, XoShiRo PRNG and Prefetch Stage
Documentation	BLOCK_DIAGRAM	Done
Documentation	DOC_INTERFACE	Done
Documentation	DOC_INTEGRATION_GUIDE	Waived	This checklist item has been added retrospectively.
Documentation	MISSING_FUNC	Done	All non security features are documented
Documentation	FEATURE_FROZEN	Done
RTL	FEATURE_COMPLETE	Done	Excluding security hardening features
RTL	PORT_FROZEN	Done
RTL	ARCHITECTURE_FROZEN	Done
RTL	REVIEW_TODO	Done
RTL	STYLE_X	Done
RTL	CDC_SYNCMACRO	Done
Code Quality	LINT_PASS	Done
Code Quality	CDC_SETUP	Waived	No block-level flow available - waived to top-level signoff.
Code Quality	RDC_SETUP	Waived	No block-level flow available - waived to top-level signoff.
Code Quality	AREA_CHECK	Done
Code Quality	TIMING_CHECK	Done
Security	SEC_CM_DOCUMENTED	Done	Two things are not yet documented, this will be done as part of D2S: Blanking, specifying exactly what is blanked. Loop stack hardening, there are a couple of options to discuss.

Type	Item	Resolution
Security	SEC_CM_ASSETS_LISTED	Done
Security	SEC_CM_IMPLEMENTED	Done
Security	SEC_CM_RND_CNST	Done
Security	SEC_CM_NON_RESET_FLOPS	Done
Security	SEC_CM_SHADOW_REGS	Done
Security	SEC_CM_RTL_REVIEWED	Done
Security	SEC_CM_COUNCIL_REVIEWED	Done

Type	Item	Resolution
Documentation	NEW_FEATURES_D3	Not Started
RTL	TODO_COMPLETE	Not Started
Code Quality	LINT_COMPLETE	Not Started
Code Quality	CDC_COMPLETE	Not Started
Code Quality	RDC_COMPLETE	Not Started
Review	REVIEW_RTL	Not Started
Review	REVIEW_DELETED_FF	Not Started
Review	REVIEW_SW_CHANGE	Not Started
Review	REVIEW_SW_ERRATA	Not Started
Review	Reviewer(s)	Not Started
Review	Signoff date	Not Started

Type	Item	Resolution	Note/Collaterals
Documentation	DV_DOC_DRAFT_COMPLETED	Done	OTBN DV document
Documentation	TESTPLAN_COMPLETED	Done	OTBN Testplan
Testbench	TB_TOP_CREATED	Done
Testbench	PRELIMINARY_ASSERTION_CHECKS_ADDED	Done
Testbench	SIM_TB_ENV_CREATED	Done
Testbench	SIM_RAL_MODEL_GEN_AUTOMATED	Done
Testbench	CSR_CHECK_GEN_AUTOMATED	Done
Testbench	TB_GEN_AUTOMATED	N/A
Tests	SIM_SMOKE_TEST_PASSING	Done
Tests	SIM_CSR_MEM_TEST_SUITE_PASSING	Done
Tests	FPV_MAIN_ASSERTIONS_PROVEN	N/A
Tool Setup	SIM_ALT_TOOL_SETUP	Done	Alt tool: xcelium
Regression	SIM_SMOKE_REGRESSION_SETUP	Done
Regression	SIM_NIGHTLY_REGRESSION_SETUP	Done
Regression	FPV_REGRESSION_SETUP	N/A
Coverage	SIM_COVERAGE_MODEL_ADDED	Done
Code Quality	TB_LINT_SETUP	Done
Integration	PRE_VERIFIED_SUB_MODULES_V1	N/A
Review	DESIGN_SPEC_REVIEWED	Done
Review	TESTPLAN_REVIEWED	Done
Review	STD_TEST_CATEGORIES_PLANNED	Done	Exception (Debug)
Review	V2_CHECKLIST_SCOPED	Done

Type	Item	Resolution
Documentation	DESIGN_DELTAS_CAPTURED_V2	Not Started
Documentation	DV_DOC_COMPLETED	Not Started
Testbench	FUNCTIONAL_COVERAGE_IMPLEMENTED	Not Started
Testbench	ALL_INTERFACES_EXERCISED	Not Started
Testbench	ALL_ASSERTION_CHECKS_ADDED	Not Started
Testbench	SIM_TB_ENV_COMPLETED	Not Started
Tests	SIM_ALL_TESTS_PASSING	Not Started
Tests	FPV_ALL_ASSERTIONS_WRITTEN	Not Started
Tests	FPV_ALL_ASSUMPTIONS_REVIEWED	Not Started
Tests	SIM_FW_SIMULATED	Not Started
Regression	SIM_NIGHTLY_REGRESSION_V2	Not Started
Coverage	SIM_CODE_COVERAGE_V2	Not Started
Coverage	SIM_FUNCTIONAL_COVERAGE_V2	Not Started
Coverage	FPV_CODE_COVERAGE_V2	Not Started
Coverage	FPV_COI_COVERAGE_V2	Not Started
Integration	PRE_VERIFIED_SUB_MODULES_V2	Not Started
Issues	NO_HIGH_PRIORITY_ISSUES_PENDING	Not Started
Issues	ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED	Not Started
Review	DV_DOC_TESTPLAN_REVIEWED	Not Started
Review	V3_CHECKLIST_SCOPED	Not Started

Type	Item	Resolution	Note/Collaterals
Documentation	SEC_CM_TESTPLAN_COMPLETED	Done
Tests	FPV_SEC_CM_VERIFIED	Done
Tests	SIM_SEC_CM_VERIFIED	Done
Coverage	SIM_COVERAGE_REVIEWED	Done
Review	SEC_CM_DV_REVIEWED	Done	11 Oct 2022

Type	Item	Resolution
Documentation	DESIGN_DELTAS_CAPTURED_V3	Not Started
Tests	X_PROP_ANALYSIS_COMPLETED	Not Started
Tests	FPV_ASSERTIONS_PROVEN_AT_V3	Not Started
Regression	SIM_NIGHTLY_REGRESSION_AT_V3	Not Started
Coverage	SIM_CODE_COVERAGE_AT_100	Not Started
Coverage	SIM_FUNCTIONAL_COVERAGE_AT_100	Not Started
Coverage	FPV_CODE_COVERAGE_AT_100	Not Started
Coverage	FPV_COI_COVERAGE_AT_100	Not Started
Code Quality	ALL_TODOS_RESOLVED	Not Started
Code Quality	NO_TOOL_WARNINGS_THROWN	Not Started
Code Quality	TB_LINT_COMPLETE	Not Started
Integration	PRE_VERIFIED_SUB_MODULES_V3	Not Started
Issues	NO_ISSUES_PENDING	Not Started
Review	Reviewer(s)	Not Started
Review	Signoff date	Not Started