HMAC Checklist

This checklist is for Hardware Stage transitions for the HMAC peripheral. All checklist items refer to the content in the Checklist.

Design Checklist

D1

TypeItemResolutionNote/Collaterals
DocumentationSPEC_COMPLETEDoneHMAC Spec
DocumentationCSR_DEFINEDDone
RTLCLKRST_CONNECTEDDone
RTLIP_TOPDone
RTLIP_INSTANTIABLEDone
RTLPHYSICAL_MACROS_DEFINED_80Done
RTLFUNC_IMPLEMENTEDDone
RTLASSERT_KNOWN_ADDEDDone
Code QualityLINT_SETUPDone

D2

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURESDoneLivestream was added
DocumentationBLOCK_DIAGRAMDone
DocumentationDOC_INTERFACEDone
Documentation[DOC_INTEGRATION_GUIDE][]WaivedThis checklist item has been added retrospectively.
DocumentationMISSING_FUNCN/A
DocumentationFEATURE_FROZENDone
RTLFEATURE_COMPLETEDone
RTLPORT_FROZENDoneInterrupt port was revised.
RTLARCHITECTURE_FROZENDoneLivestream was added
RTLREVIEW_TODODoneRemoved irrelevant TODOs and create #761
RTLSTYLE_XDone
RTLCDC_SYNCMACRON/A
Code QualityLINT_PASSDone
Code QualityCDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code Quality[RDC_SETUP][]WaivedNo block-level flow available - waived to top-level signoff.
Code QualityAREA_CHECKDone
Code Quality[TIMING_CHECK][]DoneFmax @ 50MHz on NexysVideo
SecuritySEC_CM_DOCUMENTEDN/A

D2S

TypeItemResolutionNote/Collaterals
SecuritySEC_CM_ASSETS_LISTEDDone
SecuritySEC_CM_IMPLEMENTEDDone
SecuritySEC_CM_RND_CNSTN/A
SecuritySEC_CM_NON_RESET_FLOPSN/A
SecuritySEC_CM_SHADOW_REGSN/A
SecuritySEC_CM_RTL_REVIEWEDN/A
SecuritySEC_CM_COUNCIL_REVIEWEDN/AThis block only contains the bus-integrity CM.

D3

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURES_D3Not started
RTLTODO_COMPLETENot started
Code QualityLINT_COMPLETENot started
Code QualityCDC_COMPLETENot started
Code QualityRDC_COMPLETENot started
ReviewREVIEW_RTLNot started
ReviewREVIEW_DELETED_FFNot started
ReviewREVIEW_SW_CHANGENot started
ReviewREVIEW_SW_ERRATANot started
ReviewReviewer(s)Not started
ReviewSignoff dateNot started

Verification Checklist

V1

TypeItemResolutionNote/Collaterals
DocumentationDV_DOC_DRAFT_COMPLETEDDonehmac_dv_doc
DocumentationTESTPLAN_COMPLETEDDone
TestbenchTB_TOP_CREATEDDone
TestbenchPRELIMINARY_ASSERTION_CHECKS_ADDEDDone
TestbenchSIM_TB_ENV_CREATEDDone
TestbenchSIM_RAL_MODEL_GEN_AUTOMATEDDone
TestbenchCSR_CHECK_GEN_AUTOMATEDwaivedRevisit later. Tool setup in progress.
TestbenchTB_GEN_AUTOMATEDN/A
TestsSIM_SMOKE_TEST_PASSINGDone
TestsSIM_CSR_MEM_TEST_SUITE_PASSINGDone
TestsFPV_MAIN_ASSERTIONS_PROVENN/A
Tool SetupSIM_ALT_TOOL_SETUPDone
RegressionSIM_SMOKE_REGRESSION_SETUPDone w/ waiversException (implemented in local)
RegressionSIM_NIGHTLY_REGRESSION_SETUPDone w/ waiversException (implemented in local)
RegressionFPV_REGRESSION_SETUPN/A
CoverageSIM_COVERAGE_MODEL_ADDEDDone
Code QualityTB_LINT_SETUPDone
IntegrationPRE_VERIFIED_SUB_MODULES_V1N/AExcept for IP module
ReviewDESIGN_SPEC_REVIEWEDDone
ReviewTESTPLAN_REVIEWEDDone
ReviewSTD_TEST_CATEGORIES_PLANNEDDoneException (Security, Power, Debug)
ReviewV2_CHECKLIST_SCOPEDDone

V2

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V2Done
DocumentationDV_DOC_COMPLETEDDone
TestbenchFUNCTIONAL_COVERAGE_IMPLEMENTEDDone
TestbenchALL_INTERFACES_EXERCISEDDone
TestbenchALL_ASSERTION_CHECKS_ADDEDDoneIt would be best to add more DV assertions, OK to move it to M5
TestbenchSIM_TB_ENV_COMPLETEDDone
TestsFPV_ALL_ASSERTIONS_WRITTENN/A
TestsFPV_ALL_ASSUMPTIONS_REVIEWEDN/A
TestsSIM_ALL_TESTS_PASSINGDoneNote: that 1 test marked as V3 is not passing
TestsSIM_FW_SIMULATEDN/A
RegressionSIM_NIGHTLY_REGRESSION_V2Done
CoverageSIM_CODE_COVERAGE_V2DoneNote: once PR #23116 will be merged to confirm the results
CoverageSIM_FUNCTIONAL_COVERAGE_V2DoneNote: once PR #23116 will be merged to confirm the results
CoverageFPV_CODE_COVERAGE_V2N/A
CoverageFPV_COI_COVERAGE_V2N/A
IntegrationPRE_VERIFIED_SUB_MODULES_V2N/A
IssuesNO_HIGH_PRIORITY_ISSUES_PENDINGDone
IssuesALL_LOW_PRIORITY_ISSUES_ROOT_CAUSEDDone
ReviewDV_DOC_TESTPLAN_REVIEWEDDone
ReviewV3_CHECKLIST_SCOPEDDone

V2S

TypeItemResolutionNote/Collaterals
DocumentationSEC_CM_TESTPLAN_COMPLETEDDone
TestsFPV_SEC_CM_VERIFIEDN/A
TestsSIM_SEC_CM_VERIFIEDDone
CoverageSIM_COVERAGE_REVIEWEDDone
ReviewSEC_CM_DV_REVIEWEDDoneWaived the design has only 1 standard countermeasure - bus integrity

V3

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V3Not started
TestsX_PROP_ANALYSIS_COMPLETEDNot started
TestsFPV_ASSERTIONS_PROVEN_AT_V3Not started
RegressionSIM_NIGHTLY_REGRESSION_AT_V3Not started
CoverageSIM_CODE_COVERAGE_AT_100Not started
CoverageSIM_FUNCTIONAL_COVERAGE_AT_100Not started
CoverageFPV_CODE_COVERAGE_AT_100Not started
CoverageFPV_COI_COVERAGE_AT_100Not started
Code QualityALL_TODOS_RESOLVEDNot started
Code QualityNO_TOOL_WARNINGS_THROWNNot started
Code QualityTB_LINT_COMPLETENot started
IntegrationPRE_VERIFIED_SUB_MODULES_V3Not started
IssuesNO_ISSUES_PENDINGNot started
ReviewReviewer(s)Not started
ReviewSignoff dateNot started