Top Darjeeling

Specification

The datasheet and specification of Darjeeling is located here.

Memory Map

The base addresses of the memory and peripherals are defined in this table.

The choice of memory, or lack thereof at location 0x0 confers two exclusive benefits:

• If there are no memories at location 0x0, then null pointers will immediately error and be noticed by software (the xbar will fail to decode and route)
• If SRAM is placed at 0, accesses to data located within 2KB of 0x0 can be accomplished with a single instruction and thus reduce code size.

For the purpose of top_darjeeling, the first option has been chosen to benefit software development and testing.

Tooling to generate RTL, DV, and SW code

Large parts of Darjeeling’s code is generated by topgen and ipgen based on configuration and template files. Please do not edit autogenerated code files directly. Please see the documentation of topgen and ipgen as well as the usage examples for Earlgrey for how to work with the tooling as well as configuration and template files.