TL-UL Checklist

This checklist is for Hardware Stage transitions for the TL-UL component. All checklist items refer to the content in the Checklist.

Design Checklist

D1

TypeItemResolutionNote/Collaterals
DocumentationSPEC_COMPLETEDoneTL-UL Spec crossbar_tool
DocumentationCSR_DEFINEDN/A
RTLCLKRST_CONNECTEDDone
RTLIP_TOPDone
RTLIP_INSTANTIABLEDone
RTLPHYSICAL_MACROS_DEFINED_80N/A
RTLFUNC_IMPLEMENTEDDone
RTLASSERT_KNOWN_ADDEDDone
Code QualityLINT_SETUPDone

D2

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURESN/A
DocumentationBLOCK_DIAGRAMDone
DocumentationDOC_INTERFACEN/A
DocumentationDOC_INTEGRATION_GUIDEWaivedThis checklist item has been added retrospectively.
DocumentationMISSING_FUNCN/A
DocumentationFEATURE_FROZENDone
RTLFEATURE_COMPLETEDone
RTLPORT_FROZENDoneTargeting for current top_earlgrey( Port can be changed later based on top_earlgrey config)
RTLARCHITECTURE_FROZENDone
RTLREVIEW_TODODonePR #837 is pending
RTLSTYLE_XDone
RTLCDC_SYNCMACRON/A
Code QualityLINT_PASSDone
Code QualityCDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityRDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityAREA_CHECKDone
Code QualityTIMING_CHECKDonePipeline inserted in front of Core IBEX. meet timing @ 50MHz on NexysVideo
SecuritySEC_CM_DOCUMENTEDN/A

D2S

TypeItemResolutionNote/Collaterals
SecuritySEC_CM_ASSETS_LISTEDNot Started
SecuritySEC_CM_IMPLEMENTEDNot Started
SecuritySEC_CM_RND_CNSTNot Started
SecuritySEC_CM_NON_RESET_FLOPSNot Started
SecuritySEC_CM_SHADOW_REGSNot Started
SecuritySEC_CM_RTL_REVIEWEDNot Started
SecuritySEC_CM_COUNCIL_REVIEWEDNot Started

D3

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURES_D3N/A
RTLTODO_COMPLETEDoneResolved: #837
Code QualityLINT_COMPLETEDone
Code QualityCDC_COMPLETEN/A
Code QualityRDC_COMPLETENot Started
ReviewREVIEW_RTLDone1st @tjaychen / 2nd @martin-lueker
ReviewREVIEW_DELETED_FFN/A
ReviewREVIEW_SW_CHANGEN/A
ReviewREVIEW_SW_ERRATADone
ReviewReviewer(s)Done@weicaiyang @tjaychen
ReviewSignoff dateDone2019-11-07

Verification Checklist

V1

TypeItemResolutionNote/Collaterals
DocumentationDV_DOC_DRAFT_COMPLETEDDoneXBAR DV document
DocumentationTESTPLAN_COMPLETEDDoneXBAR Testplan
TestbenchTB_TOP_CREATEDDone
TestbenchPRELIMINARY_ASSERTION_CHECKS_ADDEDDone
TestbenchTB_ENV_CREATEDDone
TestbenchRAL_MODEL_GEN_AUTOMATEDN/A
TestbenchTB_GEN_AUTOMATEDWaivedManually generated. Planned to automate later
TestsSMOKE_TEST_PASSINGDone
TestsCSR_MEM_TEST_SUITE_PASSINGN/A
Tool SetupALT_TOOL_SETUPDone
RegressionSMOKE_REGRESSION_SETUPDoneException (Runs at local)
RegressionNIGHTLY_REGRESSION_SETUPDoneException (Runs at local)
CoverageCOVERAGE_MODEL_ADDEDDone
Code QualityTB_LINT_SETUPDone
IntegrationPRE_VERIFIED_SUB_MODULES_V1Waivedprim_arbiter to be verified later
ReviewDESIGN_SPEC_REVIEWEDDone
ReviewTESTPLAN_REVIEWEDDone
ReviewSTD_TEST_CATEGORIES_PLANNEDDoneException (Security, Power, Debug, Performance)
ReviewV2_CHECKLIST_SCOPEDDone

V2

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V2N/A
DocumentationDV_DOC_COMPLETEDDone
TestbenchFUNCTIONAL_COVERAGE_IMPLEMENTEDNot Started
TestbenchALL_INTERFACES_EXERCISEDDone
TestbenchALL_ASSERTION_CHECKS_ADDEDDone
TestbenchSIM_TB_ENV_COMPLETEDDone
TestsSIM_ALL_TESTS_PASSINGDone
TestsFPV_ALL_ASSERTIONS_WRITTENN/A
TestsFPV_ALL_ASSUMPTIONS_REVIEWEDN/A
TestsSIM_FW_SIMULATEDN/A
RegressionSIM_NIGHTLY_REGRESSION_V2Done
CoverageSIM_CODE_COVERAGE_V2Done
CoverageSIM_FUNCTIONAL_COVERAGE_V2Done
CoverageFPV_CODE_COVERAGE_V2N/A
CoverageFPV_COI_COVERAGE_V2N/A
IntegrationPRE_VERIFIED_SUB_MODULES_V2Waivedprim_arbiter to be verified later
IssuesNO_HIGH_PRIORITY_ISSUES_PENDINGDone
IssuesALL_LOW_PRIORITY_ISSUES_ROOT_CAUSEDDone
ReviewDV_DOC_TESTPLAN_REVIEWEDNot Started
ReviewV3_CHECKLIST_SCOPEDDone

V2S

TypeItemResolutionNote/Collaterals
DocumentationSEC_CM_TESTPLAN_COMPLETEDNot Started
TestsFPV_SEC_CM_VERIFIEDNot Started
TestsSIM_SEC_CM_VERIFIEDNot Started
CoverageSIM_COVERAGE_REVIEWEDNot Started
ReviewSEC_CM_DV_REVIEWEDNot Started

V3

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V3N/A
TestsX_PROP_ANALYSIS_COMPLETEDWaivedtool setup in progress
TestsFPV_ASSERTIONS_PROVEN_AT_V3N/A
Regression[SIM_NIGHTLY_REGRESSION_AT_100][]Done
CoverageSIM_CODE_COVERAGE_AT_100Donexbar_cov_excl.el
CoverageSIM_FUNCTIONAL_COVERAGE_AT_100Done
CoverageFPV_CODE_COVERAGE_AT_100N/A
CoverageFPV_COI_COVERAGE_AT_100N/A
Code QualityALL_TODOS_RESOLVEDDone
Code QualityNO_TOOL_WARNINGS_THROWNDoneWaived warning due to using ‘force’ to connect the signal
Code QualityTB_LINT_COMPLETENot Started
IntegrationPRE_VERIFIED_SUB_MODULES_V3Waivedprim_arbiter to be verified later
IssuesNO_ISSUES_PENDINGDone
ReviewReviewer(s)Done@eunchan @sriyerg
ReviewSignoff dateDone2019-11-07