OpenTitan Documentation

Enable entropy_src, wait for interrupt, verify entropy.

Verify the reset values as indicated in the RAL specification.

• Write all CSRs with a random value.
• Apply reset to the DUT as well as the RAL model.
• Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify accessibility of CSRs as indicated in the RAL specification.

• Loop through each CSR to write it with a random value.
• Read the CSR back and check for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within individual bits of a CSR.

• Walk a 1 through each CSR by flipping 1 bit at a time.
• Read the CSR back and check for correctness while adhering to its access policies.
• This verify that writing a specific bit within the CSR did not affect any of the other bits.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within the CSR address space.

• Loop through each CSR to write it with a random value
• Shuffle and read ALL CSRs back.
• All CSRs except for the one that was written in this iteration should read back the previous value.
• The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify random reset during CSR/memory access.

• Run csr_rw sequence to randomly access CSRs
• If memory exists, run mem_partial_access in parallel with csr_rw
• Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.

Verify regwen CSR and its corresponding lockable CSRs.

• Randomly access all CSRs
• Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

• If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
• If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

Verify ability to access entropy register based on value of efuse input Verify sw_regupd, me_regwen bits enables/disables write access to control registers Verify control registers are read-only while DUT is enabled Verify registers at End-Of-Test

Verify health_checks aren't active Verify bypass active Verify read FIFO

• Random FIFO depths

Verify rng entropy

• Random FIFO depths
• Random rates
• Verify single_bit_mode for all bit_selector values Verify FIPS bits match predicted

Verify AdaptProp, RepCnt, RepCntSym, Bucket, Markov health check results match predicted.

• Generate passing and failing raw entropy streams
• Random window sizes
• Default and random hi/lo bypass/fips thresholds
• Enables/fail counts/clears
• Verify hi/lo bypass/fips watermarks
• Verify External health check behaves as predicted
• Verify outputs match internal reg values/entropy bus
• Pulse inputs and verify captured
• Verify health testing stops when no demand for entropy

Verify genbits seeds in bypass mode as predicted. Verify genbits seeds after sha3 conditioning as predicted.

Verify es_entropy_valid interrupt asserts as predicted. Verify es_health_test_failed interrupt asserts as predicted. Verify es_fifo_err interrupt asserts as predicted.

Verify that all recoverable alerts are asserted as expected. Any alerts not encountered as part of the usual entropy_src_rng test will be generated by the entropy_src_functional_alerts test.

Combine the individual test points while injecting TL errors and running CSR tests in parallel.

Verify that all possible classes of fatal errors (FIFOs, Counters, state machine exceptions, etc.) have been generated. These errors typically violate assumptions made by the scoreboard, and thus cannot be managed by other tests.

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

• Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
• Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
• Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
• Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
• Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
• Repeat the above steps a bunch of times.

Verify common alert_test CSR that allows SW to mock-inject alert requests.

• Enable a random set of alert requests by writing random value to alert_test CSR.
• Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
• During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
• Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
• Repeat the above steps a bunch of times.

Access out of bounds address and verify correctness of response / behavior

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec

• TL-UL protocol error cases
  • invalid opcode
  • some mask bits not set when opcode is PutFullData
  • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
  • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
  • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
  • size is greater than 2
• OpenTitan defined error cases
  • access unmapped address, expect d_error = 1 when devmode_i == 1
  • write a CSR with unaligned address, e.g. a_address[1:0] != 0
  • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
  • write a memory with a_mask != '1 when it doesn't support partial accesses
  • read a WO (write-only) memory
  • write a RO (read-only) memory
  • write with instr_type = True

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Verify that the data integrity check violation generates an alert.

• Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
• Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs

Verify the countermeasure(s) CONFIG.REGWEN. Verify that:

1. ME_REGWEN and SW_REGUPD cannot be set back to 1 after being set to 0 once.
2. If ME_REGWEN is not set, MODULE_ENABLE cannot be modified.
3. Only if MODULE_ENABLE is MuBi4False and SW_REGUPD is 1, a) REGWEN reads as 1 and b) associated control and threshold registers can be modified.

Verify the countermeasure(s) CONFIG.MUBI. Verify that upon writing invalid MUBI values to configuration registers:

1. the DUT signals a recoverable alert and sets the correct bit in the RECOV_ALERT_STS register, and
2. the DUT can be configured back to a safe configuration and the RECOV_ALERT_STS register can be cleared.

Verify the countermeasure(s) CONFIG.REDUN. Verify that upon improperly configuring the ALERT_TRESHOLD register:

1. the DUT signals a recoverable alert and sets the correct bit in the RECOV_ALERT_STS register, and
2. the DUT can be configured back to a safe configuration and the RECOV_ALERT_STS register can be cleared.

Verify the countermeasure(s) INTERSIG.MUBI. Verify that unless the otp_en_entropy_src_fw_read or otp_en_entropy_src_fw_over input signals are equal to MuBi8True the DUT doesn't allow reading entropy from the ENTROPY_DATA register or from the FW_OV_RD_DATA register, respectively.

Verify the countermeasure(s) MAIN_SM.FSM.SPARSE. The entropy_src_functional_errors test verifies that if the FSM state is forced to an illegal state encoding this is reported in the ERR_CODE register. It currently doesn't check whether the DUT actually triggers a fatal alert. Alert connection and triggering are verified through automated FPV.

Verify the countermeasure(s) ACK_SM.FSM.SPARSE. The entropy_src_functional_errors test verifies that if the FSM state is forced to an illegal state encoding this is reported in the ERR_CODE register. It currently doesn't check whether the DUT actually triggers a fatal alert. Alert connection and triggering are verified through automated FPV.

Verify the countermeasure(s) RNG.BKGN_CHK. Verify the different background health checks with different, randomized threshold values.

Verify the countermeasure(s) CTR.REDUN. The entropy_src_functional_errors test verifies that if there is any mismatch in the redundant counters this is reported in the ERR_CODE register. It currently doesn't check whether the DUT actually triggers a fatal alert. Alert connection and triggering are verified through automated FPV.

Verify the countermeasure(s) CTR.LOCAL_ESC. Verify that upon a mismatch in any of the redundant counters the main FSM enters a terminal error state and that the DUT signals a fatal alert.

Verify the countermeasure(s) ESFINAL_RDATA.BUS.CONSISTENCY. Verify that if two subsequents read requests to the esfinal FIFO obtain the same data, the DUT signals a recoverable alert and sets the correct bit in the RECOV_ALERT_STS register.

Verify the countermeasure(s) TILE_LINK.BUS.INTEGRITY.

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Covers a range of values (1, 2, 3-6, 6-10, plus > 10) for ALERT_THRESHOLD. To be sampled when a HT alert fires.

Covers that all counter-related fatal errors have been tested by forcing the respective redundant counters to be mismatched from each other.

• which_cntr (0 to 5), 6 possible counter errors, window counter, repcnt ht counter, repcnts ht counter, adaptive proportion ht counter, bucket ht counter and markov ht counter
• which_cntr_replicate (0 to RNG_BUS_WIDTH-1), reptcnt, adaptp, markov health tests have RNG_BUS_WIDTH copies of counters
• which_bin (0 to 2^{RNG_BUS_WIDTH}-1), bucket health test has 2^{RNG_BUS_WIDTH} copies of counters

Covers a range of thresholds and configurations for the continuous health tests: REPCNT (the repetition count test), and REPCNTS (the symbol based repetition count test). The primary cover points are the test_type (REPCNT vs. REPCNTS), the pass or fail value of the test, and the "score". The score is a generalization of the numerical value of the test output, which accounts for the fact it is far more likely to see high values from the REPCNT test than the REPCNTS test, and is computed by multiplying the numerical values of the REPCNTS test by RNG_BUS_WIDTH. Much like the windowed health tests which generalize the test thresholds in terms of "sigma" values, the "score" places the REPCNT and REPCNTS values on equal footing when generating cross bins. For an ideal noise distribution on each RNG bus line, the probablity of a given "score" should be the same for the two tests, under the observation that a coincidental repetition of all bus lines is as likely as RNG_BUS_WIDTH repetitions of a single line.

The cp_score coverpoint covers a range of values for the test output score (1-5, 6-10, 11-20, 21-40, and above 41). For an idealized noise source the coincidental probability of a given score, n, is roughly 2^-n, and thus it is envisioned that typically thresholds will be set to detect failures somewhere in the score range of 20-40, to fall in line with the guidance in SP 800-90B that the false positive rate for these tests should lie in the range of 2^-40 to 2^-20.

In addition to the score, pass-fail status and the test type, this covergroup also has coverpoints for other configurations such as the RNG bit select mode and the fips-mode selection status (True or False), as well as a large number of crosspoints.

Covers that data output is observed at the CSRNG HW interface for all possible modes of operation, including:

• CONF.FIPS_ENABLE (True and False)
• CONF.ENTROPY_DATA_REG_ENABLE (True and False)
• CONF.THRESHOLD_SCOPE (True and False)
• CONF.RNG_BIT_ENABLE (True and False)
• CONF.RNG_BIT_SEL (0 to 3)
• ENTROPY_CONTROL.ES_TYPE (True and False)
• FW_OV_MODE (True or False)
• FW_OV_ENTROPY_INSERT (True or False) In addition to the above, the following settings are illegal when sampling on this covergroup, and merit the creation of illegal_bins
• ENTROPY_CONTROL.ES_ROUTE = True

Since the scoreboard permits data to be dropped or rejected by the entropy source we must explicitly confirm that the data is observed at the outputs for all possible configurations.

Covers that the ERR_CODE_TEST register has been tested for all 9 valid test values:

• 0: SFIFO_ESRNG_ERR
• 1: SFIFO_OBSERVE_ERR
• 2: SFIFO_ESFINAL_ERR
• 20: ES_ACK_SM_ERR
• 21: ES_MAIN_SM_ERR
• 22: ES_CNTR_ERR
• 28: FIFO_WRITE_ERR
• 29: FIFO_READ_ERR
• 30: FIFO_STATE_ERR Each test bit should then trigger the corresponding alerts and error status bits.

Covers that all three fifos (the esrng fifo, the observe fifo, and the esfinal fifo) have all been forced into the three error states (write overflow, read underflow, and invalid state), and the error has sucessfully generated an alert and that the alert is successfully reported in the the ERR_CODE register.

Covers that all 11 register fields with built in redundancy (All multi-bit encoded except for ALERT_THRESHOLD) have been programmed with at least one one invalid mubi value, and that the corresponding recoverable alert has been registered. This includes the 10 boolean register fields which are MultiBit encoded as well as the ALERT_THRESHOLD register, which is a pair of numeric values which must be inverses of each other.

Covers that data output is observed at the fw_ov_rd_data CSE interface for all possible modes of operation, including:

• CONF.FIPS_ENABLE (True and False)
• CONF.ENTROPY_DATA_REG_ENABLE (True and False)
• CONF.THRESHOLD_SCOPE (True and False)
• CONF.RNG_BIT_ENABLE (True and False)
• CONF.RNG_BIT_SEL (0 to 3)
• ENTROPY_CONTROL.ES_ROUTE (True and False), If True, data must be observed at the ENTROPY_DATA CSR. If False, data must be observed at the CSRNG port.
• ENTROPY_CONTROL.ES_TYPE (True and False)
• FW_OV_MODE (True or False)
• FW_OV_ENTROPY_INSERT (True or False) Since the scoreboard permits data to be dropped by the entropy source we must explicitly confirm that the data is observed at this output for all possible configurations.

Covers a range of values (1-63) for OBSERVE_FIFO_THRESH. Coverage bins include the lowest value (1), the highest value (63) and four bins in between. Interrupts and data must be observed for all bins. Thus this covergroup should be sampled after an interrupt has fired and OBSERVE_FIFO_THRESH words have been read from the FIFO. Note: The value of 0 should never generate an interrupt, a constraint that must be checked in the scoreboard.

Checks that all of the health test registers have been exercised and that the one-way update feature (which prohibits thresholds being relaxed after reset) works for both the FIPS and Bypass thresholds.

This covergroup has a single coverpoint that ensures that every active bit in the "recov_alert_sts" register has been triggered. This coverpoint is thus complementary to the mubi_err_cg, fifo_err_cg, and sm_err_cg covergroups though it also covers a number of other recoverable errors, such as violations of the FW_OV usage model, or errors internal to the SHA conditioning unit.

Cover each lockable reg field with these 2 cases:

• When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
• When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

Covers that data output is observed at the entropy_data CSR interfaces for all possible modes of operation, including:

• CONF.FIPS_ENABLE (True and False)
• CONF.THRESHOLD_SCOPE (True and False)
• CONF.RNG_BIT_ENABLE (True and False)
• CONF.RNG_BIT_SEL (0 to 3)
• ENTROPY_CONTROL.ES_TYPE (True and False)
• FW_OV_MODE (True or False)
• FW_OV_ENTROPY_INSERT (True or False) In addition to the above, the following settings are illegal when sampling on the this covergroup, and merit the creation of illegal_bins
• ENTROPY_CONTROL.ES_ROUTE = False
• CONF.ENTROPY_DATA_REG_ENABLE = False

Since the scoreboard permits data to be dropped or rejected by the entropy source we must explicitly confirm that the data is observed at the outputs for all possible configurations.

Covers that both the MAIN_SM and ACK_SM have been forced into an invalid state, and this state error has been successfully detected, the appropriate alerts have been signalled, and the error has been sucessfully reported in the error CSRs.

Covers that the TB has attempted to update DUT configurations while the module is enabled, to ensure that the sw_regupd CSR is working

Cover the following error cases on TL-UL bus:

• TL-UL protocol error cases.
• OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.

Covers a range of window sizes for each windowed health test. For each test we need:

• Test: ADAPTB, BUCKET, MARKOV. No cross between tests. EXT HT, though windowed, is not used or covered at this time
• window_size: {384, 512, 1024, 2048, 4096, plus other non-powers of two}
• Result: HT Pass and Failure
• Hi or Low: Was the current sample a pass or a fail for the high threshold or the low threshold? Note: This covergroup covers a wide range of window sizes but does not cover a range of threshold values. See win_ht_deep_threshold_cg for threshold coverpoints.

Covers a range of thresholds values for a focused set of window sizes. For each test we need:

• Test: ADAPTB, BUCKET, MARKOV, REPCNT, and REPTCNTS. No cross between tests. EXT HT, though it is a windowed test, is not covered at this time.
• Window Size: Covers only the most common window sizes of 384, 1024 and 2048
• Result: HT Pass and Failure.
• Hi or Low: Was the current sample a pass or a fail for the high threshold or the low threshold?
• By-line: Was the test applied on a by-line basis or across all lines?
• Threshold Significance Buckets. There is some sublety in choosing the range of thresholds bins as the choice of thresholds depends heavily choice of window size. The output of each health test will be tighly clustered near some average value, and the health test threshold serves to tag outliers from this average.
  • For instance, when averaging over all lines, the output of the ADAPTP test should on average be close to WINSIZE/2, and the high and low thresholds will be placed on either side of this midpoint. This means however that the thresholds used for a window size of 2048 should both be somewhere close to 1024. Such thresholds would be meaningless for a window size of 384, as there is no way the test can ever output values near 1024 for such a small window.
  • Rather than choosing fixed threshold bins we choose bins based on threshold significance, or how stringent the given threshold would be in detecting deviations from the average value. Tighter thresholds will more quickly detect statistical defects in the incoming noise stream, but will also more frequently indicate false positives for health test defects.
  • We use the following bins for threshold significance:
    • 0 to 1 sigma: Greater than 1 in 3 chance of false positive. With frequent failures, this range is very good for testing the alert subsystem.
    • 1 to 2 sigma: 2.5% chance of a false positive.
    • 2 to 4.5 sigma: False positives are more frequent than 1 in 2²⁰
    • 4.5 to 7 sigma: Covers the NIST recommended range for keeping the rate of false positives within the range of 1 in 2²⁰ to 1 in 2^40.
    • Above 7 sigma: If using idealized noise sources these thresholds would yield false positive rates less than 1 part in 2⁴⁰ making these thresholds too relaxed for the recommendations in NIST SP 80-900B. However for imperfect noise sources with realistic statistical defects, which are to be expected and must be compensated for, thresholds in these ranges may be needed for practical operation, and so there should be at least one bin for these threshold significance values.