SPI_HOST Checklist

This checklist is for Hardware Stage transitions for the SPI_HOST peripheral. All checklist items refer to the content in the Checklist.

Design Checklist

D1

TypeItemResolutionNote/Collaterals
DocumentationSPEC_COMPLETEDoneSPI_HOST Design Spec
DocumentationCSR_DEFINEDDone
RTLCLKRST_CONNECTEDDone
RTLIP_TOPDone
RTLIP_INSTANTIABLEDone
RTLPHYSICAL_MACROS_DEFINED_80N/A
RTLFUNC_IMPLEMENTEDDone
RTLASSERT_KNOWN_ADDEDDone
Code QualityLINT_SETUPDone

D2

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURESDone
DocumentationBLOCK_DIAGRAMDone
DocumentationDOC_INTERFACEDone
DocumentationDOC_INTEGRATION_GUIDEWaivedThis checklist item has been added retrospectively.
DocumentationMISSING_FUNCDone
DocumentationFEATURE_FROZENDone
RTLFEATURE_COMPLETEDone
RTLPORT_FROZENDone
RTLARCHITECTURE_FROZENDone
RTLREVIEW_TODODone
RTLSTYLE_XDone
RTLCDC_SYNCMACRON/A
Code QualityLINT_PASSDone
Code QualityCDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityRDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityAREA_CHECKDone
Code QualityTIMING_CHECKDone
SecuritySEC_CM_DOCUMENTEDN/A

D2S

TypeItemResolutionNote/Collaterals
SecuritySEC_CM_ASSETS_LISTEDDone
SecuritySEC_CM_IMPLEMENTEDDone
SecuritySEC_CM_RND_CNSTN/A
SecuritySEC_CM_NON_RESET_FLOPSN/A
SecuritySEC_CM_SHADOW_REGSN/A
SecuritySEC_CM_RTL_REVIEWEDN/A
SecuritySEC_CM_COUNCIL_REVIEWEDN/AThis block only contains the bus-integrity CM.

D3

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURES_D3Not Started
RTLTODO_COMPLETENot Started
Code QualityLINT_COMPLETENot Started
Code QualityCDC_COMPLETENot Started
Code QualityRDC_COMPLETENot Started
ReviewREVIEW_RTLNot Started
ReviewREVIEW_DELETED_FFNot Started
ReviewREVIEW_SW_CHANGENot Started
ReviewREVIEW_SW_ERRATANot Started
ReviewReviewer(s)Not Started
ReviewSignoff dateNot Started

Verification Checklist

V1

TypeItemResolutionNote/Collaterals
DocumentationDV_DOC_DRAFT_COMPLETEDDONESPI_HOST DV document
DocumentationTESTPLAN_COMPLETEDDONESPI_HOST Testplan
TestbenchTB_TOP_CREATEDDONE
TestbenchPRELIMINARY_ASSERTION_CHECKS_ADDEDDONE
TestbenchSIM_TB_ENV_CREATEDDONE
TestbenchSIM_RAL_MODEL_GEN_AUTOMATEDDONE
TestbenchCSR_CHECK_GEN_AUTOMATEDDONE
TestbenchTB_GEN_AUTOMATEDDONE
TestsSIM_SMOKE_TEST_PASSINGDONE
TestsSIM_CSR_MEM_TEST_SUITE_PASSINGDONE
TestsFPV_MAIN_ASSERTIONS_PROVENN/A
Tool SetupSIM_ALT_TOOL_SETUPDONEXcelium (signoff), VCS (alt)
RegressionSIM_SMOKE_REGRESSION_SETUPDONE
RegressionSIM_NIGHTLY_REGRESSION_SETUPDONE
RegressionFPV_REGRESSION_SETUPN/A
CoverageSIM_COVERAGE_MODEL_ADDEDDONE
Code QualityTB_LINT_SETUPDONE
IntegrationPRE_VERIFIED_SUB_MODULES_V1N/A
ReviewDESIGN_SPEC_REVIEWEDDONE
ReviewTESTPLAN_REVIEWEDDONE
ReviewSTD_TEST_CATEGORIES_PLANNEDDONE
ReviewV2_CHECKLIST_SCOPEDNot Started

V2

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V2DONESPI_HOST DV document
DocumentationDV_DOC_COMPLETEDDONESPI_HOST Testplan
TestbenchFUNCTIONAL_COVERAGE_IMPLEMENTEDDONE
TestbenchALL_INTERFACES_EXERCISEDDONE
TestbenchALL_ASSERTION_CHECKS_ADDEDDONE
TestbenchSIM_TB_ENV_COMPLETEDDONE
TestsSIM_ALL_TESTS_PASSINGDONE
TestsFPV_ALL_ASSERTIONS_WRITTENN/A
TestsFPV_ALL_ASSUMPTIONS_REVIEWEDN/A
TestsSIM_FW_SIMULATEDN/A
RegressionSIM_NIGHTLY_REGRESSION_V2DONE
CoverageSIM_CODE_COVERAGE_V2DONEFSM coverage (69.57) to be improved in V3 as those uncovered transitions all require to reset during the transaction (active states -> idle state)
CoverageSIM_FUNCTIONAL_COVERAGE_V2DONE
CoverageFPV_CODE_COVERAGE_V2N/A
CoverageFPV_COI_COVERAGE_V2N/A
IntegrationPRE_VERIFIED_SUB_MODULES_V2N/A
IssuesNO_HIGH_PRIORITY_ISSUES_PENDINGDONE
IssuesALL_LOW_PRIORITY_ISSUES_ROOT_CAUSEDDONE
ReviewDV_DOC_TESTPLAN_REVIEWEDDONE
ReviewV3_CHECKLIST_SCOPEDNot Started

V2S

TypeItemResolutionNote/Collaterals
DocumentationSEC_CM_TESTPLAN_COMPLETEDNot Started
TestsFPV_SEC_CM_VERIFIEDNot Started
TestsSIM_SEC_CM_VERIFIEDNot Started
CoverageSIM_COVERAGE_REVIEWEDNot Started
ReviewSEC_CM_DV_REVIEWEDNot Started

V3

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V3Not Started
TestsX_PROP_ANALYSIS_COMPLETEDNot Started
TestsFPV_ASSERTIONS_PROVEN_AT_V3Not Started
RegressionSIM_NIGHTLY_REGRESSION_AT_V3Not Started
CoverageSIM_CODE_COVERAGE_AT_100Not Started
CoverageSIM_FUNCTIONAL_COVERAGE_AT_100Not Started
CoverageFPV_CODE_COVERAGE_AT_100Not Started
CoverageFPV_COI_COVERAGE_AT_100Not Started
Code QualityALL_TODOS_RESOLVEDNot Started
Code QualityNO_TOOL_WARNINGS_THROWNNot Started
Code QualityTB_LINT_COMPLETENot Started
IntegrationPRE_VERIFIED_SUB_MODULES_V3Not Started
IssuesNO_ISSUES_PENDINGNot Started
ReviewReviewer(s)Not Started
ReviewSignoff dateNot Started