Testpoints
Stage | Name | Tests | Description |
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V1 | smoke | sysrst_ctrl_smoke | Verify end to end data transfer in normal operation mode.
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V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | Verify end to end data transfer with inverted input and inverted output.
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V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | Verify the combo detection with ec_rst action.
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V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | Verify the pre-condition for combo detection.
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V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
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V1 | csr_rw | sysrst_ctrl_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
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V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
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V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | Verify no aliasing within the CSR address space.
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V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
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V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw sysrst_ctrl_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | combo_detect | sysrst_ctrl_combo_detect | Verify the combo detection with random action.
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V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | Verify the combo detection with random action and precondition.
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V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | Verify the auto block key output feature.
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V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | Verify the keyboard and input triggered interrupt feature by detecting the edge transitions on input pins.
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V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | Verify the keyboard inversion feature by override logic.
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V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | Verify the pin input value accessibilty.
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V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | Verify the EC and power on reset.
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V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | Verify the flash write protect.
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V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | Verify the ultra low power feature.
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V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | Verify the feature disable and debounce to idle state transitions
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V2 | stress_all | sysrst_ctrl_stress_all | Test all the sequences randomly in one sequence.
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V2 | alert_test | sysrst_ctrl_alert_test | Verify common
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V2 | intr_test | sysrst_ctrl_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
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V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec
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V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset sysrst_ctrl_csr_rw sysrst_ctrl_csr_aliasing sysrst_ctrl_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset sysrst_ctrl_csr_rw sysrst_ctrl_csr_aliasing sysrst_ctrl_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | sysrst_ctrl_tl_intg_err sysrst_ctrl_sec_cm | Verify that the data integrity check violation generates an alert.
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V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | Verify the countermeasure(s) BUS.INTEGRITY. |
V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers. |
Covergroups
Name | Description |
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debounce_timer_cg | Cover the debounce timer of the following registers
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pin_cfg_cg | Cover the override enable/disable of all the inputs. Cover the override values of all the input values. Cover the allowed value 0 and 1 of all the inputs. Cross all the above coverpoints. |
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
sysrst_ctrl_auto_blk_out_ctl_cg | Cover the auto blk input select and their values. Cross the key outputs selected to override with their override values. Sample the covergroup when the event occurs. |
sysrst_ctrl_auto_block_debounce_ctl_cg | Cover the auto block enable/disable feature. Cover the auto block debounce timer. |
sysrst_ctrl_combo_detect_action_cg | Cover all the combo detect, combo_sel and combo_pre_sel actions. Create 4 instance to cover the combo detect register [0-3]. Sample the covergroup when the event occurs. Cross the covergroup with combo_detect_sel_cg and combo_pre_sel_cg to cover all the input combination with all the possible combo_detect actions. |
sysrst_ctrl_combo_detect_det_cg | Cover the combo detect debounce timer. Create 4 instance to cover the combo detect register [0-3]. |
sysrst_ctrl_combo_intr_status_cg | Cover the combo detect status of all 4 set of combo registers. Cover all the input combinations has generated selected outcome actions and cross with the status generated. |
sysrst_ctrl_combo_precondition_det_cg | Cover the combo detect precondition debounce timer. Create 4 instance to cover the combo detect precondition register [0-3]. |
sysrst_ctrl_key_intr_status_cg | Cover the H2L/L2H edge detect event of all the inputs. |
sysrst_ctrl_key_invert_ctl_cg | Cover the invert values of all input and output values. |
sysrst_ctrl_pin_in_value_cg | Cover the raw input values before inversion for all inputs. |
sysrst_ctrl_ulp_status_cg | Cover the ultra low power event triggered. Cover the following condition triggers the ultra low power event:
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sysrst_ctrl_wkup_event_cg | Cover the ultra low power wakeup event and status. Cover the wkup event could occur due to following condition:
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tl_errors_cg | Cover the following error cases on TL-UL bus:
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tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |