Testpoints
Stage | Name | Tests | Description |
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V1 | smoke | edn_smoke | Verify send instantiate/generate command Verify single endpoint requests Verify endpoint data = genbits data |
V1 | csr_hw_reset | edn_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
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V1 | csr_rw | edn_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
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V1 | csr_bit_bash | edn_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
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V1 | csr_aliasing | edn_csr_aliasing | Verify no aliasing within the CSR address space.
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V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
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V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw edn_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | firmware | edn_genbits | Verify SW_CMD_REQ/SW_CMD_STS registers/bits behave as predicted. Verify software mode behaves as predicted. Verify INSTANTIATE/GENERATE software cmds. Verify cmd_fifo_reset bit causes fifos to reset. |
V2 | csrng_commands | edn_genbits | Verify when no/some/all endpoints requesting (test arbiter). Verify boot request mode behaves as predicted. Verify BOOT_INS_CMD/BOOT_GEN_CMD registers. Verify auto request mode behaves as predicted. Verify RESEED_CMD/GENERATE_CMD/MAX_NUM_REQS_BETWEEN_RESEEDS registers. Verify SUM_STS register bits behave as predicted. Verify all csrng commands (clen = 0-12, sw_mode, boot/auto_req_mode). Verify with ready randomly asserting/deasserting |
V2 | genbits | edn_genbits | Verify genbits input is transferred to endpoint(s) as predicted. Verify fips bit(s) are properly transferred to endpoint. |
V2 | interrupts | edn_intr | Verify intr_edn_cmd_req_done interrupt asserts/clears as predicted. Verify intr_edn_fatal_err interrupt asserts/clears as predicted. |
V2 | alerts | edn_alert | Verify recov_alert_sts asserts/clears as predicted. |
V2 | errs | edn_err | Verify ERR_CODE asserts as predicted. Verify ERR_CODE all reg bits via ERR_CODE_TEST. |
V2 | disable | edn_disable edn_disable_auto_req_mode | Disable EDN in all states and verify proper operation when re-enabled. |
V2 | stress_all | edn_stress_all | Combine the other individual testpoints while injecting TL errors and running CSR tests in parallel. |
V2 | intr_test | edn_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
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V2 | alert_test | edn_alert_test | Verify common
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V2 | tl_d_oob_addr_access | edn_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | edn_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec
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V2 | tl_d_outstanding_access | edn_csr_hw_reset edn_csr_rw edn_csr_aliasing edn_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | edn_csr_hw_reset edn_csr_rw edn_csr_aliasing edn_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | edn_tl_intg_err edn_sec_cm | Verify that the data integrity check violation generates an alert.
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V2S | sec_cm_config_regwen | edn_regwen | Verify the countermeasure(s) CONFIG.REGWEN. |
V2S | sec_cm_config_mubi | edn_alert | Verify the countermeasure(s) CONFIG.MUBI. Write non-Mubi4True or Mubi4False value to the ctrl register's mubi fields. Verify that design triggers the corresponding recoverable alerts and error status. Verify that design categorizes the value as Mubi4False. |
V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | Verify the countermeasure(s) MAIN_SM.FSM.SPARSE. |
V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | Verify the countermeasure(s) ACK_SM.FSM.SPARSE. |
V2S | sec_cm_ctr_redun | edn_sec_cm | Verify the countermeasure(s) CTR.REDUN. |
V2S | sec_cm_main_sm_ctr_local_esc | edn_sec_cm edn_alert | Verify the countermeasure(s) MAIN_SM.CTR.LOCAL_ESC. Verify that after the local escalation:
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V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | Verify the countermeasure(s) CS_RDATA.BUS.CONSISTENCY. Load randomly generated but constant fips and genbits data from the CSRNG host driver to create the consistency error. Check the corresponding recoverable alert is fired and check the recov_alert_sts register. |
V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | Verify the countermeasure(s) TILE_LINK.BUS.INTEGRITY. |
V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers. |
Covergroups
Name | Description |
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cs_cmds_cg | Covers the following:
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edn_cfg_cg | Covers that all edn configuration options have been tested. Individual config settings that will be covered include:
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edn_endpoints_cg | Covers none/some/all endpoints requesting |
err_test_cg | Covers that all fatal errors, all fifo errors and all error codes of edn have been tested. Individual config settings that will be covered include:
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regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
tl_errors_cg | Cover the following error cases on TL-UL bus:
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tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |