Testplan

Testpoints

Stage V1 Testpoints

smoke

Test: edn_smoke

Verify send instantiate/generate command Verify single endpoint requests Verify endpoint data = genbits data

csr_hw_reset

Test: edn_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_rw

Test: edn_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_bit_bash

Test: edn_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_aliasing

Test: edn_csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_mem_rw_with_rand_reset

Test: edn_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.

regwen_csr_and_corresponding_lockable_csr

Tests:

  • edn_csr_rw
  • edn_csr_aliasing

Verify regwen CSR and its corresponding lockable CSRs.

  • Randomly access all CSRs
  • Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

  • If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
  • If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

Stage V2 Testpoints

firmware

Test: edn_genbits

Verify SW_CMD_REQ/SW_CMD_STS registers/bits behave as predicted. Verify software mode behaves as predicted. Verify INSTANTIATE/GENERATE software cmds. Verify cmd_fifo_reset bit causes fifos to reset.

csrng_commands

Test: edn_genbits

Verify when no/some/all endpoints requesting (test arbiter). Verify boot request mode behaves as predicted. Verify BOOT_INS_CMD/BOOT_GEN_CMD registers. Verify auto request mode behaves as predicted. Verify RESEED_CMD/GENERATE_CMD/MAX_NUM_REQS_BETWEEN_RESEEDS registers. Verify MAIN_SM_STATE register bits behave as predicted. Verify all csrng commands (clen = 0-12, sw_mode, boot/auto_req_mode). Verify with ready randomly asserting/deasserting

genbits

Test: edn_genbits

Verify genbits input is transferred to endpoint(s) as predicted. Verify fips bit(s) are properly transferred to endpoint.

interrupts

Test: edn_intr

Verify intr_edn_cmd_req_done interrupt asserts/clears as predicted. Verify intr_edn_fatal_err interrupt asserts/clears as predicted.

alerts

Test: edn_alert

Verify recov_alert_sts asserts/clears as predicted.

errs

Test: edn_err

Verify ERR_CODE asserts as predicted. Verify ERR_CODE all reg bits via ERR_CODE_TEST.

disable

Tests:

  • edn_disable
  • edn_disable_auto_req_mode

Disable EDN in all states and verify proper operation when re-enabled.

stress_all

Test: edn_stress_all

Combine the other individual testpoints while injecting TL errors and running CSR tests in parallel.

intr_test

Test: edn_intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly “turn on” interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.

alert_test

Test: edn_alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

  • Enable a random set of alert requests by writing random value to alert_test CSR.
  • Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
  • During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
  • Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
  • Repeat the above steps a bunch of times.

tl_d_oob_addr_access

Test: edn_tl_errors

Access out of bounds address and verify correctness of response / behavior

tl_d_illegal_access

Test: edn_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec

  • TL-UL protocol error cases
    • invalid opcode
    • some mask bits not set when opcode is PutFullData
    • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
    • address and size aren’t aligned, e.g. a_address = 0x01, a_size != 0
    • size is greater than 2
  • OpenTitan defined error cases
    • access unmapped address, expect d_error = 1
    • write a CSR with unaligned address, e.g. a_address[1:0] != 0
    • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • write a memory with a_mask != '1 when it doesn’t support partial accesses
    • read a WO (write-only) memory
    • write a RO (read-only) memory
    • write with instr_type = True

tl_d_outstanding_access

Tests:

  • edn_csr_hw_reset
  • edn_csr_rw
  • edn_csr_aliasing
  • edn_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

tl_d_partial_access

Tests:

  • edn_csr_hw_reset
  • edn_csr_rw
  • edn_csr_aliasing
  • edn_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Stage V2S Testpoints

tl_intg_err

Tests:

  • edn_tl_intg_err
  • edn_sec_cm

Verify that the data integrity check violation generates an alert.

  • Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
  • Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs

sec_cm_config_regwen

Test: edn_regwen

Verify the countermeasure(s) CONFIG.REGWEN.

sec_cm_config_mubi

Test: edn_alert

Verify the countermeasure(s) CONFIG.MUBI.

Write non-Mubi4True or Mubi4False value to the ctrl register’s mubi fields. Verify that design triggers the corresponding recoverable alerts and error status. Verify that design categorizes the value as Mubi4False.

sec_cm_main_sm_fsm_sparse

Test: edn_sec_cm

Verify the countermeasure(s) MAIN_SM.FSM.SPARSE.

sec_cm_ack_sm_fsm_sparse

Test: edn_sec_cm

Verify the countermeasure(s) ACK_SM.FSM.SPARSE.

sec_cm_fifo_ctr_redun

Test: edn_sec_cm

Verify the countermeasure(s) FIFO.CTR.REDUN. The auto-generated edn_sec_cm test verifies that if there is any mismatch in the redundant pointers inside the FIFOs, a fatal alert is triggered and that the DUT enters a terminal error state.

sec_cm_ctr_redun

Test: edn_sec_cm

Verify the countermeasure(s) CTR.REDUN.

sec_cm_main_sm_ctr_local_esc

Tests:

  • edn_sec_cm
  • edn_alert

Verify the countermeasure(s) MAIN_SM.CTR.LOCAL_ESC.

Verify that after the local escalation:

  • The fatal alert fires continuously.
  • Register main_sm_state goes to error state.
  • No valid EDN responses.

sec_cm_cs_rdata_bus_consistency

Test: edn_alert

Verify the countermeasure(s) CS_RDATA.BUS.CONSISTENCY.

Load randomly generated but constant fips and genbits data from the CSRNG host driver to create the consistency error. Check the corresponding recoverable alert is fired and check the recov_alert_sts register.

Test: edn_tl_intg_err

Verify the countermeasure(s) TILE_LINK.BUS.INTEGRITY.

Stage V3 Testpoints

stress_all_with_rand_reset

Test: edn_stress_all_with_rand_reset

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Covergroups

edn_alert_cg

Cover all the recoverable alerts:

  • Invalid MUBI values: enable field, boot request mode, auto request mode and command FIFO reset
  • EDN bus comparison

edn_cfg_cg

Covers that all edn configuration options have been tested. Individual config settings that will be covered include:

  • boot_req_mode
  • auto_req_mode
  • sw_mode (neither boot_req_mode/auto_req_mode)
  • num_endpoints
  • num_boot_reqs Cross between num_endpoints and mode.

edn_cs_cmds_cg

Covers the following:

  • csrng_commands vs clen, flags, glen
    • sw, auto_req_mode commands (boot_req_mode cmds have no additional data)
  • ready deasserts during command Crosses between above coverpoints

edn_endpoints_cg

Covers none/some/all endpoints requesting

edn_error_cg

Covers that all fatal errors, all fifo errors and all error codes of edn have been tested. Individual config settings that will be covered include:

  • 3 different FIFOs: rescmd, gencmd and output
  • 3 other error codes: ack state machine, main state machine and counter
  • 3 types of FIFO errors: write/read/state errors

regwen_val_when_new_value_written_cg

Cover each lockable reg field with these 2 cases:

  • When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
  • When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

tl_errors_cg

Cover the following error cases on TL-UL bus:

  • TL-UL protocol error cases.
  • OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.