Hardware IP Blocks

HW BlockBrief Summary
adc_ctrlLow-power controller for a dual-channel ADC with filtering and debouncing capability
aesAES encryption and decryption engine with SCA and FI countermeasures
aon_timerWakeup and watchdog timers running on a low-power, always-on clock
clkmgrDerives and monitors on-chip clock signals, handles clock gating requests from power manager and software
csrngTakes entropy bits to produce cryptographically secure random numbers for consumption by hardware blocks and by software
ednDistributes random numbers produced by CSRNG to hardware blocks
entropy_srcFilters and checks raw entropy bits from a random noise source and forwards them to CSRNG
flash_ctrlInterfaces and manages integrated non-volatile flash memory; supports scrambling, integrity, and secure wipe
gpioGeneral-purpose I/O pin control interface for software
hmacAccelerator for SHA-256-based keyed hash message authentication code and the SHA-256 hash function
i2cI2C interface for host and device mode, supporting up to 1 Mbaud data rates
keymgrManaging identities and root keys; shielding confidential assets from software; providing a key derivation interface for software
kmacAccelerator for Keccak-based keyed hash message authentication code and SHA-3 hash functions; with SCA and FI countermeasures
lc_ctrlManages device life cycle states and transitions, and controls key manager, flash, OTP, and debug access
otbnProgrammable coprocessor for asymmetric cryptography with SCA and FI countermeasures
otp_ctrlInterfaces integrated one-time programmable memory, supports scrambling, integrity and secure wipe
pattgenTransmission of short time-dependent data patterns on two clock-parallel output channels
pinmuxMultiplexes between on-chip hardware blocks and pins; can be configured at runtime
pwmTransmission of pulse-width modulated output signals with adjustable duty cycle
pwrmgrSequences on-chip power, clocks, and resets through different reset and power states
rom_ctrlInterfaces scrambled boot ROM with system bus and KMAC for initial health check after reset
rstmgrControls the on-chip reset signals, records reset cause and CPU crash dump for software
rv_core_ibexDual-core lockstep 32-bit RISC-V processor running application and control software
rv_dmEnables debug support for Ibex, access protected by life cycle
rv_timerMemory-mapped timer unit implementing RISC-V mtime and mtimecmp registers
spi_deviceSerial peripheral interface supporting different device modes, suitable for bulk-load of data into and out of the chip
spi_hostSerial peripheral interface for host mode, suitable for interfacing external serial NOR flash devices
sram_ctrlInterfacing on-chip SRAM blocks with system bus, supports lightweight scrambling, integrity and secure wipe
sysrst_ctrlManages board-level reset sequencing, interfaces reset and power manager
uartFull duplex serial communication interface, supports bit rates of up to 1 Mbit/s
usbdevUSB 2.0 Full Speed device interface (12 Mbit/s)