Registers

The flash protocol controller maintains two separate access windows for the FIFO. It is implemented this way because the access window supports transaction back-pressure should the FIFO become full (in case of write) or empty (in case of read).

Summary of the core interface’s registers

INTR_STATE

Interrupt State Register

• Offset: 0x0
• Reset default: 0x3
• Reset mask: 0x3f

Fields

{"reg": [{"name": "prog_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_lvl", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rd_full", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rd_lvl", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "op_done", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "corr_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

INTR_ENABLE

Interrupt Enable Register

• Offset: 0x4
• Reset default: 0x0
• Reset mask: 0x3f

Fields

{"reg": [{"name": "prog_empty", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "prog_lvl", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rd_full", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rd_lvl", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "op_done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "corr_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

INTR_TEST

Interrupt Test Register

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0x3f

Fields

{"reg": [{"name": "prog_empty", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "prog_lvl", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rd_full", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rd_lvl", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "op_done", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "corr_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

ALERT_TEST

Alert Test Register

• Offset: 0xc
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "recov_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_std_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_prim_flash_alert", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "recov_prim_flash_alert", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}

DIS

Disable flash functionality

• Offset: 0x10
• Reset default: 0x9
• Reset mask: 0xf

Fields

{"reg": [{"name": "VAL", "bits": 4, "attr": ["rw1s"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DIS . VAL

Disables flash functionality completely. This is a shortcut mechanism used by the software to completely kill flash in case of emergency.

Since this register is rw1s instead of rw, to disable, write the value kMuBi4True to the register to disable the flash.

EXEC

Controls whether flash can be used for code execution fetches

• Offset: 0x14
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "EN", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INIT

Controller init register

• Offset: 0x18
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "VAL", "bits": 1, "attr": ["rw1s"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INIT . VAL

Initializes the flash controller.

During the initialization process, the flash controller requests the address and data scramble keys and reads out the root seeds stored in flash before allowing other usage of the flash controller.

When the initialization sequence is complete, the flash read buffers are enabled and turned on.

CTRL_REGWEN

Controls the configurability of the CONTROL register.

This register ensures the contents of CONTROL cannot be changed by software once a flash operation has begun.

It unlocks whenever the existing flash operation completes, regardless of success or error.

• Offset: 0x1c
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CONTROL

Control register

• Offset: 0x20
• Reset default: 0x0
• Reset mask: 0xfff07f1
• Register enable: CTRL_REGWEN

Fields

{"reg": [{"name": "START", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "OP", "bits": 2, "attr": ["rw"], "rotate": 0}, {"name": "PROG_SEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_SEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PARTITION_SEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "INFO_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 5}, {"name": "NUM", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

CONTROL . NUM

One fewer than the number of bus words the flash operation should read or program. For example, to read 10 words, software should program this field with the value 9.

CONTROL . INFO_SEL

Informational partions can have multiple types.

This field selects the info type to be accessed.

CONTROL . PARTITION_SEL

When doing a read, program or page erase operation, selects either info or data partition for operation. When 0, select data partition - this is the portion of flash that is accessible both by the host and by the controller. When 1, select info partition - this is the portion of flash that is only accessible by the controller.

When doing a bank erase operation, selects info partition also for erase. When 0, bank erase only erases data partition. When 1, bank erase erases data partition and info partition.

CONTROL . ERASE_SEL

Flash erase operation type selection

CONTROL . PROG_SEL

Flash program operation type selection

CONTROL . OP

Flash operation selection

Other values are reserved.

CONTROL . START

Start flash transaction. This bit shall only be set at the same time or after the other fields of the CONTROL register and ADDR have been programmed.

ADDR

Address for flash operation

• Offset: 0x24
• Reset default: 0x0
• Reset mask: 0xfffff
• Register enable: CTRL_REGWEN

Fields

{"reg": [{"name": "START", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ADDR . START

Start address of a flash transaction. This is a byte address relative to the flash only. Ie, an address of 0 will access address 0 of the requested partition.

For read operations, the flash controller will truncate to the closest, lower word aligned address. For example, if 0x13 is supplied, the controller will perform a read at address 0x10.

Program operations behave similarly, the controller does not have read modified write support.

For page erases, the controller will truncate to the closest lower page aligned address. Similarly for bank erases, the controller will truncate to the closest lower bank aligned address.

PROG_TYPE_EN

Enable different program types

• Offset: 0x28
• Reset default: 0x3
• Reset mask: 0x3
• Register enable: CTRL_REGWEN

Fields

{"reg": [{"name": "NORMAL", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "REPAIR", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ERASE_SUSPEND

Suspend erase

• Offset: 0x2c
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "REQ", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

REGION_CFG_REGWEN

Memory region registers configuration enable.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

REGION_CFG_REGWEN . REGION

Region register write enable. Once set to 0, it can longer be configured to 1

MP_REGION_CFG

Memory property configuration for data partition

• Reset default: 0x9999999
• Reset mask: 0xfffffff

Instances

Fields

{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

MP_REGION

Memory base and size configuration for data partition

• Reset default: 0x0
• Reset mask: 0x7ffff

Instances

Fields

{"reg": [{"name": "BASE", "bits": 9, "attr": ["rw"], "rotate": 0}, {"name": "SIZE", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DEFAULT_REGION

Default region properties

• Offset: 0x90
• Reset default: 0x999999
• Reset mask: 0xffffff

Fields

{"reg": [{"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

BANK0_INFO0_REGWEN

Memory region registers configuration enable.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

BANK0_INFO0_REGWEN . REGION

Info0 page write enable. Once set to 0, it can longer be configured to 1

BANK0_INFO0_PAGE_CFG

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

• Reset default: 0x9999999
• Reset mask: 0xfffffff

Instances

Fields

{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

BANK0_INFO1_REGWEN

Memory region registers configuration enable.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

BANK0_INFO1_REGWEN . REGION

Info1 page write enable. Once set to 0, it can longer be configured to 1

BANK0_INFO1_PAGE_CFG

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

• Reset default: 0x9999999
• Reset mask: 0xfffffff

Instances

Fields

{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

BANK0_INFO2_REGWEN

Memory region registers configuration enable.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

BANK0_INFO2_REGWEN . REGION

Info2 page write enable. Once set to 0, it can longer be configured to 1

BANK0_INFO2_PAGE_CFG

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

• Reset default: 0x9999999
• Reset mask: 0xfffffff

Instances

Fields

{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

BANK1_INFO0_REGWEN

Memory region registers configuration enable.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

BANK1_INFO0_REGWEN . REGION

Info0 page write enable. Once set to 0, it can longer be configured to 1

BANK1_INFO0_PAGE_CFG

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

• Reset default: 0x9999999
• Reset mask: 0xfffffff

Instances

Fields

{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

BANK1_INFO1_REGWEN

Memory region registers configuration enable.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

BANK1_INFO1_REGWEN . REGION

Info1 page write enable. Once set to 0, it can longer be configured to 1

BANK1_INFO1_PAGE_CFG

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

• Reset default: 0x9999999
• Reset mask: 0xfffffff

Instances

Fields

{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

BANK1_INFO2_REGWEN

Memory region registers configuration enable.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

BANK1_INFO2_REGWEN . REGION

Info2 page write enable. Once set to 0, it can longer be configured to 1

BANK1_INFO2_PAGE_CFG

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

• Reset default: 0x9999999
• Reset mask: 0xfffffff

Instances

Fields

{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "PROG_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HE_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

HW_INFO_CFG_OVERRIDE

HW interface info configuration rule overrides

• Offset: 0x164
• Reset default: 0x99
• Reset mask: 0xff

Fields

{"reg": [{"name": "SCRAMBLE_DIS", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_DIS", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}}

BANK_CFG_REGWEN

Bank configuration registers configuration enable.

• Offset: 0x168
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "BANK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

BANK_CFG_REGWEN . BANK

Bank register write enable. Once set to 0, it can longer be configured to 1

MP_BANK_CFG_SHADOWED

Memory properties bank configuration

• Offset: 0x16c
• Reset default: 0x0
• Reset mask: 0x3
• Register enable: BANK_CFG_REGWEN

Fields

{"reg": [{"name": "ERASE_EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ERASE_EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

OP_STATUS

Flash Operation Status

• Offset: 0x170
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

STATUS

Flash Controller Status

• Offset: 0x174
• Reset default: 0xa
• Reset mask: 0x3f

Fields

{"reg": [{"name": "rd_full", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rd_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_full", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "init_wip", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "initialized", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

DEBUG_STATE

Current flash fsm state

• Offset: 0x178
• Reset default: 0x0
• Reset mask: 0x7ff

Fields

{"reg": [{"name": "lcmgr_state", "bits": 11, "attr": ["ro"], "rotate": 0}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ERR_CODE

Flash error code register. This register tabulates detailed error status of the flash. This is separate from OP_STATUS, which is used to indicate the current state of the software initiated flash operation.

Note, all errors in this register are considered recoverable errors, ie, errors that could have been generated by software.

• Offset: 0x17c
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "op_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "mp_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rd_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "prog_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "prog_win_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "prog_type_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "update_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "macro_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

STD_FAULT_STATUS

This register tabulates standard fault status of the flash.

These represent errors that occur in the standard structures of the design. For example fsm integrity, counter integrity and tlul integrity.

• Offset: 0x180
• Reset default: 0x0
• Reset mask: 0x1ff

Fields

{"reg": [{"name": "reg_intg_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_intg_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "lcmgr_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "lcmgr_intg_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "arb_fsm_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "storage_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "phy_fsm_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ctrl_cnt_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "fifo_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}

FAULT_STATUS

This register tabulates customized fault status of the flash.

These are errors that are impossible to have been caused by software or unrecoverable in nature.

All errors except for multi-bit ECC errors (FAULT_STATUS.PHY_RELBL_ERR) and ICV (FAULT_STATUS.PHY_STORAGE_ERR) trigger a fatal alert. Once set, they remain set until reset.

• Offset: 0x184
• Reset default: 0x0
• Reset mask: 0xfff

Fields

{"reg": [{"name": "op_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "mp_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rd_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_win_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_type_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "seed_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "phy_relbl_err", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "phy_storage_err", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "spurious_ack", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "arb_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "host_gnt_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}

FAULT_STATUS . host_gnt_err

A host transaction was granted with illegal properties.

FAULT_STATUS . arb_err

The phy arbiter encountered inconsistent results.

FAULT_STATUS . spurious_ack

The flash emitted an unexpected acknowledgement.

FAULT_STATUS . phy_storage_err

The flash macro encountered a storage integrity ECC error.

Note that this error bit can be cleared to allow firmware dealing with ICV errors during firmware selection and verification. After passing this stage, it is recommended that firmware classifies the corresponding alert as fatal on the receiver end, i.e, inside the alert handler.

FAULT_STATUS . phy_relbl_err

The flash macro encountered a storage reliability ECC error.

Note that this error bit can be cleared to allow firmware dealing with multi-bit ECC errors during firmware selection and verification. After passing this stage, it is recommended that firmware classifies the corresponding alert as fatal on the receiver end, i.e, inside the alert handler.

FAULT_STATUS . seed_err

The seed reading process encountered an unexpected error.

FAULT_STATUS . prog_type_err

The flash life cycle management interface encountered a program type error. A program type not supported by the flash macro was issued.

FAULT_STATUS . prog_win_err

The flash life cycle management interface encountered a program resolution error.

FAULT_STATUS . prog_err

The flash life cycle management interface encountered a program error. This could be a program integirty eror, see STD_FAULT_STATUS for more details.

FAULT_STATUS . rd_err

The flash life cycle management interface encountered a read error. This could be a reliability ECC error or an integrity ECC error encountered during a read, see STD_FAULT_STATUS for more details.

FAULT_STATUS . mp_err

The flash life cycle management interface encountered a memory permission error.

FAULT_STATUS . op_err

The flash life cycle management interface has supplied an undefined operation. See CONTROL.OP for list of valid operations.

ERR_ADDR

Synchronous error address

• Offset: 0x188
• Reset default: 0x0
• Reset mask: 0xfffff

Fields

{"reg": [{"name": "ERR_ADDR", "bits": 20, "attr": ["ro"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ECC_SINGLE_ERR_CNT

Total number of single bit ECC error count

• Offset: 0x18c
• Reset default: 0x0
• Reset mask: 0xffff

Fields

{"reg": [{"name": "ECC_SINGLE_ERR_CNT_0", "bits": 8, "attr": ["rw"], "rotate": -90}, {"name": "ECC_SINGLE_ERR_CNT_1", "bits": 8, "attr": ["rw"], "rotate": -90}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

ECC_SINGLE_ERR_ADDR

Latest address of ECC single err

• Reset default: 0x0
• Reset mask: 0xfffff

Instances

Fields

{"reg": [{"name": "ECC_SINGLE_ERR_ADDR", "bits": 20, "attr": ["ro"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PHY_ALERT_CFG

Phy alert configuration

• Offset: 0x198
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "alert_ack", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "alert_trig", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

PHY_STATUS

Flash Phy Status

• Offset: 0x19c
• Reset default: 0x6
• Reset mask: 0x7

Fields

{"reg": [{"name": "init_wip", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_normal_avail", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "prog_repair_avail", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}

Scratch

Flash Controller Scratch

• Offset: 0x1a0
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "data", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

FIFO_LVL

Programmable depth where FIFOs should generate interrupts

• Offset: 0x1a4
• Reset default: 0xf0f
• Reset mask: 0x1f1f

Fields

{"reg": [{"name": "PROG", "bits": 5, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "RD", "bits": 5, "attr": ["rw"], "rotate": 0}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

FIFO_RST

Reset for flash controller FIFOs

• Offset: 0x1a8
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CURR_FIFO_LVL

Current program and read fifo depth

• Offset: 0x1ac
• Reset default: 0x0
• Reset mask: 0x1f1f

Fields

{"reg": [{"name": "PROG", "bits": 5, "attr": ["ro"], "rotate": 0}, {"bits": 3}, {"name": "RD", "bits": 5, "attr": ["ro"], "rotate": 0}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

prog_fifo

Flash program FIFO.

The FIFO is 16 entries of 4B flash words. This FIFO can only be programmed by software after a program operation has been initiated via the !!CONTROL register. This ensures accidental programming of the program FIFO cannot lock up the system.

• Word Aligned Offset Range: 0x1b0to0x1b0
• Size (words): 1
• Access: wo
• Byte writes are not supported.

rd_fifo

Flash read FIFO.

The FIFO is 16 entries of 4B flash words

• Word Aligned Offset Range: 0x1b4to0x1b4
• Size (words): 1
• Access: ro
• Byte writes are not supported.

Summary of the prim interface’s registers

CSR0_REGWEN

• Offset: 0x0
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "field0", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR0_REGWEN . field0

All values are reserved.

CSR1

• Offset: 0x4
• Reset default: 0x0
• Reset mask: 0x1fff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 5, "attr": ["rw"], "rotate": 0}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR1 . field1

All values are reserved.

CSR1 . field0

All values are reserved.

CSR2

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "field0", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field1", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field2", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field4", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field5", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field6", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR2 . field7

All values are reserved.

CSR2 . field6

All values are reserved.

CSR2 . field5

All values are reserved.

CSR2 . field4

All values are reserved.

CSR2 . field3

All values are reserved.

CSR2 . field2

All values are reserved.

CSR2 . field1

All values are reserved.

CSR2 . field0

All values are reserved.

CSR3

• Offset: 0xc
• Reset default: 0x0
• Reset mask: 0xfffffff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "field2", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field3", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field4", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field5", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field7", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field8", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field9", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR3 . field9

All values are reserved.

CSR3 . field8

All values are reserved.

CSR3 . field7

All values are reserved.

CSR3 . field6

All values are reserved.

CSR3 . field5

All values are reserved.

CSR3 . field4

All values are reserved.

CSR3 . field3

All values are reserved.

CSR3 . field2

All values are reserved.

CSR3 . field1

All values are reserved.

CSR3 . field0

All values are reserved.

CSR4

• Offset: 0x10
• Reset default: 0x0
• Reset mask: 0xfff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field1", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field3", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR4 . field3

All values are reserved.

CSR4 . field2

All values are reserved.

CSR4 . field1

All values are reserved.

CSR4 . field0

All values are reserved.

CSR5

• Offset: 0x14
• Reset default: 0x0
• Reset mask: 0x7fffff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field1", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 9, "attr": ["rw"], "rotate": 0}, {"name": "field3", "bits": 5, "attr": ["rw"], "rotate": 0}, {"name": "field4", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 9}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR5 . field4

All values are reserved.

CSR5 . field3

All values are reserved.

CSR5 . field2

All values are reserved.

CSR5 . field1

All values are reserved.

CSR5 . field0

All values are reserved.

CSR6

• Offset: 0x18
• Reset default: 0x0
• Reset mask: 0x1ffffff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field1", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field3", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field4", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field5", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field6", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR6 . field8

All values are reserved.

CSR6 . field7

All values are reserved.

CSR6 . field6

All values are reserved.

CSR6 . field5

All values are reserved.

CSR6 . field4

All values are reserved.

CSR6 . field3

All values are reserved.

CSR6 . field2

All values are reserved.

CSR6 . field1

All values are reserved.

CSR6 . field0

All values are reserved.

CSR7

• Offset: 0x1c
• Reset default: 0x0
• Reset mask: 0x1ffff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 15}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR7 . field1

All values are reserved.

CSR7 . field0

All values are reserved.

CSR8

• Offset: 0x20
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR8 . field0

All values are reserved.

CSR9

• Offset: 0x24
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR9 . field0

All values are reserved.

CSR10

• Offset: 0x28
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR10 . field0

All values are reserved.

CSR11

• Offset: 0x2c
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR11 . field0

All values are reserved.

CSR12

• Offset: 0x30
• Reset default: 0x0
• Reset mask: 0x3ff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 22}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR12 . field0

All values are reserved.

CSR13

• Offset: 0x34
• Reset default: 0x0
• Reset mask: 0x1fffff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 20, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 11}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR13 . field1

All values are reserved.

CSR13 . field0

All values are reserved.

CSR14

• Offset: 0x38
• Reset default: 0x0
• Reset mask: 0x1ff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR14 . field1

All values are reserved.

CSR14 . field0

All values are reserved.

CSR15

• Offset: 0x3c
• Reset default: 0x0
• Reset mask: 0x1ff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR15 . field1

All values are reserved.

CSR15 . field0

All values are reserved.

CSR16

• Offset: 0x40
• Reset default: 0x0
• Reset mask: 0x1ff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR16 . field1

All values are reserved.

CSR16 . field0

All values are reserved.

CSR17

• Offset: 0x44
• Reset default: 0x0
• Reset mask: 0x1ff
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR17 . field1

All values are reserved.

CSR17 . field0

All values are reserved.

CSR18

• Offset: 0x48
• Reset default: 0x0
• Reset mask: 0x1
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR18 . field0

All values are reserved.

CSR19

• Offset: 0x4c
• Reset default: 0x0
• Reset mask: 0x1
• Register enable: CSR0_REGWEN

Fields

{"reg": [{"name": "field0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR19 . field0

All values are reserved.

CSR20

• Offset: 0x50
• Reset default: 0x0
• Reset mask: 0x7

Fields

{"reg": [{"name": "field0", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field1", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR20 . field2

All values are reserved.

CSR20 . field1

All values are reserved.

CSR20 . field0

All values are reserved.

This interface does not expose any registers.