Registers

Summary

NameOffsetLengthDescription
spi_device.INTR_STATE0x04Interrupt State Register
spi_device.INTR_ENABLE0x44Interrupt Enable Register
spi_device.INTR_TEST0x84Interrupt Test Register
spi_device.ALERT_TEST0xc4Alert Test Register
spi_device.CONTROL0x104Control register
spi_device.CFG0x144Configuration Register
spi_device.STATUS0x184SPI Device status register
spi_device.INTERCEPT_EN0x1c4Intercept Passthrough datapath.
spi_device.ADDR_MODE0x204Flash address mode configuration
spi_device.LAST_READ_ADDR0x244Last Read Address
spi_device.FLASH_STATUS0x284SPI Flash Status register.
spi_device.JEDEC_CC0x2c4JEDEC Continuation Code configuration register.
spi_device.JEDEC_ID0x304JEDEC ID register.
spi_device.READ_THRESHOLD0x344Read Buffer threshold register.
spi_device.MAILBOX_ADDR0x384Mailbox Base address register.
spi_device.UPLOAD_STATUS0x3c4Upload module status register.
spi_device.UPLOAD_STATUS20x404Upload module status 2 register.
spi_device.UPLOAD_CMDFIFO0x444Command Fifo Read Port.
spi_device.UPLOAD_ADDRFIFO0x484Address Fifo Read Port.
spi_device.CMD_FILTER_00x4c4Command Filter
spi_device.CMD_FILTER_10x504Command Filter
spi_device.CMD_FILTER_20x544Command Filter
spi_device.CMD_FILTER_30x584Command Filter
spi_device.CMD_FILTER_40x5c4Command Filter
spi_device.CMD_FILTER_50x604Command Filter
spi_device.CMD_FILTER_60x644Command Filter
spi_device.CMD_FILTER_70x684Command Filter
spi_device.ADDR_SWAP_MASK0x6c4Address Swap Mask register.
spi_device.ADDR_SWAP_DATA0x704The address value for the address swap feature.
spi_device.PAYLOAD_SWAP_MASK0x744Write Data Swap in the passthrough mode.
spi_device.PAYLOAD_SWAP_DATA0x784Write Data Swap in the passthrough mode.
spi_device.CMD_INFO_00x7c4Command Info register.
spi_device.CMD_INFO_10x804Command Info register.
spi_device.CMD_INFO_20x844Command Info register.
spi_device.CMD_INFO_30x884Command Info register.
spi_device.CMD_INFO_40x8c4Command Info register.
spi_device.CMD_INFO_50x904Command Info register.
spi_device.CMD_INFO_60x944Command Info register.
spi_device.CMD_INFO_70x984Command Info register.
spi_device.CMD_INFO_80x9c4Command Info register.
spi_device.CMD_INFO_90xa04Command Info register.
spi_device.CMD_INFO_100xa44Command Info register.
spi_device.CMD_INFO_110xa84Command Info register.
spi_device.CMD_INFO_120xac4Command Info register.
spi_device.CMD_INFO_130xb04Command Info register.
spi_device.CMD_INFO_140xb44Command Info register.
spi_device.CMD_INFO_150xb84Command Info register.
spi_device.CMD_INFO_160xbc4Command Info register.
spi_device.CMD_INFO_170xc04Command Info register.
spi_device.CMD_INFO_180xc44Command Info register.
spi_device.CMD_INFO_190xc84Command Info register.
spi_device.CMD_INFO_200xcc4Command Info register.
spi_device.CMD_INFO_210xd04Command Info register.
spi_device.CMD_INFO_220xd44Command Info register.
spi_device.CMD_INFO_230xd84Command Info register.
spi_device.CMD_INFO_EN4B0xdc4Opcode for EN4B.
spi_device.CMD_INFO_EX4B0xe04Opcode for EX4B
spi_device.CMD_INFO_WREN0xe44Opcode for Write Enable (WREN)
spi_device.CMD_INFO_WRDI0xe84Opcode for Write Disable (WRDI)
spi_device.TPM_CAP0x8004TPM HWIP Capability register.
spi_device.TPM_CFG0x8044TPM Configuration register.
spi_device.TPM_STATUS0x8084TPM submodule state register.
spi_device.TPM_ACCESS_00x80c4TPM_ACCESS_x register.
spi_device.TPM_ACCESS_10x8104TPM_ACCESS_x register.
spi_device.TPM_STS0x8144TPM_STS_x register.
spi_device.TPM_INTF_CAPABILITY0x8184TPM_INTF_CAPABILITY
spi_device.TPM_INT_ENABLE0x81c4TPM_INT_ENABLE
spi_device.TPM_INT_VECTOR0x8204TPM_INT_VECTOR
spi_device.TPM_INT_STATUS0x8244TPM_INT_STATUS
spi_device.TPM_DID_VID0x8284TPM_DID/ TPM_VID register
spi_device.TPM_RID0x82c4TPM_RID
spi_device.TPM_CMD_ADDR0x8304TPM Command and Address buffer
spi_device.TPM_READ_FIFO0x8344TPM Read command return data FIFO.
spi_device.egress_buffer0x10003392SPI internal egress buffer.
spi_device.ingress_buffer0x1e00448SPI internal ingress buffer.

INTR_STATE

Interrupt State Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7rw1c0x0tpm_rdfifo_dropTPM RdFIFO data dropped. Data was dropped from the RdFIFO. Data was written while a read command was not active, and it was not accepted. This can occur when the host aborts a read command.
6rw1c0x0tpm_rdfifo_cmd_endTPM RdFIFO command ended. The TPM Read command targeting the RdFIFO ended. Check TPM_STATUS.rdfifo_aborted to see if the transaction completed.
5ro0x0tpm_header_not_emptyTPM Header(Command/Address) buffer available
4rw1c0x0readbuf_flipRead buffer flipped event. The host system accesses other side of buffer.
3rw1c0x0readbuf_watermarkRead Buffer Threshold event. The host system accesses greater than or equal to the threshold of a buffer.
2rw1c0x0upload_payload_overflowUpload payload overflow event. When a SPI Host system issues a command with payload more than 256B, this event is reported. When it happens, SW should read the last written payload index CSR to figure out the starting address of the last 256B.
1rw1c0x0upload_payload_not_emptyUpload payload is not empty. The event occurs after SPI transaction completed
0rw1c0x0upload_cmdfifo_not_emptyUpload Command FIFO is not empty

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7rw0x0tpm_rdfifo_dropEnable interrupt when INTR_STATE.tpm_rdfifo_drop is set.
6rw0x0tpm_rdfifo_cmd_endEnable interrupt when INTR_STATE.tpm_rdfifo_cmd_end is set.
5rw0x0tpm_header_not_emptyEnable interrupt when INTR_STATE.tpm_header_not_empty is set.
4rw0x0readbuf_flipEnable interrupt when INTR_STATE.readbuf_flip is set.
3rw0x0readbuf_watermarkEnable interrupt when INTR_STATE.readbuf_watermark is set.
2rw0x0upload_payload_overflowEnable interrupt when INTR_STATE.upload_payload_overflow is set.
1rw0x0upload_payload_not_emptyEnable interrupt when INTR_STATE.upload_payload_not_empty is set.
0rw0x0upload_cmdfifo_not_emptyEnable interrupt when INTR_STATE.upload_cmdfifo_not_empty is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7wo0x0tpm_rdfifo_dropWrite 1 to force INTR_STATE.tpm_rdfifo_drop to 1.
6wo0x0tpm_rdfifo_cmd_endWrite 1 to force INTR_STATE.tpm_rdfifo_cmd_end to 1.
5wo0x0tpm_header_not_emptyWrite 1 to force INTR_STATE.tpm_header_not_empty to 1.
4wo0x0readbuf_flipWrite 1 to force INTR_STATE.readbuf_flip to 1.
3wo0x0readbuf_watermarkWrite 1 to force INTR_STATE.readbuf_watermark to 1.
2wo0x0upload_payload_overflowWrite 1 to force INTR_STATE.upload_payload_overflow to 1.
1wo0x0upload_payload_not_emptyWrite 1 to force INTR_STATE.upload_payload_not_empty to 1.
0wo0x0upload_cmdfifo_not_emptyWrite 1 to force INTR_STATE.upload_cmdfifo_not_empty to 1.

ALERT_TEST

Alert Test Register

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.

CONTROL

Control register

  • Offset: 0x10
  • Reset default: 0x10
  • Reset mask: 0x33

Fields

BitsTypeResetName
31:6Reserved
5:4rw0x1MODE
3:2Reserved
1rw1s0x0FLASH_READ_BUFFER_CLR
0rw1s0x0FLASH_STATUS_FIFO_CLR

CONTROL . MODE

SPI Device flash operation mode.

ValueNameDescription
0x0disabledSPI Flash operations disabled. SPI device flash operations are disabled, and all transactions are ignored. Note that SPI TPM operations are controlled by !!TPM_CFG
0x1flashmodeSPI Flash Emulation mode. In flash mode, SPI Device IP accepts SPI Flash commands and processes internally, then returns data for the read commands. HW processes the Status, JEDEC ID, SFDP commands. The current version does not support Dual/Quad IO and QPI commands.
0x2passthroughIn passthrough mode, SPI Device IP forwards the incoming SPI flash traffics to the attached downstream flash device. HW may processes commands internally and returns data. SW may configure the device to drop inadmissable commands.

Other values are reserved.

CONTROL . FLASH_READ_BUFFER_CLR

Set to clear the read buffer state.

When set to 1, resets the flash read buffer state that tracks the host read address. The reset should only be used when the upstream SPI host is known to be inactive. This function is intended to allow restoring initial values when the upstream SPI host is reset.

This CSR automatically resets to 0.

CONTROL . FLASH_STATUS_FIFO_CLR

Set to clear the flash status FIFO.

When set to 1, resets the flash status FIFO used for synchronizing changes from firmware. The reset should only be used when the upstream SPI host is known to be inactive. This function is intended to allow restoring initial values when the upstream SPI host is reset.

This CSR automatically resets to 0.

CFG

Configuration Register

  • Offset: 0x14
  • Reset default: 0x0
  • Reset mask: 0x100000c

Fields

BitsTypeResetNameDescription
31:25Reserved
24rw0x0mailbox_enMailbox enable. If 1, in the flash and passthrough mode, the IP checks the incoming address and return from the internal Mailbox buffer if the address falls into the MAILBOX range (MAILBOX_ADDR:MAILBOX_ADDR+MAILBOX_SIZE)}.
23:4Reserved
3rw0x0rx_orderRX bit order on SDI. Module stores bitstream from MSB to LSB if value is 0.
2rw0x0tx_orderTX bit order on SDO. 0 for MSB to LSB, 1 for LSB to MSB
1:0Reserved

STATUS

SPI Device status register

  • Offset: 0x18
  • Reset default: 0x60
  • Reset mask: 0x60

Fields

BitsTypeResetNameDescription
31:7Reserved
6ro0x1tpm_csbDirect input of TPM CSb
5ro0x1csbDirect input of CSb signal
4:0Reserved

INTERCEPT_EN

Intercept Passthrough datapath.

  • Offset: 0x1c
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3rw0x0mbxIf set, Read Command to Mailbox region is processed internally.
2rw0x0sfdpIf set, Read SFDP is processed internally.
1rw0x0jedecIf set, Read JEDEC ID is processed internally.
0rw0x0statusIf set, Read Status is processed internally.

ADDR_MODE

Flash address mode configuration

This register shows the current address mode and pending changes. It is updated by the HW when the command phase completes.

  • Offset: 0x20
  • Reset default: 0x0
  • Reset mask: 0x80000001

Fields

BitsTypeResetName
31roxpending
30:1Reserved
0rwxaddr_4b_en

ADDR_MODE . pending

SW-originated change is pending.

This bit is 1 whenever the current value of addr_4b_en has yet to sync with the SPI domain. If an EN4B or EX4B command arrives next, the current value in addr_4b_en will be ignored, and the SPI flash command will take priority, with an update to addr_4b_en to match the command’s result.

ADDR_MODE . addr_4b_en

4B Address Mode enable.

This field configures the internal module to receive 32 bits of the SPI commands. The affected commands are the SPI read commands except QPI, and program commands. It is expected for SW to configure this field at the configuration stage and release control to HW until the next reset.

Even though Read SFDP command has address fields, the SFDP command is not affected by this field. The command always parse 24 bits on the SPI line 0 following the SPI command as the address field.

This field has noteworthy read behavior. If a software-initiated change is still pending the sync to the SPI domain, this bit will reflect the value to be sent. Otherwise, this field will reflect the current value observed in the SPI domain.

LAST_READ_ADDR

Last Read Address

This register shows the last address accessed by the host system. It is updated by the HW when CSb is de-asserted.

  • Offset: 0x24
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0roxaddrLast address

FLASH_STATUS

SPI Flash Status register.

This register emulates the SPI Flash Status 3, 2, 1 registers. bit [7:0] is for Status register, bit [15:8] is for Status-2 register, and bit [23:16] is for Status-3 register. It is SW responsibility to maintain this register value up to date.

The HW latches the value when SPI Flash transaction begins. Any updates during the transaction will be updated after the transaction is completed.

  • Offset: 0x28
  • Reset default: 0x0
  • Reset mask: 0xffffff

Fields

BitsTypeResetName
31:24Reserved
23:2rwxstatus
1rw0cxwel
0rw0cxbusy

FLASH_STATUS . status

Rest of the status register.

Fields other than the bit 0 (BUSY) and bit 1 (WEL) fields are SW-maintained fields. HW just reads and returns to the host system.

  • [ 2]: BP0
  • [ 3]: BP1
  • [ 4]: BP2
  • [ 5]: TB
  • [ 6]: SEC
  • [ 7]: SRP0
  • [ 8]: SRP1
  • [ 9]: QE
  • [11]: LB1
  • [12]: LB2
  • [13]: LB3
  • [14]: CMP
  • [15]: SUS
  • [18]: WPS
  • [21]: DRV0
  • [22]: DRV1
  • [23]: HOLD /RST

FLASH_STATUS . wel

WEL signal is cleared when CSb is high. SW should read back the register to confirm the value is cleared.

Bit 1 (WEL) is a SW modifiable and HW modifiable field. HW updates the WEL field when WRDI or WREN command is received.

FLASH_STATUS . busy

BUSY signal is cleared when CSb is high. SW should read back the register to confirm the value is cleared.

JEDEC_CC

JEDEC Continuation Code configuration register.

Read JEDEC ID must return the continuation code if the manufacturer ID is not shown in the first page of JEDEC table. This register controls the Continuation Code.

  • Offset: 0x2c
  • Reset default: 0x7f
  • Reset mask: 0xffff

Fields

BitsTypeResetNameDescription
31:16Reserved
15:8rw0x0num_ccThe number that Continuation Code repeats
7:0rw0x7fccContinuation Code byte

JEDEC_ID

JEDEC ID register.

  • Offset: 0x30
  • Reset default: 0x0
  • Reset mask: 0xffffff

Fields

BitsTypeResetNameDescription
31:24Reserved
23:16rw0x0mfManufacturer ID
15:0rw0x0idDevice ID

READ_THRESHOLD

Read Buffer threshold register.

  • Offset: 0x34
  • Reset default: 0x0
  • Reset mask: 0x3ff

Fields

BitsTypeResetNameDescription
31:10Reserved
9:0rw0x0thresholdIf 0, disable the watermark. If non-zero, when the host access above or equal to the threshold, it reports an interrupt. The value is byte-granularity not SRAM index.

MAILBOX_ADDR

Mailbox Base address register.

The mailbox size is fixed. In this version of IP, the size is 1kB. Lower 10 bits of the Mailbox address is tied to 0.

  • Offset: 0x38
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0addrMailbox Address. Lower 10 bits are ignored

UPLOAD_STATUS

Upload module status register.

  • Offset: 0x3c
  • Reset default: 0x0
  • Reset mask: 0x9f9f

Fields

BitsTypeResetNameDescription
31:16Reserved
15ro0x0addrfifo_notemptyUpload Address FIFO Not Empty
14:13Reserved
12:8ro0x0addrfifo_depthAddress FIFO Entry
7ro0x0cmdfifo_notemptyUpload Command FIFO Not Empty
6:5Reserved
4:0ro0x0cmdfifo_depthCommand FIFO Entry

UPLOAD_STATUS2

Upload module status 2 register.

This register contains payload related status. payload_depth indicates the payload size (from 0 to 256 bytes).

payload_start_idx indicates the start of the 256B. This stays 0 usually. However, when the SPI host system issues more than 256B of payload in a command, this field may not be 0. For example, if the system issues 258B payload, the payload_depth is 256 (as the IP only holds 256B of payload), the payload_start_idx is 2. SW should read from 2 to 255 then 0 and 1.

  • Offset: 0x40
  • Reset default: 0x0
  • Reset mask: 0xff01ff

Fields

BitsTypeResetNameDescription
31:24Reserved
23:16ro0x0payload_start_idxPayload Start Index
15:9Reserved
8:0ro0x0payload_depthPayload buffer depth

UPLOAD_CMDFIFO

Command Fifo Read Port.

  • Offset: 0x44
  • Reset default: 0x0
  • Reset mask: 0xe0ff

Fields

BitsTypeResetNameDescription
31:16Reserved
15roxaddr4b_mode1 if address mode at command time is 4 Bytes, else 3 Bytes
14roxwelState of WEL bit at command time
13roxbusyState of BUSY bit at command time
12:8Reserved
7:0roxdatacommand opcode

UPLOAD_ADDRFIFO

Address Fifo Read Port.

  • Offset: 0x48
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0roxdataread data

CMD_FILTER_0

Command Filter

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

  • Offset: 0x4c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31rw0x0filter_31If 1, command will be filtered
30rw0x0filter_30If 1, command will be filtered
29rw0x0filter_29If 1, command will be filtered
28rw0x0filter_28If 1, command will be filtered
27rw0x0filter_27If 1, command will be filtered
26rw0x0filter_26If 1, command will be filtered
25rw0x0filter_25If 1, command will be filtered
24rw0x0filter_24If 1, command will be filtered
23rw0x0filter_23If 1, command will be filtered
22rw0x0filter_22If 1, command will be filtered
21rw0x0filter_21If 1, command will be filtered
20rw0x0filter_20If 1, command will be filtered
19rw0x0filter_19If 1, command will be filtered
18rw0x0filter_18If 1, command will be filtered
17rw0x0filter_17If 1, command will be filtered
16rw0x0filter_16If 1, command will be filtered
15rw0x0filter_15If 1, command will be filtered
14rw0x0filter_14If 1, command will be filtered
13rw0x0filter_13If 1, command will be filtered
12rw0x0filter_12If 1, command will be filtered
11rw0x0filter_11If 1, command will be filtered
10rw0x0filter_10If 1, command will be filtered
9rw0x0filter_9If 1, command will be filtered
8rw0x0filter_8If 1, command will be filtered
7rw0x0filter_7If 1, command will be filtered
6rw0x0filter_6If 1, command will be filtered
5rw0x0filter_5If 1, command will be filtered
4rw0x0filter_4If 1, command will be filtered
3rw0x0filter_3If 1, command will be filtered
2rw0x0filter_2If 1, command will be filtered
1rw0x0filter_1If 1, command will be filtered
0rw0x0filter_0If 1, command will be filtered

CMD_FILTER_1

Command Filter

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

  • Offset: 0x50
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31rw0x0filter_63For SPI_DEVICE1
30rw0x0filter_62For SPI_DEVICE1
29rw0x0filter_61For SPI_DEVICE1
28rw0x0filter_60For SPI_DEVICE1
27rw0x0filter_59For SPI_DEVICE1
26rw0x0filter_58For SPI_DEVICE1
25rw0x0filter_57For SPI_DEVICE1
24rw0x0filter_56For SPI_DEVICE1
23rw0x0filter_55For SPI_DEVICE1
22rw0x0filter_54For SPI_DEVICE1
21rw0x0filter_53For SPI_DEVICE1
20rw0x0filter_52For SPI_DEVICE1
19rw0x0filter_51For SPI_DEVICE1
18rw0x0filter_50For SPI_DEVICE1
17rw0x0filter_49For SPI_DEVICE1
16rw0x0filter_48For SPI_DEVICE1
15rw0x0filter_47For SPI_DEVICE1
14rw0x0filter_46For SPI_DEVICE1
13rw0x0filter_45For SPI_DEVICE1
12rw0x0filter_44For SPI_DEVICE1
11rw0x0filter_43For SPI_DEVICE1
10rw0x0filter_42For SPI_DEVICE1
9rw0x0filter_41For SPI_DEVICE1
8rw0x0filter_40For SPI_DEVICE1
7rw0x0filter_39For SPI_DEVICE1
6rw0x0filter_38For SPI_DEVICE1
5rw0x0filter_37For SPI_DEVICE1
4rw0x0filter_36For SPI_DEVICE1
3rw0x0filter_35For SPI_DEVICE1
2rw0x0filter_34For SPI_DEVICE1
1rw0x0filter_33For SPI_DEVICE1
0rw0x0filter_32For SPI_DEVICE1

CMD_FILTER_2

Command Filter

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

  • Offset: 0x54
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31rw0x0filter_95For SPI_DEVICE2
30rw0x0filter_94For SPI_DEVICE2
29rw0x0filter_93For SPI_DEVICE2
28rw0x0filter_92For SPI_DEVICE2
27rw0x0filter_91For SPI_DEVICE2
26rw0x0filter_90For SPI_DEVICE2
25rw0x0filter_89For SPI_DEVICE2
24rw0x0filter_88For SPI_DEVICE2
23rw0x0filter_87For SPI_DEVICE2
22rw0x0filter_86For SPI_DEVICE2
21rw0x0filter_85For SPI_DEVICE2
20rw0x0filter_84For SPI_DEVICE2
19rw0x0filter_83For SPI_DEVICE2
18rw0x0filter_82For SPI_DEVICE2
17rw0x0filter_81For SPI_DEVICE2
16rw0x0filter_80For SPI_DEVICE2
15rw0x0filter_79For SPI_DEVICE2
14rw0x0filter_78For SPI_DEVICE2
13rw0x0filter_77For SPI_DEVICE2
12rw0x0filter_76For SPI_DEVICE2
11rw0x0filter_75For SPI_DEVICE2
10rw0x0filter_74For SPI_DEVICE2
9rw0x0filter_73For SPI_DEVICE2
8rw0x0filter_72For SPI_DEVICE2
7rw0x0filter_71For SPI_DEVICE2
6rw0x0filter_70For SPI_DEVICE2
5rw0x0filter_69For SPI_DEVICE2
4rw0x0filter_68For SPI_DEVICE2
3rw0x0filter_67For SPI_DEVICE2
2rw0x0filter_66For SPI_DEVICE2
1rw0x0filter_65For SPI_DEVICE2
0rw0x0filter_64For SPI_DEVICE2

CMD_FILTER_3

Command Filter

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

  • Offset: 0x58
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31rw0x0filter_127For SPI_DEVICE3
30rw0x0filter_126For SPI_DEVICE3
29rw0x0filter_125For SPI_DEVICE3
28rw0x0filter_124For SPI_DEVICE3
27rw0x0filter_123For SPI_DEVICE3
26rw0x0filter_122For SPI_DEVICE3
25rw0x0filter_121For SPI_DEVICE3
24rw0x0filter_120For SPI_DEVICE3
23rw0x0filter_119For SPI_DEVICE3
22rw0x0filter_118For SPI_DEVICE3
21rw0x0filter_117For SPI_DEVICE3
20rw0x0filter_116For SPI_DEVICE3
19rw0x0filter_115For SPI_DEVICE3
18rw0x0filter_114For SPI_DEVICE3
17rw0x0filter_113For SPI_DEVICE3
16rw0x0filter_112For SPI_DEVICE3
15rw0x0filter_111For SPI_DEVICE3
14rw0x0filter_110For SPI_DEVICE3
13rw0x0filter_109For SPI_DEVICE3
12rw0x0filter_108For SPI_DEVICE3
11rw0x0filter_107For SPI_DEVICE3
10rw0x0filter_106For SPI_DEVICE3
9rw0x0filter_105For SPI_DEVICE3
8rw0x0filter_104For SPI_DEVICE3
7rw0x0filter_103For SPI_DEVICE3
6rw0x0filter_102For SPI_DEVICE3
5rw0x0filter_101For SPI_DEVICE3
4rw0x0filter_100For SPI_DEVICE3
3rw0x0filter_99For SPI_DEVICE3
2rw0x0filter_98For SPI_DEVICE3
1rw0x0filter_97For SPI_DEVICE3
0rw0x0filter_96For SPI_DEVICE3

CMD_FILTER_4

Command Filter

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

  • Offset: 0x5c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31rw0x0filter_159For SPI_DEVICE4
30rw0x0filter_158For SPI_DEVICE4
29rw0x0filter_157For SPI_DEVICE4
28rw0x0filter_156For SPI_DEVICE4
27rw0x0filter_155For SPI_DEVICE4
26rw0x0filter_154For SPI_DEVICE4
25rw0x0filter_153For SPI_DEVICE4
24rw0x0filter_152For SPI_DEVICE4
23rw0x0filter_151For SPI_DEVICE4
22rw0x0filter_150For SPI_DEVICE4
21rw0x0filter_149For SPI_DEVICE4
20rw0x0filter_148For SPI_DEVICE4
19rw0x0filter_147For SPI_DEVICE4
18rw0x0filter_146For SPI_DEVICE4
17rw0x0filter_145For SPI_DEVICE4
16rw0x0filter_144For SPI_DEVICE4
15rw0x0filter_143For SPI_DEVICE4
14rw0x0filter_142For SPI_DEVICE4
13rw0x0filter_141For SPI_DEVICE4
12rw0x0filter_140For SPI_DEVICE4
11rw0x0filter_139For SPI_DEVICE4
10rw0x0filter_138For SPI_DEVICE4
9rw0x0filter_137For SPI_DEVICE4
8rw0x0filter_136For SPI_DEVICE4
7rw0x0filter_135For SPI_DEVICE4
6rw0x0filter_134For SPI_DEVICE4
5rw0x0filter_133For SPI_DEVICE4
4rw0x0filter_132For SPI_DEVICE4
3rw0x0filter_131For SPI_DEVICE4
2rw0x0filter_130For SPI_DEVICE4
1rw0x0filter_129For SPI_DEVICE4
0rw0x0filter_128For SPI_DEVICE4

CMD_FILTER_5

Command Filter

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

  • Offset: 0x60
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31rw0x0filter_191For SPI_DEVICE5
30rw0x0filter_190For SPI_DEVICE5
29rw0x0filter_189For SPI_DEVICE5
28rw0x0filter_188For SPI_DEVICE5
27rw0x0filter_187For SPI_DEVICE5
26rw0x0filter_186For SPI_DEVICE5
25rw0x0filter_185For SPI_DEVICE5
24rw0x0filter_184For SPI_DEVICE5
23rw0x0filter_183For SPI_DEVICE5
22rw0x0filter_182For SPI_DEVICE5
21rw0x0filter_181For SPI_DEVICE5
20rw0x0filter_180For SPI_DEVICE5
19rw0x0filter_179For SPI_DEVICE5
18rw0x0filter_178For SPI_DEVICE5
17rw0x0filter_177For SPI_DEVICE5
16rw0x0filter_176For SPI_DEVICE5
15rw0x0filter_175For SPI_DEVICE5
14rw0x0filter_174For SPI_DEVICE5
13rw0x0filter_173For SPI_DEVICE5
12rw0x0filter_172For SPI_DEVICE5
11rw0x0filter_171For SPI_DEVICE5
10rw0x0filter_170For SPI_DEVICE5
9rw0x0filter_169For SPI_DEVICE5
8rw0x0filter_168For SPI_DEVICE5
7rw0x0filter_167For SPI_DEVICE5
6rw0x0filter_166For SPI_DEVICE5
5rw0x0filter_165For SPI_DEVICE5
4rw0x0filter_164For SPI_DEVICE5
3rw0x0filter_163For SPI_DEVICE5
2rw0x0filter_162For SPI_DEVICE5
1rw0x0filter_161For SPI_DEVICE5
0rw0x0filter_160For SPI_DEVICE5

CMD_FILTER_6

Command Filter

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

  • Offset: 0x64
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31rw0x0filter_223For SPI_DEVICE6
30rw0x0filter_222For SPI_DEVICE6
29rw0x0filter_221For SPI_DEVICE6
28rw0x0filter_220For SPI_DEVICE6
27rw0x0filter_219For SPI_DEVICE6
26rw0x0filter_218For SPI_DEVICE6
25rw0x0filter_217For SPI_DEVICE6
24rw0x0filter_216For SPI_DEVICE6
23rw0x0filter_215For SPI_DEVICE6
22rw0x0filter_214For SPI_DEVICE6
21rw0x0filter_213For SPI_DEVICE6
20rw0x0filter_212For SPI_DEVICE6
19rw0x0filter_211For SPI_DEVICE6
18rw0x0filter_210For SPI_DEVICE6
17rw0x0filter_209For SPI_DEVICE6
16rw0x0filter_208For SPI_DEVICE6
15rw0x0filter_207For SPI_DEVICE6
14rw0x0filter_206For SPI_DEVICE6
13rw0x0filter_205For SPI_DEVICE6
12rw0x0filter_204For SPI_DEVICE6
11rw0x0filter_203For SPI_DEVICE6
10rw0x0filter_202For SPI_DEVICE6
9rw0x0filter_201For SPI_DEVICE6
8rw0x0filter_200For SPI_DEVICE6
7rw0x0filter_199For SPI_DEVICE6
6rw0x0filter_198For SPI_DEVICE6
5rw0x0filter_197For SPI_DEVICE6
4rw0x0filter_196For SPI_DEVICE6
3rw0x0filter_195For SPI_DEVICE6
2rw0x0filter_194For SPI_DEVICE6
1rw0x0filter_193For SPI_DEVICE6
0rw0x0filter_192For SPI_DEVICE6

CMD_FILTER_7

Command Filter

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

  • Offset: 0x68
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31rw0x0filter_255For SPI_DEVICE7
30rw0x0filter_254For SPI_DEVICE7
29rw0x0filter_253For SPI_DEVICE7
28rw0x0filter_252For SPI_DEVICE7
27rw0x0filter_251For SPI_DEVICE7
26rw0x0filter_250For SPI_DEVICE7
25rw0x0filter_249For SPI_DEVICE7
24rw0x0filter_248For SPI_DEVICE7
23rw0x0filter_247For SPI_DEVICE7
22rw0x0filter_246For SPI_DEVICE7
21rw0x0filter_245For SPI_DEVICE7
20rw0x0filter_244For SPI_DEVICE7
19rw0x0filter_243For SPI_DEVICE7
18rw0x0filter_242For SPI_DEVICE7
17rw0x0filter_241For SPI_DEVICE7
16rw0x0filter_240For SPI_DEVICE7
15rw0x0filter_239For SPI_DEVICE7
14rw0x0filter_238For SPI_DEVICE7
13rw0x0filter_237For SPI_DEVICE7
12rw0x0filter_236For SPI_DEVICE7
11rw0x0filter_235For SPI_DEVICE7
10rw0x0filter_234For SPI_DEVICE7
9rw0x0filter_233For SPI_DEVICE7
8rw0x0filter_232For SPI_DEVICE7
7rw0x0filter_231For SPI_DEVICE7
6rw0x0filter_230For SPI_DEVICE7
5rw0x0filter_229For SPI_DEVICE7
4rw0x0filter_228For SPI_DEVICE7
3rw0x0filter_227For SPI_DEVICE7
2rw0x0filter_226For SPI_DEVICE7
1rw0x0filter_225For SPI_DEVICE7
0rw0x0filter_224For SPI_DEVICE7

ADDR_SWAP_MASK

Address Swap Mask register.

This register is used in the SPI passthrough mode. If any of bits in this register is set, the corresponding address bit in the SPI Read commands is replaced with the data from ADDR_SWAP_DATA.

If 3B address mode is active, upper 8bit [31:24] is ignored.

  • Offset: 0x6c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0maskWhen a bit is 1, the SPI read address to the downstream SPI Flash device is swapped to ADDR_SWAP_DATA.

ADDR_SWAP_DATA

The address value for the address swap feature.

  • Offset: 0x70
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0dataDesired value to be swapped for the SPI read commands.

PAYLOAD_SWAP_MASK

Write Data Swap in the passthrough mode.

PAYLOAD_SWAP_MASK CSR provides the SW to change certain bits in the first 4 bytes of the write payload in the passthrough mode.

  • Offset: 0x74
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0maskbyte mask

PAYLOAD_SWAP_DATA

Write Data Swap in the passthrough mode.

PAYLOAD_SWAP_DATA combined with PAYLOAD_SWAP_MASK provides the SW to change certain bits in the first 4 bytes of the write payload in the passthrough mode.

The register should be written in Little-Endian order. [7:0] bits are processed in the first received payload byte. [31:24] bits for the 4th byte.

  • Offset: 0x78
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0datareplaced data

CMD_INFO

Command Info register.

  • Reset default: 0x7000
  • Reset mask: 0x83ffffff

Instances

NameOffset
CMD_INFO_00x7c
CMD_INFO_10x80
CMD_INFO_20x84
CMD_INFO_30x88
CMD_INFO_40x8c
CMD_INFO_50x90
CMD_INFO_60x94
CMD_INFO_70x98
CMD_INFO_80x9c
CMD_INFO_90xa0
CMD_INFO_100xa4
CMD_INFO_110xa8
CMD_INFO_120xac
CMD_INFO_130xb0
CMD_INFO_140xb4
CMD_INFO_150xb8
CMD_INFO_160xbc
CMD_INFO_170xc0
CMD_INFO_180xc4
CMD_INFO_190xc8
CMD_INFO_200xcc
CMD_INFO_210xd0
CMD_INFO_220xd4
CMD_INFO_230xd8

Fields

BitsTypeResetName
31rw0x0valid
30:26Reserved
25rw0x0busy
24rw0x0upload
23:22rw0x0read_pipeline_mode
21rw0x0payload_swap_en
20rw0x0payload_dir
19:16rw0x0payload_en
15rw0x0dummy_en
14:12rw0x7dummy_size
11rw0x0mbyte_en
10rw0x0addr_swap_en
9:8rw0x0addr_mode
7:0rw0x0opcode

CMD_INFO . valid

Set to 1 if the config in the register is valid

CMD_INFO . busy

Set to 1 to set the BUSY bit in the FLASH_STATUS when the command is received. This bit is active only when upload bit is set.

CMD_INFO . upload

Set to 1 to upload the command.

If upload field in the command info entry is set, the cmdparse activates the upload submodule when the opcode is received. addr_en, addr_4B_affected, and addr_4b_forced (TBD) affect the upload functionality. The three address related configs defines the command address field size.

The logic assumes the following SPI input stream as payload, which max size is 256B. If the command exceeds the maximum payload size 256B, the logic wraps the payload and overwrites.

CMD_INFO . read_pipeline_mode

Add 2-stage pipeline to read payload.

If read_pipeline_mode is not set to zero_stages, the read logic adds a 2-stage pipeline to the read data for this command. This read pipeline enables higher throughput for certain read commands in passthrough mode.

payload_dir must be set to PayloadOut: payload_pipeline_en only works with read data. It may be used with any IO mode, but general host compatibility is likely limited to Quad Read. If this pipeline is used for passthrough, the internal SFDP should report 2 additional dummy cycles compared to the downstream flash. SFDP read commands should be processed internally, and dummy_size should still reflect the downstream device’s dummy cycle count.

ValueNameDescription
0x0zero_stagesBypass the 2-stage read pipeline. This mode is for ordinary SPI flash operation. Passthrough read data flows combinatorially from input pads to output pads.
0x1two_stages_half_cycle2-stage read pipeline with half-cycle sampling. In this mode, the 2-stage read pipeline is enabled. Read data appears 2 cycles later than the zero_stages option. In addition, read data originating from the downstream flash is first sampled on the normal sampling edge for half-cycle sampling.
0x2two_stages_full_cycle2-stage read pipeline with full-cycle sampling. In this mode, the 2-stage read pipeline is enabled. Read data appears 2 cycles later than the zero_stages option. In addition, read data originating from the downstream flash is first sampled on the next launch edge. In other words, the internal pipeline performs full-cycle sampling of the downstream flash’s response.

Other values are reserved.

CMD_INFO . payload_swap_en

Swap the first byte of the write payload.

If payload_swap_en is set, the passthrough logic swaps the first byte of the write payload with DATA_SWAP CSR.

payload_swap_en only works with write data and SingleIO mode. payload_en must be 4’b 0001 and paylod_dir to be PayloadIn.

CMD_INFO . payload_dir

Set to 1 if the command returns data. If 0, the payload sends to the downstream Flash device.

ValueNameDescription
0x0PayloadInFrom host to the downstream flash device
0x1PayloadOutFrom the downstream flash device to the host

CMD_INFO . payload_en

Payload Enable per SPI lane.

Set to non-zero if the command has payload at the end of the protocol. This field has four bits. Each bit represents the SPI line. If a command is a Single IO command and returns data to the host system, the data is returned on the MISO line (IO[1]). In this case, SW sets payload_en to 4’b 0010.

CMD_INFO . dummy_en

Set to 1 if the command has a dummy cycle following the address field.

CMD_INFO . dummy_size

The number of dummy cycles -1 for the command

CMD_INFO . mbyte_en

If 1, the command has a MByte field following the address field. This is set to 1 for DualIO, QuadIO commands.

CMD_INFO . addr_swap_en

This field is used in the passthrough logic. If this field is set to 1, the address in the passthrough command is replaced to the preconfigured value.

CMD_INFO . addr_mode

Command address mode

A command can have four modes:

  • 0: Command does not have an address field
  • 1: CFG.addr_4b_en decides the address size (3B/4B)
  • 2: Address size is always 3B regardless of CFG.addr_4b_en
  • 3: Address size is always 4B regardless of CFG.addr_4b_en
ValueNameDescription
0x0AddrDisabledAddress field does not exist
0x1AddrCfgCFG.addr_4b_en determines the address size
0x2Addr3BAddress size in the command is always 3B.
0x3Addr4BAddress size in the command is always 4B.

CMD_INFO . opcode

Command Opcode

CMD_INFO_EN4B

Opcode for EN4B.

If the register is active, it affects in flash / passthrough modes.

  • Offset: 0xdc
  • Reset default: 0x0
  • Reset mask: 0x800000ff

Fields

BitsTypeResetNameDescription
31rw0x0validIf 1, Opcode affects
30:8Reserved
7:0rw0x0opcodeEN4B opcode

CMD_INFO_EX4B

Opcode for EX4B

  • Offset: 0xe0
  • Reset default: 0x0
  • Reset mask: 0x800000ff

Fields

BitsTypeResetNameDescription
31rw0x0validIf 1, Opcode affects
30:8Reserved
7:0rw0x0opcodeEX4B opcode

CMD_INFO_WREN

Opcode for Write Enable (WREN)

  • Offset: 0xe4
  • Reset default: 0x0
  • Reset mask: 0x800000ff

Fields

BitsTypeResetNameDescription
31rw0x0validIf 1, opcode affects
30:8Reserved
7:0rw0x0opcodeWREN opcode

CMD_INFO_WRDI

Opcode for Write Disable (WRDI)

  • Offset: 0xe8
  • Reset default: 0x0
  • Reset mask: 0x800000ff

Fields

BitsTypeResetNameDescription
31rw0x0validIf 1, opcode affects
30:8Reserved
7:0rw0x0opcodeWRDI opcode

TPM_CAP

TPM HWIP Capability register.

This register shows the features the current TPM HWIP supports.

  • Offset: 0x800
  • Reset default: 0x660100
  • Reset mask: 0x7701ff

Fields

BitsTypeResetName
31:23Reserved
22:20ro0x6max_rd_size
19Reserved
18:16ro0x6max_wr_size
15:9Reserved
8ro0x1locality
7:0ro0x0rev

TPM_CAP . max_rd_size

The maximum read size in bytes the TPM submodule supports. The value is the exponent of the 2.

  • 3’b 010: Support up to 4B
  • 3’b 011: Support up to 8B
  • 3’b 100: Support up to 16B
  • 3’b 101: Support up to 32B
  • 3’b 110: Support up to 64B

All other values are reserved.

It is not recommended for SW to advertise TPM supporting more than max_rd_size to the South Bridge.

TPM_CAP . max_wr_size

The maximum write size in bytes the TPM submodule supports. The value is the exponent of the 2.

  • 3’b 010: Support up to 4B
  • 3’b 011: Support up to 8B
  • 3’b 100: Support up to 16B
  • 3’b 101: Support up to 32B
  • 3’b 110: Support up to 64B

All other values are reserved.

It is not recommended for SW to advertise TPM supporting more than max_wr_size to the South Bridge.

TPM_CAP . locality

If 1, the TPM submodule supports 5 Locality. If 0, only one Locality is provided

TPM_CAP . rev

Revision of the TPM submodule

TPM_CFG

TPM Configuration register.

  • Offset: 0x804
  • Reset default: 0x0
  • Reset mask: 0x1f

Fields

BitsTypeResetName
31:5Reserved
4rw0x0invalid_locality
3rw0x0tpm_reg_chk_dis
2rw0x0hw_reg_dis
1rw0x0tpm_mode
0rw0x0en

TPM_CFG . invalid_locality

If 1, TPM submodule returns the invalid data (0xFF) for the out of the max Locality request. If it is a write request, HW still uploads the command and address. SW needs to process the incoming invalid command.

If 0, TPM submodule uploads the TPM command and address. The SW may write 0xFF to the read FIFO.

Note: The TPM submodule uploads the TPM commands that do not fall into the FIFO registers (0xD4_XXXX) regardless of invalid_locality bit.

TPM_CFG . tpm_reg_chk_dis

If 1, the logic does not compare the upper 8 bit of the received address with the TpmAddr constant, D4h.

If this field is 0, the HW uploads the command, address, and write payload to the buffers in case of address that is not 0xD4_XXXX.

TPM_CFG . hw_reg_dis

If 0, TPM submodule directly returns the return-by-HW registers for the read requests.

If 1, TPM submodule uploads the TPM command regardless of the address, and the SW may return the value through the read FIFO.

TPM_CFG . tpm_mode

Configure the TPM mode. 1 for CRB, 0 for FIFO.

If the SW set this field to 1, the HW logic always pushes the command/addr and write data to buffers. The logic does not compare the incoming address to the list of managed-by-HW register addresses.

The invalid locality check still runs based on the invalid_locality configuration.

TPM_CFG . en

If 1, TPM submodule accepts the transactions over SPI

TPM_STATUS

TPM submodule state register.

The TPM_STATUS CSR provides the current TPM status, mostly the buffer and FIFO status.

  • Offset: 0x808
  • Reset default: 0x0
  • Reset mask: 0x7

Fields

BitsTypeResetName
31:3Reserved
2roxrdfifo_aborted
1rw0cxwrfifo_pending
0roxcmdaddr_notempty

TPM_STATUS . rdfifo_aborted

If 1, the last Read FIFO command was aborted.

This bit becomes 1 when a Read FIFO command became active, but the transaction did not complete. An aborted transaction occurs when the host de-asserts CSB without clocking all the requested data. This bit remains 1 until reset, or it will clear automatically after the next valid command is read from TPM_CMD_ADDR.

TPM_STATUS . wrfifo_pending

If 1, the Write FIFO is reserved for software processing.

This bit becomes 1 when a complete write command is received. While it remains 1, subsequent write commands will block at the wait state until it is cleared. Write 0 to release the Write FIFO back to the TPM module.

TPM_STATUS . cmdaddr_notempty

If 1, the TPM_CMD_ADDR has a valid data. This status is reported via the interrupt also.

TPM_ACCESS_0

TPM_ACCESS_x register.

  • Offset: 0x80c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:24rw0x0access_3TPM_ACCESS
23:16rw0x0access_2TPM_ACCESS
15:8rw0x0access_1TPM_ACCESS
7:0rw0x0access_0TPM_ACCESS

TPM_ACCESS_1

TPM_ACCESS_x register.

  • Offset: 0x810
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7:0rw0x0access_4For TPM1

TPM_STS

TPM_STS_x register.

The register is mirrored to all Localities. The value is returned to the host system only when the activeLocality in the TPM_ACCESS_x is matched to the current received Locality.

  • Offset: 0x814
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0stsTPM_STS_x

TPM_INTF_CAPABILITY

TPM_INTF_CAPABILITY

  • Offset: 0x818
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0intf_capabilityTPM_INTF_CAPABILITY

TPM_INT_ENABLE

TPM_INT_ENABLE

  • Offset: 0x81c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0int_enableTPM_INT_ENABLE

TPM_INT_VECTOR

TPM_INT_VECTOR

  • Offset: 0x820
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7:0rw0x0int_vectorTPM_INT_VECTOR

TPM_INT_STATUS

TPM_INT_STATUS

  • Offset: 0x824
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0int_statusTPM_INT_STATUS

TPM_DID_VID

TPM_DID/ TPM_VID register

  • Offset: 0x828
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16rw0x0didTPM_DID
15:0rw0x0vidTPM_VID

TPM_RID

TPM_RID

  • Offset: 0x82c
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7:0rw0x0ridTPM_RID

TPM_CMD_ADDR

TPM Command and Address buffer

The SW may get the received TPM command and address by readin gthis CSR.

  • Offset: 0x830
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:24roxcmdreceived command
23:0roxaddrreceived address

TPM_READ_FIFO

TPM Read command return data FIFO.

The write port of the read command FIFO.

  • Offset: 0x834
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0woxvaluewrite port of the read FIFO

egress_buffer

SPI internal egress buffer.

The lower 2 kB is for Read content emulating eFlash. The next 1 kB is for the Mailbox buffer. Then the next 256 B is for the SFDP buffer. Finally, the buffer spaces end with a 64 B TPM Read FIFO.

  • Word Aligned Offset Range: 0x1000to0x1d3c
  • Size (words): 848
  • Access: wo
  • Byte writes are not supported.

ingress_buffer

SPI internal ingress buffer.

The layout is as follows (starting from offset 0):

  • 256 B SFDP buffer

  • 32 B CmdFIFO

  • 32 B AddrFIFO

  • 256 B payload FIFO

  • 64 B TPM Write FIFO

  • Word Aligned Offset Range: 0x1e00to0x1fbc

  • Size (words): 112

  • Access: ro

  • Byte writes are not supported.