Registers

Summary

INTR_STATE

Interrupt State Register

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "upload_cmdfifo_not_empty", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "upload_payload_not_empty", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "upload_payload_overflow", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "readbuf_watermark", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "readbuf_flip", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "tpm_header_not_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "tpm_rdfifo_cmd_end", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "tpm_rdfifo_drop", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}}

INTR_ENABLE

Interrupt Enable Register

• Offset: 0x4
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "upload_cmdfifo_not_empty", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "upload_payload_not_empty", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "upload_payload_overflow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "readbuf_watermark", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "readbuf_flip", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tpm_header_not_empty", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tpm_rdfifo_cmd_end", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tpm_rdfifo_drop", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}}

INTR_TEST

Interrupt Test Register

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "upload_cmdfifo_not_empty", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "upload_payload_not_empty", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "upload_payload_overflow", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "readbuf_watermark", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "readbuf_flip", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tpm_header_not_empty", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tpm_rdfifo_cmd_end", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tpm_rdfifo_drop", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}}

ALERT_TEST

Alert Test Register

• Offset: 0xc
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

CONTROL

Control register.

• Offset: 0x10
• Reset default: 0x10
• Reset mask: 0x33

Fields

{"reg": [{"name": "FLASH_STATUS_FIFO_CLR", "bits": 1, "attr": ["rw1s"], "rotate": -90}, {"name": "FLASH_READ_BUFFER_CLR", "bits": 1, "attr": ["rw1s"], "rotate": -90}, {"bits": 2}, {"name": "MODE", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}

CONTROL . MODE

SPI Device flash operation mode.

Other values are reserved.

CONTROL . FLASH_READ_BUFFER_CLR

Set to clear the read buffer state.

When set to 1, resets the flash read buffer state that tracks the host read address. The reset should only be used when the upstream SPI host is known to be inactive. This function is intended to allow restoring initial values when the upstream SPI host is reset.

This CSR automatically resets to 0.

CONTROL . FLASH_STATUS_FIFO_CLR

Set to clear the flash status FIFO.

When set to 1, resets the flash status FIFO used for synchronizing changes from firmware. The reset should only be used when the upstream SPI host is known to be inactive. This function is intended to allow restoring initial values when the upstream SPI host is reset.

This CSR automatically resets to 0.

CFG

Configuration Register.

• Offset: 0x14
• Reset default: 0x0
• Reset mask: 0x100000c

Fields

{"reg": [{"bits": 2}, {"name": "tx_order", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_order", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 20}, {"name": "mailbox_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

STATUS

SPI Device status register.

• Offset: 0x18
• Reset default: 0x60
• Reset mask: 0x60

Fields

{"reg": [{"bits": 5}, {"name": "csb", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "tpm_csb", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}

INTERCEPT_EN

Intercept Passthrough datapath.

• Offset: 0x1c
• Reset default: 0x0
• Reset mask: 0xf

Fields

{"reg": [{"name": "status", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "jedec", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "sfdp", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "mbx", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ADDR_MODE

Flash Address Mode configuration.

This register shows the current address mode and pending changes to it. It is updated by the HW when the command opcode phase completes.

• Offset: 0x20
• Reset default: 0x0
• Reset mask: 0x80000001

Fields

{"reg": [{"name": "addr_4b_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}, {"name": "pending", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

ADDR_MODE . pending

SW-initiated change is pending.

This bit is set whenever the current value of ADDR_MODE.addr_4b_en is not yet in sync with the SPI domain. If an EN4B or EX4B command arrives next, the current value in ADDR_MODE.addr_4b_en will be ignored and the command will take priority.

ADDR_MODE . addr_4b_en

4B Address Mode enable.

This field determines whether 4B address mode is currently enabled.

If set, the size of addresses for SPI commands with CMD_INFO.addr_mode == AddrCfg is 4B, otherwise it is 3B. This field is modified by HW on receiving the EN4B and EX4B commands - see CMD_INFO_EN4B and CMD_INFO_EX4B.

Read SFDP commands (CMD_INFO slot 4) are unaffected by the configuration of ADDR_MODE.addr_4b_en, and a 3-byte address will always be expected following the command opcode.

If a SW-initiated change is still pending the sync to the SPI domain, this bit will reflect the value to be sent. Otherwise, this field will reflect the current value observed in the SPI domain. See ADDR_MODE.pending.

It is expected that software only sets this field during early configuration. Modifying this field mid-operation is almost always a protocol violation.

LAST_READ_ADDR

Last Read Address.

This register shows the last address accessed by the host system. It is updated by the HW when CSb is de-asserted.

• Offset: 0x24
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "addr", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

FLASH_STATUS

SPI Flash Status register.

This register emulates the SPI Flash Status 1-3 registers. Bits [7:0], [15:8], and [23:16] contain the values for the Status 1, 2, and 3 registers respectively. It is the responsibility of SW to keep the value of this register up-to-date.

When software writes a value here, it is delivered to a staging async FIFO, where it waits for the SPI side to commit it. Any updates require at least 8 SPI clocks before they commit on the SPI side, which is the source-of-truth. After committing on the SPI side, the CSRs will eventually update with the latest value.

• Offset: 0x28
• Reset default: 0x0
• Reset mask: 0xffffff

Fields

{"reg": [{"name": "busy", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "wel", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "status", "bits": 22, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

FLASH_STATUS . status

Rest of the status register. HW reads will return the value stored. This field is managed by SW and the bits have no special significance to the HW - SW should use the bits according to the specific flash chip emulated. The following is a normative list of common uses for each bit:

FLASH_STATUS . wel

The Write Enable Latch signal.

This bit is set or unset by HW when a WREN or WRDI command is received - see CMD_INFO_WREN and CMD_INFO_WRDI. SW may only clear this bit. SW should read back the register to confirm the bit is cleared.

FLASH_STATUS . busy

The BUSY signal.

This bit is set by HW when a matched command with CMD_INFO.upload and CMD_INFO.busy set is received. SW may only clear this bit. SW should read back the register to confirm the bit is cleared.

Note that the observable state of the BUSY bit updates every 8 SPI clocks. This enables continuous polling of the BUSY bit. However, the passthrough gate (for passthrough mode) only updates when CSb is de-asserted, not on SPI clocks.

JEDEC_CC

JEDEC Continuation Code configuration register.

Read JEDEC ID must return the continuation code if the manufacturer ID is not shown in the first page of JEDEC table. This register controls the Continuation Code.

• Offset: 0x2c
• Reset default: 0x7f
• Reset mask: 0xffff

Fields

{"reg": [{"name": "cc", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "num_cc", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

JEDEC_ID

JEDEC ID register.

• Offset: 0x30
• Reset default: 0x0
• Reset mask: 0xffffff

Fields

{"reg": [{"name": "id", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mf", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

READ_THRESHOLD

Read Buffer threshold register.

• Offset: 0x34
• Reset default: 0x0
• Reset mask: 0x3ff

Fields

{"reg": [{"name": "threshold", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 22}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MAILBOX_ADDR

Mailbox Base address register.

The mailbox size is fixed. In this version of IP, the size is 1kB. The least-significant 10 bits of the Mailbox address are tied to 0.

• Offset: 0x38
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "addr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

UPLOAD_STATUS

Upload Module status register.

• Offset: 0x3c
• Reset default: 0x0
• Reset mask: 0x9f9f

Fields

{"reg": [{"name": "cmdfifo_depth", "bits": 5, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "cmdfifo_notempty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "addrfifo_depth", "bits": 5, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "addrfifo_notempty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}

UPLOAD_STATUS2

Upload Module second status register.

This register contains information related to the uploaded command payload. UPLOAD_STATUS2.payload_depth indicates the length of the command payload, in bytes.

UPLOAD_STATUS2.payload_start_idx indicates the start position of this command payload within the Payload Buffer, in bytes. This field is usually 0, unless more than 256 bytes of payload have been issued.

For example, if 258 bytes of payload are issued, UPLOAD_STATUS2.payload_depth will be 256 (as the Payload Buffer only has capacity for 256 bytes), but UPLOAD_STATUS2.payload_start_idx will be 2. SW should read bytes 2-255 followed by bytes 0-1 to read the intact portion of the payload in the correct order.

• Offset: 0x40
• Reset default: 0x0
• Reset mask: 0xff01ff

Fields

{"reg": [{"name": "payload_depth", "bits": 9, "attr": ["ro"], "rotate": 0}, {"bits": 7}, {"name": "payload_start_idx", "bits": 8, "attr": ["ro"], "rotate": -90}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}

UPLOAD_CMDFIFO

Command FIFO Read Port.

• Offset: 0x44
• Reset default: 0x0
• Reset mask: 0xe0ff

Fields

{"reg": [{"name": "data", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 5}, {"name": "busy", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "wel", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "addr4b_mode", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

UPLOAD_ADDRFIFO

Address FIFO Read Port.

• Offset: 0x48
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "data", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CMD_FILTER_0

Passthrough mode: Command Filter.

If the bit corresponding to a received command’s opcode is set, the command is filtered (CSb is de-asserted) and does not reach the downstream flash device.

• Offset: 0x4c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "filter_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_12", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_13", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_14", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_15", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_16", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_17", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_18", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_19", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_20", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_21", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_22", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_23", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_24", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_25", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_26", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_27", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_28", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_29", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_30", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_31", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

CMD_FILTER_1

Passthrough mode: Command Filter.

If the bit corresponding to a received command’s opcode is set, the command is filtered (CSb is de-asserted) and does not reach the downstream flash device.

• Offset: 0x50
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "filter_32", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_33", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_34", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_35", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_36", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_37", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_38", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_39", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_40", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_41", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_42", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_43", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_44", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_45", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_46", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_47", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_48", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_49", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_50", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_51", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_52", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_53", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_54", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_55", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_56", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_57", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_58", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_59", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_60", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_61", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_62", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_63", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

CMD_FILTER_2

Passthrough mode: Command Filter.

If the bit corresponding to a received command’s opcode is set, the command is filtered (CSb is de-asserted) and does not reach the downstream flash device.

• Offset: 0x54
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "filter_64", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_65", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_66", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_67", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_68", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_69", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_70", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_71", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_72", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_73", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_74", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_75", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_76", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_77", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_78", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_79", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_80", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_81", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_82", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_83", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_84", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_85", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_86", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_87", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_88", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_89", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_90", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_91", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_92", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_93", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_94", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_95", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

CMD_FILTER_3

Passthrough mode: Command Filter.

If the bit corresponding to a received command’s opcode is set, the command is filtered (CSb is de-asserted) and does not reach the downstream flash device.

• Offset: 0x58
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "filter_96", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_97", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_98", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_99", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_100", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_101", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_102", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_103", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_104", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_105", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_106", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_107", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_108", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_109", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_110", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_111", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_112", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_113", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_114", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_115", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_116", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_117", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_118", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_119", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_120", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_121", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_122", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_123", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_124", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_125", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_126", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_127", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

CMD_FILTER_4

Passthrough mode: Command Filter.

If the bit corresponding to a received command’s opcode is set, the command is filtered (CSb is de-asserted) and does not reach the downstream flash device.

• Offset: 0x5c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "filter_128", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_129", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_130", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_131", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_132", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_133", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_134", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_135", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_136", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_137", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_138", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_139", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_140", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_141", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_142", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_143", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_144", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_145", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_146", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_147", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_148", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_149", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_150", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_151", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_152", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_153", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_154", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_155", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_156", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_157", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_158", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_159", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

CMD_FILTER_5

Passthrough mode: Command Filter.

If the bit corresponding to a received command’s opcode is set, the command is filtered (CSb is de-asserted) and does not reach the downstream flash device.

• Offset: 0x60
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "filter_160", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_161", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_162", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_163", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_164", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_165", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_166", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_167", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_168", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_169", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_170", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_171", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_172", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_173", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_174", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_175", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_176", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_177", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_178", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_179", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_180", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_181", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_182", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_183", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_184", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_185", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_186", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_187", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_188", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_189", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_190", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_191", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

CMD_FILTER_6

Passthrough mode: Command Filter.

If the bit corresponding to a received command’s opcode is set, the command is filtered (CSb is de-asserted) and does not reach the downstream flash device.

• Offset: 0x64
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "filter_192", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_193", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_194", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_195", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_196", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_197", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_198", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_199", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_200", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_201", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_202", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_203", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_204", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_205", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_206", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_207", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_208", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_209", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_210", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_211", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_212", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_213", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_214", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_215", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_216", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_217", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_218", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_219", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_220", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_221", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_222", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_223", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

CMD_FILTER_7

Passthrough mode: Command Filter.

If the bit corresponding to a received command’s opcode is set, the command is filtered (CSb is de-asserted) and does not reach the downstream flash device.

• Offset: 0x68
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "filter_224", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_225", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_226", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_227", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_228", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_229", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_230", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_231", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_232", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_233", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_234", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_235", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_236", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_237", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_238", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_239", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_240", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_241", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_242", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_243", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_244", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_245", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_246", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_247", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_248", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_249", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_250", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_251", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_252", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_253", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_254", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "filter_255", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

ADDR_SWAP_MASK

Passthrough mode: Address Swap Mask.

This register is used in the SPI passthrough mode. If any of bits in this register is set, the corresponding address bit in the SPI Read commands is replaced with the data from ADDR_SWAP_DATA.

If the command’s address size is 3B, the upper byte (bits [31:24]) are not used.

• Offset: 0x6c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "mask", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ADDR_SWAP_DATA

Passthrough mode: Address Swap Data.

• Offset: 0x70
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "data", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PAYLOAD_SWAP_MASK

Passthrough mode: Payload Swap Mask.

Passthrough mode payload swapping can set or unset any bits in the first 4 bytes of the payload written to the downstream flash. For any bit set in PAYLOAD_SWAP_MASK, the passthrough logic instead uses the value of the corresponding bit in PAYLOAD_SWAP_DATA for that payload bit.

For example, if PAYLOAD_SWAP_MASK is set to 0x0000000f and PAYLOAD_SWAP_DATA is set to 0x00000005, bits 0 and 2 of the first payload byte are set to 1, bits 1 and 3 of the first payload byte are set to 0, and the rest of the payload is unchanged.

Payload swapping is applied least-significant bit first - bits [7:0] are applied to the first received byte, followed by bits [15:8], and so on.

• Offset: 0x74
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "mask", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PAYLOAD_SWAP_DATA

Passthrough mode: Payload Swap Data.

Passthrough mode payload swapping can set or unset any bits in the first 4 bytes of the payload written to the downstream flash. For any bit set in PAYLOAD_SWAP_MASK, the passthrough logic instead uses the value of the corresponding bit in PAYLOAD_SWAP_DATA for that payload bit.

For example, if PAYLOAD_SWAP_MASK is set to 0x0000000f and PAYLOAD_SWAP_DATA is set to 0x00000005, bits 0 and 2 of the first payload byte are set to 1, bits 1 and 3 of the first payload byte are set to 0, and the rest of the payload is unchanged.

Payload swapping is applied least-significant bit first - bits [7:0] are applied to the first received byte, followed by bits [15:8], and so on.

• Offset: 0x78
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "data", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CMD_INFO

Command Information register.

For CMD_INFO slots assigned to HW functionality, HW ignores the setting of some configurable fields and the behaviour is hard-coded.

Read SFDP commands (CMD_INFO slot 4) are unaffected by the configuration of ADDR_MODE.addr_4b_en, and a 3-byte address will always be expected following the command opcode.

• Reset default: 0x7000
• Reset mask: 0x83ffffff

Instances

Fields

{"reg": [{"name": "opcode", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "addr_mode", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "addr_swap_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "mbyte_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "dummy_size", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "dummy_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "payload_en", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "payload_dir", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "payload_swap_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "read_pipeline_mode", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "upload", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "busy", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 5}, {"name": "valid", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

CMD_INFO . valid

If set, the command is active and can be matched on command receive. Otherwise, this command information entry is ignored.

CMD_INFO . busy

If set, sets the FLASH_STATUS.busy bit when the command is received. This bit is only effective if the CMD_INFO.upload bit is set.

CMD_INFO . upload

If set, the command parser activates the upload submodule when this command is received and the command is uploaded.

The command’s opcode (CMD_INFO.opcode), as well as the state of the FLASH_STATUS.busy, FLASH_STATUS.wel, and ADDR_MODE.addr_4b_en bits at the time the command is received, are stored in the Command Upload FIFO, readable from UPLOAD_CMDFIFO.

if CMD_INFO.addr_mode is not AddrDisabled, the command’s address field is stored in the Address Upload FIFO, readable from UPLOAD_ADDRFIFO.

The behaviour of CMD_INFO.upload with CMD_INFO.addr_mode == AddrDisabled is not defined.

The command’s payload is written to the Payload Buffer. See UPLOAD_STATUS and UPLOAD_STATUS2.

The behaviour of CMD_INFO.upload with CMD_INFO.payload_dir is not defined.

In Passthrough mode, uploaded commands are still delivered to the downstream flash device unless the bit corresponding to the opcode is set in CMD_FILTER.

The behaviour of CMD_INFO.upload with CMD_INFO.addr_swap_en and CMD_INFO.payload_swap_en is not defined.

In Passthrough mode, address and payload swapping (as controlled by CMD_INFO.addr_swap_en and CMD_INFO.payload_swap_en) are applied only to the data passed-through to the downstream flash, and not the uploaded address and payload. SW may manually apply address and payload swapping to see the values sent downstream using the same swap mask/data registers.

CMD_INFO . read_pipeline_mode

Add 2-stage pipeline to read payload.

If read_pipeline_mode is not set to zero_stages, the read logic adds a 2-stage pipeline to the read data for this command. This read pipeline enables higher throughput for certain read commands in passthrough mode.

payload_dir must be set to PayloadOut: payload_pipeline_en only works with read data. It may be used with any IO mode, but general host compatibility is likely limited to Quad Read. If this pipeline is used for passthrough, the internal SFDP should report 2 additional dummy cycles compared to the downstream flash. SFDP read commands should be processed internally, and dummy_size should still reflect the downstream device’s dummy cycle count.

Other values are reserved.

CMD_INFO . payload_swap_en

Passthrough mode: Swap the first 4 bytes of the write payload.

If set, passthrough logic swaps the first 4 bytes of the command’s written payload, according to the values of PAYLOAD_SWAP_MASK and PAYLOAD_SWAP_DATA.

Payload swapping only works with write payloads and in Single IO mode - CMD_INFO.payload_en must be 0b0001 and CMD_INFO.payload_dir must be PayloadIn.

CMD_INFO . payload_dir

The direction of the command’s payload phase.

If set, the payload is from the downstream flash or SPI Device IP to the host, otherwise it is from the host to the downstream flash or SPI Device IP.

This field has no effect if the command has no payload phase - see also CMD_INFO.payload_en.

CMD_INFO . payload_en

Payload Enable per SPI lane.

Represents which SPI lines this command’s payload is transmitted over, if any. Each bit corresponds to one of the SPI IO lines.

For example, if the command is a Single IO command with a payload that is written to the SPI Device IP or downstream flash, this should be set to 0b0001 for the MOSI line (IO[0]). If the payload is read from the SPI Device IP or downstream flash, this should be set to 0b0010 for the MISO line (IO[1]). CMD_INFO.payload_dir should also be configured with the appropriate payload direction.

CMD_INFO . dummy_en

If set, the command has at least one dummy cycle between the opcode/address phase and the payload phase.

CMD_INFO . dummy_size

The number of dummy cycles between this command’s opcode/address phase and the payload phase, minus one.

This field has no effect if CMD_INFO.dummy_en is unset.

CMD_INFO . mbyte_en

If set, the command has an MByte field following the address field. This should be set for Dual IO and Quad IO commands.

This field is currently unimplemented.

CMD_INFO . addr_swap_en

Passthrough mode: Swap the command’s address bytes.

If set, passthrough logic swaps the bytes of the command’s address field, according to the values ADDR_SWAP_MASK and ADDR_SWAP_DATA.

This bit is only effective if CMD_INFO.addr_mode is not AddrDisabled.

CMD_INFO . addr_mode

The size of the command’s address field.

CMD_INFO . opcode

Command opcode

CMD_INFO_EN4B

EN4B command information register.

This command is handled by HW in Flash and Passthrough modes.

This command sets the ADDR_MODE.addr_4b_en bit.

• Offset: 0xdc
• Reset default: 0x0
• Reset mask: 0x800000ff

Fields

{"reg": [{"name": "opcode", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 23}, {"name": "valid", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CMD_INFO_EX4B

EX4B command information register.

This command is handled by HW in Flash and Passthrough modes.

This command clears the ADDR_MODE.addr_4b_en bit.

• Offset: 0xe0
• Reset default: 0x0
• Reset mask: 0x800000ff

Fields

{"reg": [{"name": "opcode", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 23}, {"name": "valid", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CMD_INFO_WREN

Write Enable (WREN) command information register.

This command is handled by HW in Flash and Passthrough modes.

This command sets the FLASH_STATUS.wel bit.

• Offset: 0xe4
• Reset default: 0x0
• Reset mask: 0x800000ff

Fields

{"reg": [{"name": "opcode", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 23}, {"name": "valid", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CMD_INFO_WRDI

Write Disable (WRDI) command information register.

This command is handled by HW in Flash and Passthrough modes.

This command clears the FLASH_STATUS.wel bit.

• Offset: 0xe8
• Reset default: 0x0
• Reset mask: 0x800000ff

Fields

{"reg": [{"name": "opcode", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 23}, {"name": "valid", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TPM_CAP

TPM HWIP Capability register.

This register shows the features the current TPM HWIP supports.

• Offset: 0x800
• Reset default: 0x660100
• Reset mask: 0x7701ff

Fields

{"reg": [{"name": "rev", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "locality", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 7}, {"name": "max_wr_size", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "max_rd_size", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 9}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

TPM_CAP . max_rd_size

The maximum read size in bytes the TPM submodule supports. The maximum read size is 2 to the power of the value in this field (between 4 and 64 byes).

All other values are reserved.

It is recommended that SW does not advertise the TPM as supporting reads larger than max_rd_size to the Southbridge.

TPM_CAP . max_wr_size

The maximum write size in bytes the TPM submodule supports. The maximum write size is 2 to the power of the value in this field (between 4 and 64 byes).

All other values are reserved.

It is recommended that SW does not advertise the TPM as supporting writes larger than max_wr_size to the Southbridge.

TPM_CAP . locality

If set, the TPM submodule supports 5 Localities, otherwise only one Locality is supported.

TPM_CAP . rev

Revision of the TPM submodule.

TPM_CFG

TPM Configuration register.

• Offset: 0x804
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tpm_mode", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "hw_reg_dis", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tpm_reg_chk_dis", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "invalid_locality", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}

TPM_CFG . invalid_locality

If set, TPM submodule returns the invalid data (0xFF) for the out of the max Locality request. If the request is a write request, The HW will still upload the command and address. In that case, SW still needs to precess the incoming invalid command.

If unset, TPM submodule uploads the TPM command and address. The SW may write 0xFF to the read FIFO.

Note: The TPM submodule uploads the TPM commands that do not fall into the FIFO registers (0xD4_XXXX) regardless of invalid_locality bit.

TPM_CFG . tpm_reg_chk_dis

If set, the logic does not compare the upper 8 bits of the received address with the TpmAddr constant, 0xD4.

If unset, the HW uploads the command, address, and write payload to the buffers in case of address that is not 0xD4_XXXX.

TPM_CFG . hw_reg_dis

If unset, TPM submodule directly returns the return-by-HW registers for read requests.

If set, TPM submodule uploads the TPM command regardless of the address, and the SW may return the value through the read FIFO.

TPM_CFG . tpm_mode

Configure the TPM mode. If set, the TPM is in CRB mode, otherwise it is FIFO mode.

If this field is set by SW, the HW logic always pushes the command, address, and write data to buffers. The logic does not compare the incoming address to the list of managed-by-HW register addresses.

The invalid locality check still runs based on the invalid_locality configuration.

TPM_CFG . en

If set, the TPM submodule accepts the transactions over SPI.

TPM_STATUS

TPM submodule state register.

The TPM_STATUS CSR provides the status of the read and write FIFOs, as well as the Command and Address buffer.

• Offset: 0x808
• Reset default: 0x0
• Reset mask: 0x7

Fields

{"reg": [{"name": "cmdaddr_notempty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "wrfifo_pending", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "rdfifo_aborted", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}

TPM_STATUS . rdfifo_aborted

If set, the last Read FIFO command was aborted.

This bit becomes set when a Read FIFO command became active, but the transaction did not complete. An aborted transaction occurs when the host de-asserts CSb without clocking all the requested data. This bit remains set until reset, or it will clear automatically after the next valid command is read from TPM_CMD_ADDR.

TPM_STATUS . wrfifo_pending

If set, the Write FIFO is reserved for software processing.

This bit becomes set when a complete write command is received. While it remains set, subsequent write commands will block at the wait state until it is cleared. Write 0 to release the Write FIFO back to the TPM module.

TPM_STATUS . cmdaddr_notempty

If set, TPM_CMD_ADDR contains valid data. This status is reported via the interrupt also.

TPM_ACCESS_0

TPM_ACCESS_x register.

• Offset: 0x80c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "access_0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "access_1", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "access_2", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "access_3", "bits": 8, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TPM_ACCESS_1

TPM_ACCESS_x register.

• Offset: 0x810
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "access_4", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TPM_STS

TPM_STS_x register.

The register is mirrored to all Localities. The value is returned to the host system only when the activeLocality in the TPM_ACCESS_x is matched to the current received Locality.

• Offset: 0x814
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "sts", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TPM_INTF_CAPABILITY

TPM_INTF_CAPABILITY register.

• Offset: 0x818
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "intf_capability", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TPM_INT_ENABLE

TPM_INT_ENABLE register.

• Offset: 0x81c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "int_enable", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TPM_INT_VECTOR

TPM_INT_VECTOR register.

• Offset: 0x820
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "int_vector", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TPM_INT_STATUS

TPM_INT_STATUS register.

• Offset: 0x824
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "int_status", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TPM_DID_VID

TPM_DID/ TPM_VID register.

• Offset: 0x828
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "vid", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "did", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TPM_RID

TPM_RID register.

• Offset: 0x82c
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "rid", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TPM_CMD_ADDR

TPM Command and Address buffer.

The SW may get the received TPM command and address by reading this CSR.

• Offset: 0x830
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "addr", "bits": 24, "attr": ["ro"], "rotate": 0}, {"name": "cmd", "bits": 8, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TPM_READ_FIFO

TPM Read command return data FIFO.

The write port of the read command FIFO.

• Offset: 0x834
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "value", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

egress_buffer

SPI internal egress buffer.

• Word Aligned Offset Range: 0x1000to0x1d3c
• Size (words): 848
• Access: wo
• Byte writes are not supported.

ingress_buffer

SPI internal ingress buffer.

• Word Aligned Offset Range: 0x1e00to0x1fbc
• Size (words): 112
• Access: ro
• Byte writes are not supported.