OpenTitan
Getting Started
1.
Getting Started
2.
Workflows
❱
2.1.
Design Verification
2.2.
Formal Verification
2.3.
Building (and Testing) Software
2.4.
Building Documentation
2.5.
Using OpenOCD
3.
Tools Setup
❱
3.1.
FPGA Setup
3.2.
Verilator Setup
3.3.
Installing Vivado
4.
Unofficial Guides
❱
4.1.
RedHat/Fedora
Hardware
5.
Introduction
6.
Top Earlgrey
❱
6.1.
Datasheet
6.2.
Design
6.3.
Design Verification
❱
6.3.1.
Chip Testplan
6.4.
Analog Sensor Top
❱
6.4.1.
Interfaces
6.5.
Alert Handler
❱
6.5.1.
Theory of Operation
6.5.2.
Design Verification
❱
6.5.2.1.
Testplan
6.5.3.
Programmer's Guide
6.5.4.
Interface and Registers
6.5.5.
Device Interface Functions
6.5.6.
Checklist
6.6.
Interrupt Controller
❱
6.6.1.
Theory of Operation
6.6.2.
Design Verification
❱
6.6.2.1.
Testplan
6.6.3.
Programmer's Guide
6.6.4.
Interface and Registers
6.6.5.
Device Interface Functions
6.6.6.
Checklist
6.7.
Sensor Control
❱
6.7.1.
Theory of Operation
6.7.2.
Programmer's Guide
6.7.3.
Hardware Interfaces
6.7.4.
Registers
6.7.5.
Device Interface Functions
6.7.6.
Checklist
6.8.
TL-UL Checklist
6.9.
Pinmux Targets
❱
6.9.1.
ASIC Target Pinout and Pinmux Connectivity
6.9.2.
CW310 Target Pinout and Pinmux Connectivity
6.9.3.
CW340 Target Pinout and Pinmux Connectivity
7.
Top Darjeeling
❱
7.1.
Datasheet
8.
Cores
❱
8.1.
Ibex RISC-V Core Wrapper
❱
8.1.1.
Theory of Operation
8.1.2.
Design Verification
8.1.3.
Programmer's Guide
8.1.4.
Hardware Interfaces
8.1.5.
Registers
8.1.6.
Checklist
8.2.
OTBN
❱
8.2.1.
Theory of Operation
8.2.2.
Introduction to OTBN
8.2.3.
Developing OTBN
8.2.4.
ISA Guide
8.2.5.
Design Verification
❱
8.2.5.1.
Random Instruction Generator
❱
8.2.5.1.1.
Internals
8.2.5.1.2.
Configuration
8.2.5.2.
memutil wrapper
8.2.5.3.
OTBN Simulation Software
8.2.5.4.
Tracer
8.2.5.5.
Formal Masking Verification Using Alma
8.2.6.
Functional Coverage
8.2.7.
Programmer's Guide
8.2.8.
Hardware Interfaces
8.2.9.
Registers
8.2.10.
Checklist
9.
Hardware IP Blocks
❱
9.1.
Analog to Digital Converter Control
❱
9.1.1.
Theory of Operation
9.1.2.
Design Verification
❱
9.1.2.1.
Testplan
9.1.3.
Programmer's Guide
9.1.4.
Hardware Interfaces
9.1.5.
Registers
9.1.6.
Checklist
9.2.
AES
❱
9.2.1.
Theory of Operation
9.2.2.
Design Verification
❱
9.2.2.1.
Testplan
9.2.3.
Programmer's Guide
9.2.4.
Hardware Interfaces
9.2.5.
Registers
9.2.6.
Device Interface Functions
9.2.7.
Checklist
9.3.
AON Timer
❱
9.3.1.
Theory of Operation
9.3.2.
Design Verification
❱
9.3.2.1.
Testplan
9.3.3.
Programmer's Guide
9.3.4.
Hardware Interfaces
9.3.5.
Registers
9.3.6.
Device Interface Functions
9.3.7.
Checklist
9.4.
Ascon
❱
9.4.1.
Background
9.4.2.
Theory of Operation
9.4.3.
Programmer's Guide
9.4.4.
Hardware Interfaces
9.4.5.
Registers
9.4.6.
Checklist
9.5.
Clock Manager
❱
9.5.1.
Theory of Operation
9.5.2.
Design Verification
❱
9.5.2.1.
Testplan
9.5.3.
Programmer's Guide
9.5.4.
Hardware Interfaces
9.5.5.
Registers
9.5.6.
Device Interface Functions
9.5.7.
Checklist
9.6.
CSRNG
❱
9.6.1.
Theory of Operation
9.6.2.
Design Verification
❱
9.6.2.1.
Testplan
9.6.3.
Programmer's Guide
9.6.4.
Hardware Interfaces
9.6.5.
Registers
9.6.6.
Device Interface Functions
9.6.7.
Checklist
9.7.
EDN
❱
9.7.1.
Theory of Operation
9.7.2.
Design Verification
❱
9.7.2.1.
Testplan
9.7.3.
Programmer's Guide
9.7.4.
Hardware Interfaces
9.7.5.
Registers
9.7.6.
Device Interface Functions
9.7.7.
Checklist
9.8.
Entropy Source
❱
9.8.1.
Theory of Operation
9.8.2.
Design Verification
❱
9.8.2.1.
Testplan
9.8.3.
Programmer's Guide
9.8.4.
Hardware Interfaces
9.8.5.
Registers
9.8.6.
Device Interface Functions
9.8.7.
Checklist
9.9.
Flash Controller
❱
9.9.1.
Theory of Operation
9.9.2.
Design Verification
❱
9.9.2.1.
Testplan
9.9.3.
Programmer's Guide
9.9.4.
Hardware Interfaces
9.9.5.
Registers
9.9.6.
Device Interface Functions
9.9.7.
Checklist
9.10.
GPIO
❱
9.10.1.
Theory of Operation
9.10.2.
Design Verification
❱
9.10.2.1.
Testplan
9.10.3.
Programmer's Guide
9.10.4.
Hardware Interfaces
9.10.5.
Registers
9.10.6.
Device Interface Functions
9.10.7.
Checklist
9.11.
HMAC
❱
9.11.1.
Theory of Operation
9.11.2.
Design Verification
❱
9.11.2.1.
Testplan
9.11.3.
Programmer's Guide
9.11.4.
Hardware Interfaces
9.11.5.
Registers
9.11.6.
Device Interface Functions
9.11.7.
Checklist
9.12.
I2C
❱
9.12.1.
Theory of Operation
9.12.2.
Design Verification
❱
9.12.2.1.
Testplan
9.12.3.
Programmer's Guide
9.12.4.
Hardware Interfaces
9.12.5.
Registers
9.12.6.
Device Interface Functions
9.12.7.
Checklist
9.13.
Key Manager
❱
9.13.1.
Theory of Operation
9.13.2.
Design Verification
❱
9.13.2.1.
Testplan
9.13.3.
Programmer's Guide
9.13.4.
Hardware Interfaces
9.13.5.
Registers
9.13.6.
Device Interface Functions
9.13.7.
Checklist
9.14.
Key Manager DPE
❱
9.14.1.
Theory of Operation
9.14.2.
Programmer's Guide
9.14.3.
Interface and Registers
9.14.4.
Checklist
9.15.
KMAC
❱
9.15.1.
Theory of Operation
9.15.2.
Design Verification
❱
9.15.2.1.
Testplan
9.15.3.
Programmer's Guide
9.15.4.
Hardware Interfaces
9.15.5.
Registers
9.15.6.
Device Interface Functions
9.15.7.
Checklist
9.16.
Life Cycle Controller
❱
9.16.1.
Theory of Operation
9.16.2.
Design Verification
❱
9.16.2.1.
Testplan
9.16.3.
Programmer's Guide
9.16.4.
Hardware Interfaces
9.16.5.
Registers
9.16.6.
Device Interface Functions
9.16.7.
Checklist
9.17.
OTP Controller
❱
9.17.1.
Theory of Operation
9.17.2.
Design Verification
❱
9.17.2.1.
Testplan
9.17.3.
Programmer's Guide
9.17.4.
Hardware Interfaces
9.17.5.
Registers
9.17.6.
Device Interface Functions
9.17.7.
Checklist
9.18.
Pattern Generator
❱
9.18.1.
Theory of Operation
9.18.2.
Design Verification
❱
9.18.2.1.
Testplan
9.18.3.
Programmer's Guide
9.18.4.
Hardware Interfaces
9.18.5.
Registers
9.18.6.
Device Interface Functions
9.18.7.
Checklist
9.19.
Pinmux
❱
9.19.1.
Theory of Operation
9.19.2.
Design Verification
❱
9.19.2.1.
Testplan
9.19.3.
Programmer's Guide
9.19.4.
Hardware Interfaces
9.19.5.
Registers
9.19.6.
Device Interface Functions
9.19.7.
Checklist
9.20.
Pulse Width Modulator
❱
9.20.1.
Theory of Operation
9.20.2.
Design Verification
❱
9.20.2.1.
Testplan
9.20.3.
Programmer's Guide
9.20.4.
Hardware Interfaces
9.20.5.
Registers
9.20.6.
Device Interface Functions
9.20.7.
Checklist
9.21.
Power Management
❱
9.21.1.
Theory of Operation
9.21.2.
Design Verification
❱
9.21.2.1.
Testplan
9.21.3.
Programmer's Guide
9.21.4.
Hardware Interfaces
9.21.5.
Registers
9.21.6.
Device Interface Functions
9.21.7.
Checklist
9.22.
ROM Control
❱
9.22.1.
Theory of Operation
9.22.2.
Design Verification
❱
9.22.2.1.
Testplan
9.22.3.
Programmer's Guide
9.22.4.
Hardware Interfaces
9.22.5.
Registers
9.22.6.
Device Interface Functions
9.22.7.
Checklist
9.23.
Reset Manager
❱
9.23.1.
Theory of Operation
9.23.2.
Design Verification
❱
9.23.2.1.
Testplan
9.23.3.
Programmer's Guide
9.23.4.
Hardware Interfaces
9.23.5.
Registers
9.23.6.
Device Interface Functions
9.23.7.
Checklist
9.24.
RISC-V Debug Manager
❱
9.24.1.
Theory of Operation
9.24.2.
Design Verification
❱
9.24.2.1.
Testplan
9.24.3.
Programmer's Guide
9.24.4.
Hardware Interfaces
9.24.5.
Registers
9.24.6.
Checklist
9.25.
SPI Device
❱
9.25.1.
Theory of Operation
9.25.2.
Design Verification
❱
9.25.2.1.
Testplan
9.25.3.
Programmer's Guide
9.25.4.
Hardware Interfaces
9.25.5.
Registers
9.25.6.
Device Interface Functions
9.25.7.
Checklist
9.26.
SPI Host
❱
9.26.1.
Theory of Operation
9.26.2.
Design Verification
❱
9.26.2.1.
Testplan
9.26.3.
Programmer's Guide
9.26.4.
Hardware Interfaces
9.26.5.
Registers
9.26.6.
Device Interface Functions
9.26.7.
Checklist
9.27.
SRAM Controller
❱
9.27.1.
Theory of Operation
9.27.2.
Design Verification
❱
9.27.2.1.
Testplan
9.27.3.
Programmer's Guide
9.27.4.
Hardware Interfaces
9.27.5.
Registers
9.27.6.
Device Interface Functions
9.27.7.
Checklist
9.28.
System Reset Controller
❱
9.28.1.
Theory of Operation
9.28.2.
Design Verification
❱
9.28.2.1.
Testplan
9.28.3.
Hardware Interfaces
9.28.4.
Registers
9.28.5.
Device Interface Functions
9.28.6.
Checklist
9.29.
Timer
❱
9.29.1.
Theory of Operation
9.29.2.
Design Verification
❱
9.29.2.1.
Testplan
9.29.3.
Programmer's Guide
9.29.4.
Hardware Interfaces
9.29.5.
Registers
9.29.6.
Device Interface Functions
9.29.7.
Checklist
9.30.
TL-UL Bus
❱
9.30.1.
Design Verification
❱
9.30.1.1.
Testplan
9.30.1.2.
Protocol Checker
9.31.
UART
❱
9.31.1.
Theory of Operation
9.31.2.
Design Verification
❱
9.31.2.1.
Testplan
9.31.3.
Programmer's Guide
9.31.4.
Hardware Interfaces
9.31.5.
Registers
9.31.6.
Device Interface Functions
9.31.7.
Checklist
9.32.
USB 2.0
❱
9.32.1.
Theory of Operation
9.32.2.
Design Verification
❱
9.32.2.1.
Testplan
9.32.3.
Programmer's Guide
9.32.4.
Suspending and Resuming
9.32.5.
Hardware Interfaces
9.32.6.
Registers
9.32.7.
Device Interface Functions
9.32.8.
Checklist
9.33.
lowRISC Hardware Primitives
❱
9.33.1.
Flash Wrapper
9.33.2.
Keccak Permutation
9.33.3.
Linear Feedback Shift Register
9.33.4.
Packer
9.33.5.
Packer FIFO
9.33.6.
Present Scrambler
9.33.7.
Prince Scrambler
9.33.8.
SRAM Scrambler
9.33.9.
Pseudo Random Number Generator
10.
Common SystemVerilog and UVM Components
❱
10.1.
ALERT_ESC Agent
10.2.
Bus Params Package
10.3.
Comportable IP Testbench Architecture
10.4.
Common Interfaces
10.5.
CSR Utils
10.6.
CSRNG Agent
10.7.
DV Library Classes
10.8.
DV Utils
10.9.
FLASH_PHY_PRIM Agent
10.10.
I2C Agent
10.11.
JTAG Agent
10.12.
JTAG DMI Agent
10.13.
JTAG RISCV Agent
10.14.
KEY_SIDELOAD Agent
10.15.
KMAC_APP Agent
10.16.
Memory Backdoor Scoreboard
10.17.
Memory Backdoor Utility
10.18.
Memory Model
10.19.
PATTGEN Agent
10.20.
PUSH_PULL Agent
10.21.
PWM Monitor
10.22.
RNG Agent
10.23.
Scoreboard
10.24.
Simulation SRAM
10.25.
SPI Agent
10.26.
String Utils
10.27.
Test Vectors
10.28.
Tile Link Agent
10.29.
UART Agent
10.30.
USB20 Agent
Software
11.
Introduction
12.
Build Software
13.
Device Software
❱
13.1.
Build & Test Rules
❱
13.1.1.
FPGA Bitstreams
13.1.2.
OTP Build and Test Infrastructure
13.2.
Device Libraries
❱
13.2.1.
DIF Library
❱
13.2.1.1.
ADC Checklist
13.2.1.2.
AES Checklist
13.2.1.3.
Alert Handler Checklist
13.2.1.4.
Always-On Timer Checklist
13.2.1.5.
Clock Manager Checklist
13.2.1.6.
CSRNG Checklist
13.2.1.7.
EDN Checklist
13.2.1.8.
Entropy Source Checklist
13.2.1.9.
Flash Controller Checklist
13.2.1.10.
GPIO Checklist
13.2.1.11.
HMAC Checklist
13.2.1.12.
I2C Checklist
13.2.1.13.
Key Manager Checklist
13.2.1.14.
KMAC Checklist
13.2.1.15.
Lifecycle Checklist
13.2.1.16.
OTBN Checklist
13.2.1.17.
OTP Controller Checklist
13.2.1.18.
Pattern Generator Checklist
13.2.1.19.
Pin Multiplexer Checklist
13.2.1.20.
PWM Checklist
13.2.1.21.
Power Manager Checklist
13.2.1.22.
ROM Checklist
13.2.1.23.
Reset Manager Checklist
13.2.1.24.
RV Core Ibex Checklist
13.2.1.25.
PLIC Checklist
13.2.1.26.
RV Timer Checklist
13.2.1.27.
Sensor Controller Checklist
13.2.1.28.
SPI Device Checklist
13.2.1.29.
SPI Host Checklist
13.2.1.30.
SRAM Controller Checklist
13.2.1.31.
System Reset Controller Checklist
13.2.1.32.
UART Checklist
13.2.1.33.
USB Checklist
13.2.2.
Top-Level Test Libraries
❱
13.2.2.1.
On-Device Test Framework
13.2.3.
OpenTitan Standard Library
❱
13.2.3.1.
Freestanding C Headers
13.3.
Silicon Creator Software
❱
13.3.1.
Manufacturing Firmware
❱
13.3.1.1.
Test Plan
13.3.2.
ROM
❱
13.3.2.1.
ROM Specification
13.3.2.2.
Bootstrap
13.3.2.3.
Memory Protection
13.3.2.4.
E2E tests
13.3.2.5.
Root Keys
13.3.2.6.
Signature Verification
13.3.2.7.
Test Plan
13.3.2.8.
Signoff Test Plan
13.3.2.9.
Shutdown Specification
13.3.3.
ROM_EXT
❱
13.3.3.1.
ROM_EXT for Silicon Validation
13.3.3.2.
ROM_EXT Ownership Transfer
13.3.3.3.
ROM_EXT Rescue Protocol
13.3.4.
Manifest Format
13.3.5.
Boot Log
13.4.
Top-Level Tests
❱
13.4.1.
Manufacturer Test Hooks
13.4.2.
Cryptotest
13.5.
Silicon Validation
❱
13.5.1.
Developer Guide
14.
Host Software
❱
14.1.
OpenTitanLib
14.2.
OpenTitanTool
14.3.
OpenTitanSession
14.4.
OpenTitan Certificate Generator
14.5.
Hardware Security Module (HSM) tool
❱
14.5.1.
Requirements
14.5.2.
Signing Guide
14.6.
TPM2 Test Server
Tooling
15.
Tools Overview
16.
Design-Related Tooling
17.
dvsim
❱
17.1.
Design Document
17.2.
Testplanner
17.3.
Glossary
18.
fpvgen: Initial FPV Testbench Generation
19.
reggen & regtool: Register Generator
❱
19.1.
Setup and use of regtool
20.
ralgen: FuseSoC UVM RAL Generator
21.
uvmdvgen: Initial Testbench Auto-generation
22.
tlgen: Crossbar Generation
23.
ipgen: Generate IP Blocks from IP Templates
24.
topgen: Top Generator
25.
vendor: Vendoring In Tool
26.
i2csvg: Generate SVGs of I2C Commands
Contributing
27.
Contributing
❱
27.1.
Detailed Contribution Guide
27.2.
Directory Structure
27.3.
Contributing to Documentation
❱
27.3.1.
An Example IP Block's Documentation
27.4.
Continuous Intergration
27.5.
Top-Level Design and Targets
27.6.
GitHub Notes
27.7.
Bazel Notes
27.8.
Using the Container
28.
Contributing to Hardware
❱
28.1.
Comportability
28.2.
Hardware Design
28.3.
Design Methodology
28.4.
Vendoring in Hardware
28.5.
Linting
28.6.
Synthesis Flow
29.
Contributing to Verification
❱
29.1.
Verification Methodology
29.2.
Security Countermeasure Verification Framework
29.3.
Assertions
30.
Contributing to Software
❱
30.1.
Device Interface Functions
30.2.
Writing and Building Software for OTBN
31.
Style Guides
❱
31.1.
HJSON
31.2.
Python
31.3.
C & C++
31.4.
Markdown
31.5.
RISC-V Assembly
31.6.
OTBN Assembly
31.7.
Guidance for Volatile
32.
Developing on an FPGA
❱
32.1.
Get a Board
32.2.
FPGA Reference Manual
32.3.
Debugging with an ILA
Project Governance
33.
Introduction
34.
Committers
35.
RFC Process
36.
Generalized Priority Definitions
37.
Generalized Project Milestone Definitions
38.
OpenTitan Technical Committee
39.
Hardware Development Stages
40.
Signoff Checklist
Security
41.
Security
42.
Cryptography Library
❱
42.1.
API Documentation
42.2.
Contributing
43.
Implementation Guidelines
❱
43.1.
Secure Hardware Design Guidelines
43.2.
Reset vs. Non-Reset Flops
44.
Logical Security Model
45.
Security Model Specification
❱
45.1.
Device Attestation
45.2.
Device Life Cycle
45.3.
Device Provisioning
45.4.
Firmware Update
45.5.
Identities and Root Keys
45.6.
Ownership Transfer
45.7.
Secure Boot
46.
Lightweight Threat Model
Use Cases
47.
Use Cases
48.
Platform Integrity Module
49.
Trusted Platform Module
50.
Universal 2nd-Factor Security Key
Rust for C Developers
51.
Rust for Embedded C Programmers
Appendix
52.
Glossary
OpenTitan Light
opentitan.org
I2C DV UVM Agent
I2C UVM Agent is extended from DV library agent classes.