Testplan

Testpoints

Stage V1 Testpoints

ac_range_check_smoke

Test: ac_range_check_smoke

Smoke test in which we configure a randomized number of ranges to allow a transfer and perform transfers.

Stimulus:

  • Assert range_check_overwrite_i to MuBi8::False
  • Configure a random number of ranges:
    • Randomize the RANGE_BASE and RANGE_LIMIT register (RANGE_LIMIT > RANGE_BASE)
    • Randomize the RANGE_ATTR register and set the RANGE_ATTR.enable bit to 1
    • Set RANGE_RACL_POLICY_SHADOWED.read_perm and RANGE_RACL_POLICY_SHADOWED.write_perm to 0xFFFF (disables RACL checks)
  • Perform random TLUL requests on the unfiltered interface (ctn_tl_h2d_i) and provide random TLUL responses on the filtered interface (ctn_filtered_tl_d2h_i).

Checking:

  • If a request falls outside of any enabled range:
    • The request should be denied and an error should be returned in the response on the unfiltered TLUL D channel (ctn_tl_d2h_o).
    • Read and Execute requests should return all zero as data on the unfiltered TLUL D channel (ctn_tl_d2h_o).
  • If the request falls into the address space of at least one enabled range, the request is allowed if and only if the permissions of that range allow it (e.g., if the access is a data read, the range needs to allow reads for the access to be allowed) and it does not fall into the address space of any other enabled range with lower index whose permissions deny the request. Allowed requests should propagate without modifications on the A channel. And the corresponding responses should propagate unmodified on the D channel. One exception to this is the d_data field for AccessAck responses (i.e., responses to writes): the TL-UL spec defines that this field in this case can be any value, and the current implementation sets it to zero (for the reason described in PR #1236).

csr_hw_reset

Test: ac_range_check_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_rw

Test: ac_range_check_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_bit_bash

Test: ac_range_check_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_aliasing

Test: ac_range_check_csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_mem_rw_with_rand_reset

Test: ac_range_check_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.

regwen_csr_and_corresponding_lockable_csr

Tests:

  • ac_range_check_csr_rw
  • ac_range_check_csr_aliasing

Verify regwen CSR and its corresponding lockable CSRs.

  • Randomly access all CSRs
  • Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

  • If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
  • If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

Stage V2 Testpoints

ac_range_check_lock_range

Test: ac_range_check_lock_range

Test the range lock functionality

Stimulus:

  • Configure a range’s RANGE_BASE, RANGE_LIMIT, RANGE_ATTR, RANGE_RACL_POLICY_SHADOWED register
  • Clear RANGE_REGWEN to MuBi4::False in a randomized way
  • Try to reconfigure the range with different values

Checking:

  • If RANGE_REGWEN was cleared to MuBi4::False, the reconfigured register values The original configuration should remain in the registers. If RANGE_REGWEN was not cleared, the reconfigured values should have replaced the original ones.

ac_range_bypass_enable

Test: ac_range_check_bypass

Test the bypass functionality for enabled ranges.

Stimulus:

  • Assert range_check_overwrite_i to Mubi8::True
  • Configure the AC range check to block certain address ranges
    • Randomize type of denial (R/W/X, RACL policies)
  • Perform random TLUL requests that fall within blocked ranges and outside with:
    • Random request type (R/W/X) and random RACL role

Checking:

  • Check if all transfers are allowed
  • LOG_STATUS.deny_cnt must stay 0

alert_test

Test: ac_range_check_alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

  • Enable a random set of alert requests by writing random value to alert_test CSR.
  • Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
  • During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
  • Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
  • Repeat the above steps a bunch of times.

intr_test

Test: ac_range_check_intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly “turn on” interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.

tl_d_oob_addr_access

Test: ac_range_check_tl_errors

Access out of bounds address and verify correctness of response / behavior

tl_d_illegal_access

Test: ac_range_check_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec

  • TL-UL protocol error cases
    • invalid opcode
    • some mask bits not set when opcode is PutFullData
    • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
    • address and size aren’t aligned, e.g. a_address = 0x01, a_size != 0
    • size is greater than 2
  • OpenTitan defined error cases
    • access unmapped address, expect d_error = 1
    • write a CSR with unaligned address, e.g. a_address[1:0] != 0
    • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • write a memory with a_mask != '1 when it doesn’t support partial accesses
    • read a WO (write-only) memory
    • write a RO (read-only) memory
    • write with instr_type = True

tl_d_outstanding_access

Tests:

  • ac_range_check_csr_hw_reset
  • ac_range_check_csr_rw
  • ac_range_check_csr_aliasing
  • ac_range_check_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

tl_d_partial_access

Tests:

  • ac_range_check_csr_hw_reset
  • ac_range_check_csr_rw
  • ac_range_check_csr_aliasing
  • ac_range_check_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Stage V2S Testpoints

tl_intg_err

Tests:

  • ac_range_check_tl_intg_err
  • ac_range_check_sec_cm

Verify that the data integrity check violation generates an alert.

  • Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
  • Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs

Covergroups

ac_range_check_log_status_cg

Cover all status fields of the LOG_STATUS. (deny_cnt and deny_range_index are not part of this).

regwen_val_when_new_value_written_cg

Cover each lockable reg field with these 2 cases:

  • When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
  • When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

tl_errors_cg

Cover the following error cases on TL-UL bus:

  • TL-UL protocol error cases.
  • OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.