Registers

Summary

NameOffsetLengthDescription
lc_ctrl.ALERT_TEST0x04Alert Test Register
lc_ctrl.STATUS0x44life cycle status register. Note that all errors are terminal and require a reset cycle.
lc_ctrl.CLAIM_TRANSITION_IF_REGWEN0x84Register write enable for the hardware mutex register.
lc_ctrl.CLAIM_TRANSITION_IF0xc4Hardware mutex to claim exclusive access to the transition interface.
lc_ctrl.TRANSITION_REGWEN0x104Register write enable for all transition interface registers.
lc_ctrl.TRANSITION_CMD0x144Command register for state transition requests.
lc_ctrl.TRANSITION_CTRL0x184Control register for state transition requests.
lc_ctrl.TRANSITION_TOKEN_00x1c4128bit token for conditional transitions.
lc_ctrl.TRANSITION_TOKEN_10x204128bit token for conditional transitions.
lc_ctrl.TRANSITION_TOKEN_20x244128bit token for conditional transitions.
lc_ctrl.TRANSITION_TOKEN_30x284128bit token for conditional transitions.
lc_ctrl.TRANSITION_TARGET0x2c4This register exposes the decoded life cycle state.
lc_ctrl.OTP_VENDOR_TEST_CTRL0x304Test/vendor-specific settings for the OTP macro wrapper.
lc_ctrl.OTP_VENDOR_TEST_STATUS0x344Test/vendor-specific settings for the OTP macro wrapper.
lc_ctrl.LC_STATE0x384This register exposes the decoded life cycle state.
lc_ctrl.LC_TRANSITION_CNT0x3c4This register exposes the state of the decoded life cycle transition counter.
lc_ctrl.LC_ID_STATE0x404This register exposes the id state of the device.
lc_ctrl.HW_REVISION00x444This register holds the SILICON_CREATOR_ID and the PRODUCT_ID.
lc_ctrl.HW_REVISION10x484This register holds the REVISION_ID.
lc_ctrl.DEVICE_ID_00x4c4This is the 256bit DEVICE_ID value that is stored in the HW_CFG0 partition in OTP.
lc_ctrl.DEVICE_ID_10x504This is the 256bit DEVICE_ID value that is stored in the HW_CFG0 partition in OTP.
lc_ctrl.DEVICE_ID_20x544This is the 256bit DEVICE_ID value that is stored in the HW_CFG0 partition in OTP.
lc_ctrl.DEVICE_ID_30x584This is the 256bit DEVICE_ID value that is stored in the HW_CFG0 partition in OTP.
lc_ctrl.DEVICE_ID_40x5c4This is the 256bit DEVICE_ID value that is stored in the HW_CFG0 partition in OTP.
lc_ctrl.DEVICE_ID_50x604This is the 256bit DEVICE_ID value that is stored in the HW_CFG0 partition in OTP.
lc_ctrl.DEVICE_ID_60x644This is the 256bit DEVICE_ID value that is stored in the HW_CFG0 partition in OTP.
lc_ctrl.DEVICE_ID_70x684This is the 256bit DEVICE_ID value that is stored in the HW_CFG0 partition in OTP.
lc_ctrl.MANUF_STATE_00x6c4This is a 256bit field used for keeping track of the manufacturing state.
lc_ctrl.MANUF_STATE_10x704This is a 256bit field used for keeping track of the manufacturing state.
lc_ctrl.MANUF_STATE_20x744This is a 256bit field used for keeping track of the manufacturing state.
lc_ctrl.MANUF_STATE_30x784This is a 256bit field used for keeping track of the manufacturing state.
lc_ctrl.MANUF_STATE_40x7c4This is a 256bit field used for keeping track of the manufacturing state.
lc_ctrl.MANUF_STATE_50x804This is a 256bit field used for keeping track of the manufacturing state.
lc_ctrl.MANUF_STATE_60x844This is a 256bit field used for keeping track of the manufacturing state.
lc_ctrl.MANUF_STATE_70x884This is a 256bit field used for keeping track of the manufacturing state.

ALERT_TEST

Alert Test Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x7

Fields

{"reg": [{"name": "fatal_prog_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_state_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_bus_integ_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
BitsTypeResetNameDescription
31:3Reserved
2wo0x0fatal_bus_integ_errorWrite 1 to trigger one alert event of this kind.
1wo0x0fatal_state_errorWrite 1 to trigger one alert event of this kind.
0wo0x0fatal_prog_errorWrite 1 to trigger one alert event of this kind.

STATUS

life cycle status register. Note that all errors are terminal and require a reset cycle.

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0xfff

Fields

{"reg": [{"name": "INITIALIZED", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "READY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "EXT_CLOCK_SWITCHED", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TRANSITION_SUCCESSFUL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TRANSITION_COUNT_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TRANSITION_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TOKEN_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FLASH_RMA_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "OTP_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "STATE_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "BUS_INTEG_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "OTP_PARTITION_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}

STATUS . OTP_PARTITION_ERROR

This bit is set to 1 if the life cycle partition in OTP is in error state. This bit is intended for production testing during the RAW life cycle state, where the OTP control and status registers are not accessible. This error does not trigger an alert in the life cycle controller.

STATUS . BUS_INTEG_ERROR

This bit is set to 1 if a fatal bus integrity fault is detected. This error triggers a fatal_bus_integ_error alert.

STATUS . STATE_ERROR

This bit is set to 1 if either the controller FSM state or the life cycle state is invalid or has been corrupted as part of a tampering attempt. This error will move the life cycle state automatically to INVALID and raise a fatal_state_error alert.

STATUS . OTP_ERROR

This bit is set to 1 if an error occurred during an OTP programming operation. This error will move the life cycle state automatically to POST_TRANSITION and raise a fatal_prog_error alert.

STATUS . FLASH_RMA_ERROR

This bit is set to 1 if flash failed to correctly respond to an RMA request. Note that each transition attempt increments the LC_TRANSITION_CNT and moves the life cycle state into POST_TRANSITION.

STATUS . TOKEN_ERROR

This bit is set to 1 if the token supplied for a conditional transition was invalid. Note that each transition attempt increments the LC_TRANSITION_CNT and moves the life cycle state into POST_TRANSITION.

STATUS . TRANSITION_ERROR

This bit is set to 1 if the last transition command requested an invalid state transition (e.g. DEV -> RAW). Note that each transition attempt increments the LC_TRANSITION_CNT and moves the life cycle state into POST_TRANSITION.

STATUS . TRANSITION_COUNT_ERROR

This bit is set to 1 if the LC_TRANSITION_CNT has reached its maximum. If this is the case, no more state transitions can be performed. Note that each transition attempt increments the LC_TRANSITION_CNT and moves the life cycle state into POST_TRANSITION.

STATUS . TRANSITION_SUCCESSFUL

This bit is set to 1 if the last life cycle transition request was successful. Note that each transition attempt increments the LC_TRANSITION_CNT and moves the life cycle state into POST_TRANSITION.

STATUS . EXT_CLOCK_SWITCHED

This bit is set to 1 if the clock manager has successfully switched to the external clock due to EXT_CLOCK_EN being set to 1.

STATUS . READY

This bit is set to 1 if the life cycle controller has successfully initialized and is ready to accept a life cycle transition command.

STATUS . INITIALIZED

This bit is set to 1 if the life cycle controller has successfully initialized and the state exposed in LC_STATE and LC_TRANSITION_CNT is valid.

CLAIM_TRANSITION_IF_REGWEN

Register write enable for the hardware mutex register.

  • Offset: 0x8
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

{"reg": [{"name": "CLAIM_TRANSITION_IF_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 280}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1CLAIM_TRANSITION_IF_REGWENThis bit is managed by software and is set to 1 by default. When cleared to 0, the CLAIM_TRANSITION_IF mutex register cannot be written to anymore. Write 0 to clear this bit.

CLAIM_TRANSITION_IF

Hardware mutex to claim exclusive access to the transition interface.

Fields

{"reg": [{"name": "MUTEX", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:8Reserved
7:0rw0x69MUTEX

CLAIM_TRANSITION_IF . MUTEX

In order to have exclusive access to the transition interface, SW must first claim the associated hardware mutex by writing kMultiBitBool8True to this register. If the register reads back kMultiBitBool8True, the mutex claim has been successful, and TRANSITION_REGWEN will be set automatically to 1 by HW. Write 0 to this register in order to release the HW mutex.

TRANSITION_REGWEN

Register write enable for all transition interface registers.

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

{"reg": [{"name": "TRANSITION_REGWEN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
BitsTypeResetName
31:1Reserved
0ro0x0TRANSITION_REGWEN

TRANSITION_REGWEN . TRANSITION_REGWEN

This bit is hardware-managed and only readable by software. By default, this bit is set to 0 by hardware. Once SW has claimed the CLAIM_TRANSITION_IF mutex, this bit will be set to 1. Note that the life cycle controller sets this bit temporarily to 0 while executing a life cycle state transition.

TRANSITION_CMD

Command register for state transition requests.

Fields

{"reg": [{"name": "START", "bits": 1, "attr": ["r0w1c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:1Reserved
0r0w1cxSTART

TRANSITION_CMD . START

Writing a 1 to this register initiates the life cycle state transition to the state specified in TRANSITION_TARGET. Note that not all transitions are possible, and certain conditional transitions require an additional TRANSITION_TOKEN_0. In order to have exclusive access to this register, SW must first claim the associated hardware mutex via CLAIM_TRANSITION_IF.

TRANSITION_CTRL

Control register for state transition requests.

Fields

{"reg": [{"name": "EXT_CLOCK_EN", "bits": 1, "attr": ["rw1s"], "rotate": -90}, {"name": "VOLATILE_RAW_UNLOCK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
BitsTypeResetName
31:2Reserved
1rwxVOLATILE_RAW_UNLOCK
0rw1sxEXT_CLOCK_EN

TRANSITION_CTRL . VOLATILE_RAW_UNLOCK

When set to 1, LC_CTRL performs a volatile lifecycle transition from RAW -> TEST_UNLOCKED0. No state update will be written to OTP, and no reset will be needed after the transition has succeeded. Note that the token to be provided has to be the hashed unlock token, since in this case the token is NOT passed through KMAC before performing the comparison.

After a successful VOLATILE_RAW_UNLOCK transition from RAW -> TEST_UNLOCKED0, the LC_CTRL FSM will go back to the IdleSt and set the STATUS.TRANSITION_SUCCESSFUL bit. The LC_CTRL accepts further transition commands in this state.

IMPORTANT NOTE: this feature is intended for test chips only in order to mitigate the risks of a malfunctioning OTP macro. Production devices will permanently disable this feature at compile time via the SecVolatileRawUnlockEn parameter.

Software can check whether VOLATILE_RAW_UNLOCK is available by writing 1 and reading back the register value. If the register reads back as 1 the mechanism is available, and if it reads back 0 it is not.

TRANSITION_CTRL . EXT_CLOCK_EN

When set to 1, the OTP clock will be switched to an externally supplied clock right away when the device is in a non-PROD life cycle state. The clock mux will remain switched until the next system reset.

TRANSITION_TOKEN

128bit token for conditional transitions. Make sure to set this to 0 for unconditional transitions. Note that this register is shared with the life cycle TAP interface. In order to have exclusive access to this register, SW must first claim the associated hardware mutex via CLAIM_TRANSITION_IF.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
TRANSITION_TOKEN_00x1c
TRANSITION_TOKEN_10x20
TRANSITION_TOKEN_20x24
TRANSITION_TOKEN_30x28

Fields

{"reg": [{"name": "TRANSITION_TOKEN", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rwxTRANSITION_TOKEN

TRANSITION_TARGET

This register exposes the decoded life cycle state.

  • Offset: 0x2c
  • Reset default: 0x0
  • Reset mask: 0x3fffffff
  • Register enable: TRANSITION_REGWEN

Fields

{"reg": [{"name": "STATE", "bits": 30, "attr": ["rw"], "rotate": 0}, {"bits": 2}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:30Reserved
29:0rwxSTATE

TRANSITION_TARGET . STATE

This field encodes the target life cycle state in a redundant enum format. The 5bit state enum is repeated 6x so that it fills the entire 32bit register. The encoding is straightforward replication: [val, val, val, val, val, val].

Note that this register is shared with the life cycle TAP interface. In order to have exclusive access to this register, SW must first claim the associated hardware mutex via CLAIM_TRANSITION_IF.

ValueNameDescription
0x00000000RAWRaw life cycle state after fabrication where all functions are disabled.
0x02108421TEST_UNLOCKED0Unlocked test state where debug functions are enabled.
0x04210842TEST_LOCKED0Locked test state where where all functions are disabled.
0x06318c63TEST_UNLOCKED1Unlocked test state where debug functions are enabled.
0x08421084TEST_LOCKED1Locked test state where where all functions are disabled.
0x0a5294a5TEST_UNLOCKED2Unlocked test state where debug functions are enabled.
0x0c6318c6TEST_LOCKED2Locked test state where debug all functions are disabled.
0x0e739ce7TEST_UNLOCKED3Unlocked test state where debug functions are enabled.
0x10842108TEST_LOCKED3Locked test state where debug all functions are disabled.
0x1294a529TEST_UNLOCKED4Unlocked test state where debug functions are enabled.
0x14a5294aTEST_LOCKED4Locked test state where debug all functions are disabled.
0x16b5ad6bTEST_UNLOCKED5Unlocked test state where debug functions are enabled.
0x18c6318cTEST_LOCKED5Locked test state where debug all functions are disabled.
0x1ad6b5adTEST_UNLOCKED6Unlocked test state where debug functions are enabled.
0x1ce739ceTEST_LOCKED6Locked test state where debug all functions are disabled.
0x1ef7bdefTEST_UNLOCKED7Unlocked test state where debug functions are enabled.
0x21084210DEVDevelopment life cycle state where limited debug functionality is available.
0x2318c631PRODProduction life cycle state.
0x25294a52PROD_ENDSame as PROD, but transition into RMA is not possible from this state.
0x2739ce73RMARMA life cycle state.
0x294a5294SCRAPSCRAP life cycle state where all functions are disabled.

Other values are reserved.

OTP_VENDOR_TEST_CTRL

Test/vendor-specific settings for the OTP macro wrapper. These values are only active during RAW, TEST_* and RMA life cycle states. In all other states, these values will be gated to zero before sending them to the OTP macro wrapper - even if this register is programmed to a non-zero value.

  • Offset: 0x30
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: TRANSITION_REGWEN

Fields

{"reg": [{"name": "OTP_VENDOR_TEST_CTRL", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rwxOTP_VENDOR_TEST_CTRL

OTP_VENDOR_TEST_STATUS

Test/vendor-specific settings for the OTP macro wrapper. These values are only active during RAW, TEST_* and RMA life cycle states. In all other states, these values will read as zero.

  • Offset: 0x34
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "OTP_VENDOR_TEST_STATUS", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0roxOTP_VENDOR_TEST_STATUS

LC_STATE

This register exposes the decoded life cycle state.

  • Offset: 0x38
  • Reset default: 0x0
  • Reset mask: 0x3fffffff

Fields

{"reg": [{"name": "STATE", "bits": 30, "attr": ["ro"], "rotate": 0}, {"bits": 2}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:30Reserved
29:0roxSTATE

LC_STATE . STATE

This field exposes the decoded life cycle state in a redundant enum format. The 5bit state enum is repeated 6x so that it fills the entire 32bit register. The encoding is straightforward replication: [val, val, val, val, val, val].

ValueNameDescription
0x00000000RAWRaw life cycle state after fabrication where all functions are disabled.
0x02108421TEST_UNLOCKED0Unlocked test state where debug functions are enabled.
0x04210842TEST_LOCKED0Locked test state where where all functions are disabled.
0x06318c63TEST_UNLOCKED1Unlocked test state where debug functions are enabled.
0x08421084TEST_LOCKED1Locked test state where where all functions are disabled.
0x0a5294a5TEST_UNLOCKED2Unlocked test state where debug functions are enabled.
0x0c6318c6TEST_LOCKED2Locked test state where debug all functions are disabled.
0x0e739ce7TEST_UNLOCKED3Unlocked test state where debug functions are enabled.
0x10842108TEST_LOCKED3Locked test state where debug all functions are disabled.
0x1294a529TEST_UNLOCKED4Unlocked test state where debug functions are enabled.
0x14a5294aTEST_LOCKED4Locked test state where debug all functions are disabled.
0x16b5ad6bTEST_UNLOCKED5Unlocked test state where debug functions are enabled.
0x18c6318cTEST_LOCKED5Locked test state where debug all functions are disabled.
0x1ad6b5adTEST_UNLOCKED6Unlocked test state where debug functions are enabled.
0x1ce739ceTEST_LOCKED6Locked test state where debug all functions are disabled.
0x1ef7bdefTEST_UNLOCKED7Unlocked test state where debug functions are enabled.
0x21084210DEVDevelopment life cycle state where limited debug functionality is available.
0x2318c631PRODProduction life cycle state.
0x25294a52PROD_ENDSame as PROD, but transition into RMA is not possible from this state.
0x2739ce73RMARMA life cycle state.
0x294a5294SCRAPSCRAP life cycle state where all functions are disabled.
0x2b5ad6b5POST_TRANSITIONThis state is temporary and behaves the same way as SCRAP.
0x2d6b5ad6ESCALATEThis state is temporary and behaves the same way as SCRAP.
0x2f7bdef7INVALIDThis state is reported when the life cycle state encoding is invalid. This state is temporary and behaves the same way as SCRAP.

Other values are reserved.

LC_TRANSITION_CNT

This register exposes the state of the decoded life cycle transition counter.

  • Offset: 0x3c
  • Reset default: 0x0
  • Reset mask: 0x1f

Fields

{"reg": [{"name": "CNT", "bits": 5, "attr": ["ro"], "rotate": 0}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:5Reserved
4:0roxCNT

LC_TRANSITION_CNT . CNT

Number of total life cycle state transition attempts. The life cycle controller allows up to 24 transition attempts. If this counter is equal to 24, the LC_STATE is considered to be invalid and will read as SCRAP.

If the counter state is invalid, or the life cycle controller is in the post-transition state, the counter will have the value 31 (i.e., all counter bits will be set).

LC_ID_STATE

This register exposes the id state of the device.

  • Offset: 0x40
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "STATE", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:0roxSTATE

LC_ID_STATE . STATE

This field exposes the id state in redundant enum format. The 2bit id state enum is repeated 16x so that it fills the entire 32bit register. The encoding is straightforward replication: [val, val, … val].“

ValueNameDescription
0x00000000BLANKThe device has not yet been personalized.
0x55555555PERSONALIZEDThe device has been personalized.
0xaaaaaaaaINVALIDThe state is not valid.

Other values are reserved.

HW_REVISION0

This register holds the SILICON_CREATOR_ID and the PRODUCT_ID.

  • Offset: 0x44
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "PRODUCT_ID", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "SILICON_CREATOR_ID", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:16roxSILICON_CREATOR_ID
15:0roxPRODUCT_ID

HW_REVISION0 . SILICON_CREATOR_ID

ID of the silicon creator. Assigned by the OpenTitan project. Zero is an invalid value. The encoding must follow the following range constraints:

0x0000: invalid value 0x0001 - 0x3FFF: reserved for use in the open-source OpenTitan project 0x4000 - 0x7FFF: reserved for real integrations of OpenTitan 0x8000 - 0xFFFF: reserved for future use

HW_REVISION0 . PRODUCT_ID

Used to identify a class of devices. Assigned by the Silicon Creator. Zero is an invalid value. The encoding must follow the following range constraints:

0x0000: invalid value 0x0001 - 0x3FFF: reserved for discrete chip products 0x4000 - 0x7FFF: reserved for integrated IP products 0x8000 - 0xFFFF: reserved for future use

HW_REVISION1

This register holds the REVISION_ID.

  • Offset: 0x48
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "REVISION_ID", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "RESERVED", "bits": 24, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:8ro0x0RESERVED
7:0roxREVISION_ID

HW_REVISION1 . RESERVED

Reserved bits. Set to zero.

HW_REVISION1 . REVISION_ID

Product revision ID. Assigned by the Silicon Creator. The encoding is not specified other than that different tapeouts must be assigned different revision numbers. I.e., each base or metal layer respin must be reflected so that software can rely on it to modify firmware and driver behavior. Zero is an invalid value.

DEVICE_ID

This is the 256bit DEVICE_ID value that is stored in the HW_CFG0 partition in OTP. If this register reads all-one, the HW_CFG0 partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
DEVICE_ID_00x4c
DEVICE_ID_10x50
DEVICE_ID_20x54
DEVICE_ID_30x58
DEVICE_ID_40x5c
DEVICE_ID_50x60
DEVICE_ID_60x64
DEVICE_ID_70x68

Fields

{"reg": [{"name": "DEVICE_ID", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0roxDEVICE_ID

MANUF_STATE

This is a 256bit field used for keeping track of the manufacturing state.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
MANUF_STATE_00x6c
MANUF_STATE_10x70
MANUF_STATE_20x74
MANUF_STATE_30x78
MANUF_STATE_40x7c
MANUF_STATE_50x80
MANUF_STATE_60x84
MANUF_STATE_70x88

Fields

{"reg": [{"name": "MANUF_STATE", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0roxMANUF_STATE