Registers

Summary

NameOffsetLengthDescription
aon_timer.ALERT_TEST0x04Alert Test Register
aon_timer.WKUP_CTRL0x44Wakeup Timer Control register
aon_timer.WKUP_THOLD_HI0x84Wakeup Timer Threshold Register (bits 63 - 32)
aon_timer.WKUP_THOLD_LO0xc4Wakeup Timer Threshold Register (bits 31 - 0)
aon_timer.WKUP_COUNT_HI0x104Wakeup Timer Count Register (bits 63 - 32)
aon_timer.WKUP_COUNT_LO0x144Wakeup Timer Count Register (bits 31 - 0)
aon_timer.WDOG_REGWEN0x184Watchdog Timer Write Enable Register
aon_timer.WDOG_CTRL0x1c4Watchdog Timer Control register
aon_timer.WDOG_BARK_THOLD0x204Watchdog Timer Bark Threshold Register
aon_timer.WDOG_BITE_THOLD0x244Watchdog Timer Bite Threshold Register
aon_timer.WDOG_COUNT0x284Watchdog Timer Count Register
aon_timer.INTR_STATE0x2c4Interrupt State Register
aon_timer.INTR_TEST0x304Interrupt Test Register
aon_timer.WKUP_CAUSE0x344Wakeup request status

ALERT_TEST

Alert Test Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.

WKUP_CTRL

Wakeup Timer Control register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x1fff

Fields

BitsTypeResetNameDescription
31:13Reserved
12:1rw0x0prescalerPre-scaler value for wakeup timer count
0rw0x0enableWhen set to 1, the wakeup timer will count

WKUP_THOLD_HI

Wakeup Timer Threshold Register (bits 63 - 32)

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0threshold_hiThe count at which a wakeup interrupt should be generated, top 32 bits

WKUP_THOLD_LO

Wakeup Timer Threshold Register (bits 31 - 0)

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0threshold_loThe count at which a wakeup interrupt should be generated, bottom 32 bits

WKUP_COUNT_HI

Wakeup Timer Count Register (bits 63 - 32)

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0count_hiThe current wakeup counter value, top 32 bits

WKUP_COUNT_LO

Wakeup Timer Count Register (bits 31 - 0)

  • Offset: 0x14
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0count_loThe current wakeup counter value, bottom 32 bits

WDOG_REGWEN

Watchdog Timer Write Enable Register

  • Offset: 0x18
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1regwenOnce cleared, the watchdog configuration will be locked until the next reset

WDOG_CTRL

Watchdog Timer Control register

  • Offset: 0x1c
  • Reset default: 0x0
  • Reset mask: 0x3
  • Register enable: WDOG_REGWEN

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw0x0pause_in_sleepWhen set to 1, the watchdog timer will not count during sleep
0rw0x0enableWhen set to 1, the watchdog timer will count

WDOG_BARK_THOLD

Watchdog Timer Bark Threshold Register

  • Offset: 0x20
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: WDOG_REGWEN

Fields

BitsTypeResetNameDescription
31:0rw0x0thresholdThe count at which a watchdog bark interrupt should be generated

WDOG_BITE_THOLD

Watchdog Timer Bite Threshold Register

  • Offset: 0x24
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: WDOG_REGWEN

Fields

BitsTypeResetNameDescription
31:0rw0x0thresholdThe count at which a watchdog bite reset should be generated

WDOG_COUNT

Watchdog Timer Count Register

  • Offset: 0x28
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0countThe current watchdog counter value

INTR_STATE

Interrupt State Register

  • Offset: 0x2c
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw1c0x0wdog_timer_barkRaised if the watchdog timer has hit the bark threshold
0rw1c0x0wkup_timer_expiredRaised if the wakeup timer has hit the specified threshold

INTR_TEST

Interrupt Test Register

  • Offset: 0x30
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1woxwdog_timer_barkWrite 1 to force wdog_timer_bark interrupt
0woxwkup_timer_expiredWrite 1 to force wkup_timer_expired interrupt

WKUP_CAUSE

Wakeup request status

  • Offset: 0x34
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x0causeAON timer requested wakeup, write 0 to clear