Registers

Summary

INTR_STATE

Interrupt State Register

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0xf

Fields

{"reg": [{"name": "es_entropy_valid", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "es_health_test_failed", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "es_observe_fifo_ready", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "es_fatal_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}

INTR_ENABLE

Interrupt Enable Register

• Offset: 0x4
• Reset default: 0x0
• Reset mask: 0xf

Fields

{"reg": [{"name": "es_entropy_valid", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "es_health_test_failed", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "es_observe_fifo_ready", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "es_fatal_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}

INTR_TEST

Interrupt Test Register

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0xf

Fields

{"reg": [{"name": "es_entropy_valid", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "es_health_test_failed", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "es_observe_fifo_ready", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "es_fatal_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}

ALERT_TEST

Alert Test Register

• Offset: 0xc
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "recov_alert", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_alert", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

ME_REGWEN

Register write enable for module enable register

• Offset: 0x10
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "ME_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

SW_REGUPD

Register write enable for control and threshold registers

• Offset: 0x14
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "SW_REGUPD", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

REGWEN

Register write enable for all control registers

• Offset: 0x18
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "REGWEN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

REGWEN . REGWEN

This read-only write enable bit will allow write access to control and threshold registers that are associated with this bit, but only when the MODULE_ENABLE register is set to kMultiBitBool4False and the SW_REGUPD write enable bit is set to true. When read as false, these registers become read-only.

REV

Revision register

• Offset: 0x1c
• Reset default: 0x10303
• Reset mask: 0xffffff

Fields

{"reg": [{"name": "ABI_REVISION", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "HW_REVISION", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "CHIP_TYPE", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MODULE_ENABLE

Module enable register

• Offset: 0x20
• Reset default: 0x9
• Reset mask: 0xf
• Register enable: ME_REGWEN

Fields

{"reg": [{"name": "MODULE_ENABLE", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

MODULE_ENABLE . MODULE_ENABLE

Setting this field to kMultiBitBool4True will enable the ENTROPY_SRC module. Setting this field to kMultiBitBool4False will effectively reset the module. The modules of the entropy complex may only be enabled and disabled in a specific order, see Programmers Guide for details.

CONF

Configuration register

• Offset: 0x24
• Reset default: 0x2649999
• Reset mask: 0x3ffffff
• Register enable: REGWEN

Fields

{"reg": [{"name": "FIPS_ENABLE", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "FIPS_FLAG", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "RNG_FIPS", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "RNG_BIT_ENABLE", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "RNG_BIT_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "THRESHOLD_SCOPE", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ENTROPY_DATA_REG_ENABLE", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}

CONF . ENTROPY_DATA_REG_ENABLE

Setting this field to kMultiBitBool4True will enable reading entropy values from the ENTROPY_DATA register. This function also requires that the otp_en_entropy_src_fw_read input is set to kMultiBitBool8True.

CONF . THRESHOLD_SCOPE

This field controls the scope (either by-line or by-sum) of the health checks. If set to kMultiBitBool4True, the Adaptive Proportion and Markov Tests will accumulate all RNG input lines into a single score, and thresholds will be applied to the sum all the entropy input lines. If set to kMultiBitBool4False, the RNG input lines are all scored individually. A statistical deviation in any one input line, be it due to coincidence or failure, will force rejection of the sample, and count toward the total alert count.

CONF . RNG_BIT_SEL

When CONF.RNG_BIT_ENABLE is set, this field selects which bit from the RNG bus will be processed. This two bit field selects the RNG bit stream: 0b00: RNG bit 0 0b01: RNG bit 1 0b10: RNG bit 2 0b11: RNG bit 3

CONF . RNG_BIT_ENABLE

Setting this field to kMultiBitBool4True enables the single RNG bit mode, where only one bit is sampled per symbol.

CONF . RNG_FIPS

Setting this field to kMultiBitBool4True sets the analog RNG into a conservative operation mode that may reduce the bit rate. In this mode, the RNG potentially outputs entropy with higher entropy per bit and with a simpler sampling mechanism.

CONF . FIPS_FLAG

This flag indicates that the ENTROPY_SRC is setup with the configuration used for FIPS/CC validation. Setting this field to kMultiBitBool4True will set the FIPS flag for the ENTROPY_SRC block output to true.

CONF . FIPS_ENABLE

Setting this field to kMultiBitBool4True selects the mode targeting FIPS/CC compliance (in short FIPS mode) with hardware conditioning enabled. The ENTROPY_SRC block will use the FIPS_WINDOW, FIPS_THRESH and FIPS_WATERMARK values of the HEALTH_TEST_WINDOWS, health test thresholds and watermark register, respectively. Whether the ENTROPY_SRC block is indeed running with the configuration used for FIPS/CC validation is under the control of firmware. Thus, firmware must explicitly mark the produced entropy as FIPS qualified using the CONF.FIPS_FLAG field. Note that the hardware conditioning can still be disabled in FIPS mode by setting both ENTROPY_CONTROL.ES_ROUTE and ENTROPY_CONTROL.ES_TYPE fields to kMultiBitBool4True. However, no entropy is being passed to the block hardware interface in this mode.

Setting this field to kMultiBitBool4False selects the boot-time / bypass mode in which the hardware conditioning is bypassed.

ENTROPY_CONTROL

Entropy control register

• Offset: 0x28
• Reset default: 0x99
• Reset mask: 0xff
• Register enable: REGWEN

Fields

{"reg": [{"name": "ES_ROUTE", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ES_TYPE", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}

ENTROPY_CONTROL . ES_TYPE

When this field is kMultiBitBool4False, the hardware conditioning inside the ENTROPY_SRC block is enabled. Setting this field to kMultiBitBool4True will bypass the hardware conditioning. For this to work, also ENTROPY_CONTROL.ES_ROUTE needs to be set to kMultiBitBool4True to route the unconditioned, raw entropy to the ENTROPY_DATA register. Alternatively, the hardware conditioning can be bypassed by setting CONF.FIPS_ENABLE to kMultiBitBool4False. This enables the bypass / boot-time mode.

ENTROPY_CONTROL . ES_ROUTE

When this field is kMultiBitBool4False, the generated entropy will be forwarded out of this module to the hardware interface. Setting this field to kMultiBitBool4True routes the generated entropy to the ENTROPY_DATA register to be read by firmware. Note that for ENTROPY_DATA to become readable, also CONF.ENTROPY_DATA_REG_ENABLE needs to be set to kMultiBitBool4True. In addition, the otp_en_entropy_src_fw_read input needs to be set to kMultiBitBool8True.

ENTROPY_DATA

Entropy data bits

• Offset: 0x2c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "ENTROPY_DATA", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ENTROPY_DATA . ENTROPY_DATA

A read of this register provides generated entropy bits to firmware. For this to work also CONF.ENTROPY_DATA_REG_ENABLE needs to be set to kMultiBitBool4True. In addition, the otp_en_entropy_src_fw_read input needs to be set to kMultiBitBool8True.

HEALTH_TEST_WINDOWS

Health test windows register

• Offset: 0x30
• Reset default: 0x600200
• Reset mask: 0xffffffff
• Register enable: REGWEN

Fields

{"reg": [{"name": "FIPS_WINDOW", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "BYPASS_WINDOW", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

HEALTH_TEST_WINDOWS . BYPASS_WINDOW

This is the window size for all health tests when running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware by setting CONF.FIPS_ENABLE to kMultiBitBool4False. The default value is (384 bits * 1 clock/4 bits);

Note that currently only a window size of 384 is supported and tested (this corresponds to the register default value 0x60). Do not use any other values, unless you know what you are doing.

HEALTH_TEST_WINDOWS . FIPS_WINDOW

This is the window size for all health tests. This value is used when entropy is being tested in FIPS/CC compliance mode (for simplicity referred to as FIPS mode). The default value is (2048 bits * 1 clock/4 bits);

Note that the number of tested bits taken by the conditioner to produce a seed is equal to the window size x 4. The only exception is the startup seed which is produced using the bits of two subsequent windows, i.e., 2 x window size x 4 tested bits. The factor of 4 relates to the number of noise source channels (i.e. symbol size) and applies both in single-channel and multi-channel mode (see ENTROPY_SRC.RNG_BIT_ENABLE).

Note that NIST SP 800-90B (Table 2) requires the adaptive proportion test to be run on 1024 or 512 samples in single-channel or multi-channel mode, respectively (see ENTROPY_SRC.RNG_BIT_ENABLE). The startup tests must be run on at least 1024 consecutive samples (see Section 4.3 Requirements for Health Tests of NIST SP 800-90B) and this block always uses two subsequent windows for startup health testing. The use of window sizes below 512 samples is thus not recommended as this may not comply with NIST SP 800-90B.

REPCNT_THRESHOLDS

Repetition count test thresholds register

• Offset: 0x34
• Reset default: 0xffffffff
• Reset mask: 0xffffffff
• Register enable: REGWEN

Fields

{"reg": [{"name": "FIPS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "BYPASS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

REPCNT_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the repetition count health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

REPCNT_THRESHOLDS . FIPS_THRESH

This is the threshold size for the repetition count health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

REPCNTS_THRESHOLDS

Repetition count symbol test thresholds register

• Offset: 0x38
• Reset default: 0xffffffff
• Reset mask: 0xffffffff
• Register enable: REGWEN

Fields

{"reg": [{"name": "FIPS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "BYPASS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

REPCNTS_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the repetition count symbol health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

REPCNTS_THRESHOLDS . FIPS_THRESH

This is the threshold size for the repetition count symbol health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

ADAPTP_HI_THRESHOLDS

Adaptive proportion test high thresholds register

• Offset: 0x3c
• Reset default: 0xffffffff
• Reset mask: 0xffffffff
• Register enable: REGWEN

Fields

{"reg": [{"name": "FIPS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "BYPASS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ADAPTP_HI_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the adaptive proportion health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

ADAPTP_HI_THRESHOLDS . FIPS_THRESH

This is the threshold size for the adaptive proportion health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

ADAPTP_LO_THRESHOLDS

Adaptive proportion test low thresholds register

• Offset: 0x40
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: REGWEN

Fields

{"reg": [{"name": "FIPS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "BYPASS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ADAPTP_LO_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the adaptive proportion health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

ADAPTP_LO_THRESHOLDS . FIPS_THRESH

This is the threshold size for the adaptive proportion health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

BUCKET_THRESHOLDS

Bucket test thresholds register

• Offset: 0x44
• Reset default: 0xffffffff
• Reset mask: 0xffffffff
• Register enable: REGWEN

Fields

{"reg": [{"name": "FIPS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "BYPASS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

BUCKET_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the bucket health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

BUCKET_THRESHOLDS . FIPS_THRESH

This is the threshold size for the bucket health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

MARKOV_HI_THRESHOLDS

Markov test high thresholds register

• Offset: 0x48
• Reset default: 0xffffffff
• Reset mask: 0xffffffff
• Register enable: REGWEN

Fields

{"reg": [{"name": "FIPS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "BYPASS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MARKOV_HI_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the Markov health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

MARKOV_HI_THRESHOLDS . FIPS_THRESH

This is the threshold size for the Markov health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

MARKOV_LO_THRESHOLDS

Markov test low thresholds register

• Offset: 0x4c
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: REGWEN

Fields

{"reg": [{"name": "FIPS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "BYPASS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MARKOV_LO_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the Markov health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

MARKOV_LO_THRESHOLDS . FIPS_THRESH

This is the threshold size for the Markov health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

EXTHT_HI_THRESHOLDS

External health test high thresholds register

• Offset: 0x50
• Reset default: 0xffffffff
• Reset mask: 0xffffffff
• Register enable: REGWEN

Fields

{"reg": [{"name": "FIPS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "BYPASS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

EXTHT_HI_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the external health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

EXTHT_HI_THRESHOLDS . FIPS_THRESH

This is the threshold size for the external health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

EXTHT_LO_THRESHOLDS

External health test low thresholds register

• Offset: 0x54
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: REGWEN

Fields

{"reg": [{"name": "FIPS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "BYPASS_THRESH", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

EXTHT_LO_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the external health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

EXTHT_LO_THRESHOLDS . FIPS_THRESH

This is the threshold size for the external health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

REPCNT_HI_WATERMARKS

Repetition count test high watermarks register

• Offset: 0x58
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "FIPS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "BYPASS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

REPCNTS_HI_WATERMARKS

Repetition count symbol test high watermarks register

• Offset: 0x5c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "FIPS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "BYPASS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ADAPTP_HI_WATERMARKS

Adaptive proportion test high watermarks register

• Offset: 0x60
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "FIPS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "BYPASS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ADAPTP_LO_WATERMARKS

Adaptive proportion test low watermarks register

• Offset: 0x64
• Reset default: 0xffffffff
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "FIPS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "BYPASS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

EXTHT_HI_WATERMARKS

External health test high watermarks register

• Offset: 0x68
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "FIPS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "BYPASS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

EXTHT_LO_WATERMARKS

External health test low watermarks register

• Offset: 0x6c
• Reset default: 0xffffffff
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "FIPS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "BYPASS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

BUCKET_HI_WATERMARKS

Bucket test high watermarks register

• Offset: 0x70
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "FIPS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "BYPASS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MARKOV_HI_WATERMARKS

Markov test high watermarks register

• Offset: 0x74
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "FIPS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "BYPASS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MARKOV_LO_WATERMARKS

Markov test low watermarks register

• Offset: 0x78
• Reset default: 0xffffffff
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "FIPS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "BYPASS_WATERMARK", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

REPCNT_TOTAL_FAILS

Repetition count test failure counter register

• Offset: 0x7c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "REPCNT_TOTAL_FAILS", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

REPCNTS_TOTAL_FAILS

Repetition count symbol test failure counter register

• Offset: 0x80
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "REPCNTS_TOTAL_FAILS", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ADAPTP_HI_TOTAL_FAILS

Adaptive proportion high test failure counter register

• Offset: 0x84
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "ADAPTP_HI_TOTAL_FAILS", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ADAPTP_LO_TOTAL_FAILS

Adaptive proportion low test failure counter register

• Offset: 0x88
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "ADAPTP_LO_TOTAL_FAILS", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

BUCKET_TOTAL_FAILS

Bucket test failure counter register

• Offset: 0x8c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "BUCKET_TOTAL_FAILS", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MARKOV_HI_TOTAL_FAILS

Markov high test failure counter register

• Offset: 0x90
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "MARKOV_HI_TOTAL_FAILS", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MARKOV_LO_TOTAL_FAILS

Markov low test failure counter register

• Offset: 0x94
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "MARKOV_LO_TOTAL_FAILS", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

EXTHT_HI_TOTAL_FAILS

External health test high threshold failure counter register

• Offset: 0x98
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "EXTHT_HI_TOTAL_FAILS", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

EXTHT_LO_TOTAL_FAILS

External health test low threshold failure counter register

• Offset: 0x9c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "EXTHT_LO_TOTAL_FAILS", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ALERT_THRESHOLD

Alert threshold register

This register determines during how many subsequent health test windows one or more health test failures can occur before a recoverable alert is raised and the ENTROPY_SRC block stops operating. In case the configured threshold is reached, firmware needs to disable/re-enable the block to restart operation including the startup health testing.

Note that when reaching the threshold while running in Firmware Override: Extract & Insert mode, the recoverable alert is not raised nor does the block stop operating. In other modes, the generation of the recoverable alert can be disabled by configuring a value of zero. The default value is set to two.

• Offset: 0xa0
• Reset default: 0xfffd0002
• Reset mask: 0xffffffff
• Register enable: REGWEN

Fields

{"reg": [{"name": "ALERT_THRESHOLD", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "ALERT_THRESHOLD_INV", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ALERT_SUMMARY_FAIL_COUNTS

Alert summary failure counts register

This register holds the total number of subsequent health test windows during which one or more health test failures occurred. For information on which health tests failed specifically, refer to ALERT_FAIL_COUNTS and EXTHT_FAIL_COUNTS.

If the value of this register reaches the value configured in the ALERT_THRESHOLD register, a recoverable alert is raised and the ENTROPY_SRC block stops operating. If an alert is signaled, the value persists until it is cleared by firmware.

The register is automatically cleared after every passing health test window unless the ENTROPY_SRC is configured in Firmware Override: Extract & Insert mode. The register is also cleared after re-enabling the block.

• Offset: 0xa4
• Reset default: 0x0
• Reset mask: 0xffff

Fields

{"reg": [{"name": "ANY_FAIL_COUNT", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ALERT_FAIL_COUNTS

Alert failure counts register

This register holds the number of health test failures since the last passing health test window. The values are reported on a per-test basis. Note that if multiple health tests fail for a certain window, the value in ALERT_SUMMARY_FAIL_COUNTS is incremented by just one whereas multiple fields in this register may get incremented.

All fields of this register are automatically cleared after every passing health test window unless the ENTROPY_SRC is configured in Firmware Override: Extract & Insert mode. The fields are also cleared after re-enabling the block.

• Offset: 0xa8
• Reset default: 0x0
• Reset mask: 0xfffffff0

Fields

{"reg": [{"bits": 4}, {"name": "REPCNT_FAIL_COUNT", "bits": 4, "attr": ["ro"], "rotate": -90}, {"name": "ADAPTP_HI_FAIL_COUNT", "bits": 4, "attr": ["ro"], "rotate": -90}, {"name": "ADAPTP_LO_FAIL_COUNT", "bits": 4, "attr": ["ro"], "rotate": -90}, {"name": "BUCKET_FAIL_COUNT", "bits": 4, "attr": ["ro"], "rotate": -90}, {"name": "MARKOV_HI_FAIL_COUNT", "bits": 4, "attr": ["ro"], "rotate": -90}, {"name": "MARKOV_LO_FAIL_COUNT", "bits": 4, "attr": ["ro"], "rotate": -90}, {"name": "REPCNTS_FAIL_COUNT", "bits": 4, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

EXTHT_FAIL_COUNTS

External health test alert failure counts register

This register holds the number of external health test failures since the last passing health test window. The values are reported on a per-test basis. Note that if multiple health tests fail for a certain window, the value in ALERT_SUMMARY_FAIL_COUNTS is incremented by just one whereas multiple fields in this register may get incremented.

All fields of this register are automatically cleared after every passing health test window unless the ENTROPY_SRC is configured in Firmware Override: Extract & Insert mode. The fields are also cleared after re-enabling the block.

• Offset: 0xac
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "EXTHT_HI_FAIL_COUNT", "bits": 4, "attr": ["ro"], "rotate": -90}, {"name": "EXTHT_LO_FAIL_COUNT", "bits": 4, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}

FW_OV_CONTROL

Firmware override control register

• Offset: 0xb0
• Reset default: 0x99
• Reset mask: 0xff
• Register enable: REGWEN

Fields

{"reg": [{"name": "FW_OV_MODE", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "FW_OV_ENTROPY_INSERT", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

FW_OV_CONTROL . FW_OV_ENTROPY_INSERT

Setting this field to kMultiBitBool4True allows firmware to extract entropy bits by reading the observe FIFO (see FW_OV_RD_DATA) and insert entropy bits into the entropy flow by writing the FW_OV_WR_DATA register. This is useful e.g. for performing additional health tests and/or firmware-based conditioning. For this to work, FW_OV_CONTROL.FW_OV_MODE needs to be set to kMultiBitBool4True. In addition, the otp_en_entropy_src_fw_over input needs to be set to kMultiBitBool8True.

Firmware can use the hardware conditioning for the inserted entropy bits (see FW_OV_SHA3_START).

Note that if the field is set to kMultiBitBool4True, post-health test entropy bits do NOT continue to flow through the hardware pipeline. Also, the FW_OV_CONTROL.FW_OV_MODE bit must be set. The observe FIFO will collect 2 kBit of contiguous entropy bits. Any entropy bits arriving after the observe FIFO is full are being discarded. Firmware has to read out the entire observe FIFO to restart entropy collection. Only entropy bits inserted by firmware by writing FW_OV_WR_DATA may eventually reach the block hardware interface.

Also, the hardware startup health testing is skipped and firmware becomes responsible for performing any startup health testing.

FW_OV_CONTROL . FW_OV_MODE

Setting this field to kMultiBitBool4True will put the entropy flow in firmware override mode. In this mode, firmware can monitor the post-health test entropy by reading the observe FIFO (see FW_OV_RD_DATA). This includes the entropy bits used for the startup health testing. For this to work, the otp_en_entropy_src_fw_over input needs to be set to kMultiBitBool8True.

Note that the post-health test entropy bits collected in the observe FIFO continue to flow through the hardware pipeline and may eventually reach the block hardware interface.

FW_OV_SHA3_START

Firmware override sha3 block start control register

• Offset: 0xb4
• Reset default: 0x9
• Reset mask: 0xf

Fields

{"reg": [{"name": "FW_OV_INSERT_START", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

FW_OV_SHA3_START . FW_OV_INSERT_START

Setting this field to kMultiBitBool4True will instruct the ENTROPY_SRC main state machine to start the SHA3 process and be ready to accept entropy data. This field should be set prior to writing the FW_OV_WR_DATA register. Once all data has been written, this field should be set to kMultiBitBool4False. Once that happened, the SHA3 block will finish processing and push the result into the esfinal FIFO.

Note that clearing this bit to kMultiBitBool4False while there is still unprocessed entropy in FW_OV_WR_DATA will start the SHA3 engine before data can be added to the input message, and will also signal a recoverable alert in RECOV_ALERT_STS.ES_FW_OV_DISABLE_ALERT. To avoid this, check that FW_OV_WR_FIFO_FULL is clear before setting this field to kMultiBitBool4False.

FW_OV_WR_FIFO_FULL

Firmware override FIFO write full status register

• Offset: 0xb8
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "FW_OV_WR_FIFO_FULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

FW_OV_RD_FIFO_OVERFLOW

Firmware override observe FIFO overflow status

• Offset: 0xbc
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "FW_OV_RD_FIFO_OVERFLOW", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}

FW_OV_RD_FIFO_OVERFLOW . FW_OV_RD_FIFO_OVERFLOW

This bit is set by hardware whenever RNG data is lost due to an overflow condition in the observe FIFO. The RNG data rate is slow enough that firmware should always be able to keep up. This register meanwhile provides an additional check to confirm that bytes read from the FW_OV_RD_DATA register represent contiguous RNG samples. If an overflow event occurs, this bit is cleared by hardware as soon as the FIFO is emptied.

FW_OV_RD_DATA

Firmware override observe FIFO read register

• Offset: 0xc0
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "FW_OV_RD_DATA", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

FW_OV_RD_DATA . FW_OV_RD_DATA

A read of this register pops and returns the top of the observe FIFO. For this to work, the FW_OV_CONTROL.FW_OV_MODE field needs to be set to kMultiBitBool4True In addition, the otp_en_entropy_src_fw_over input needs to be set to kMultiBitBool8True. Reading this register while the observe FIFO is empty results in a fatal error with ERR_CODE.FIFO_READ_ERR and ERR_CODE.SFIFO_OBSERVE_ERR going high.

FW_OV_WR_DATA

Firmware override FIFO write register

• Offset: 0xc4
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "FW_OV_WR_DATA", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

FW_OV_WR_DATA . FW_OV_WR_DATA

A write to this register will insert entropy back into the entropy source module flow. For this to work, both the FW_OV_CONTROL.FW_OV_MODE and FW_OV_CONTROL.FW_OV_ENTROPY_INSERT fields need to be set to kMultiBitBool4True. In addition, the otp_en_entropy_src_fw_over input needs to be set to kMultiBitBool8True.

OBSERVE_FIFO_THRESH

Observe FIFO threshold register

• Offset: 0xc8
• Reset default: 0x10
• Reset mask: 0x3f
• Register enable: REGWEN

Fields

{"reg": [{"name": "OBSERVE_FIFO_THRESH", "bits": 6, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}

OBSERVE_FIFO_DEPTH

Observe FIFO depth register

• Offset: 0xcc
• Reset default: 0x0
• Reset mask: 0x3f

Fields

{"reg": [{"name": "OBSERVE_FIFO_DEPTH", "bits": 6, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

DEBUG_STATUS

Debug status register

• Offset: 0xd0
• Reset default: 0x10000
• Reset mask: 0x303fb

Fields

{"reg": [{"name": "ENTROPY_FIFO_DEPTH", "bits": 2, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SHA3_FSM", "bits": 3, "attr": ["ro"], "rotate": -90}, {"name": "SHA3_BLOCK_PR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SHA3_SQUEEZING", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SHA3_ABSORBED", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SHA3_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 6}, {"name": "MAIN_SM_IDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_BOOT_DONE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 14}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

RECOV_ALERT_STS

Recoverable alert status register

• Offset: 0xd4
• Reset default: 0x0
• Reset mask: 0x8007ffaf

Fields

{"reg": [{"name": "FIPS_ENABLE_FIELD_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "ENTROPY_DATA_REG_EN_FIELD_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "MODULE_ENABLE_FIELD_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "THRESHOLD_SCOPE_FIELD_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 1}, {"name": "RNG_BIT_ENABLE_FIELD_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 1}, {"name": "FW_OV_SHA3_START_FIELD_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "FW_OV_MODE_FIELD_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "FW_OV_ENTROPY_INSERT_FIELD_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "ES_ROUTE_FIELD_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "ES_TYPE_FIELD_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "ES_MAIN_SM_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "ES_BUS_CMP_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "ES_THRESH_CFG_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "ES_FW_OV_WR_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "ES_FW_OV_DISABLE_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "FIPS_FLAG_FIELD_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "RNG_FIPS_FIELD_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 12}, {"name": "POSTHT_ENTROPY_DROP_ALERT", "bits": 1, "attr": ["rw0c"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 340}}

RECOV_ALERT_STS . POSTHT_ENTROPY_DROP_ALERT

This bit is set when post-health test entropy bits are being dropped from the hardware pipeline. The pipeline can drop individual symbols at the input of the postht FIFO (esbit FIFO when running in single-channel mode, see ENTROPY_SRC.RNG_BIT_ENABLE). Entropy bits might get dropped in these locations e.g. due to backpressure from the conditioner.

Note that the conditioner will still use the amount of bits configured in HEALTH_TEST_WINDOW.FIPS_WINDOW to produce the seed. The resulting seed is still okay to use. But as the dropped bits are still tested, the effective test window increases beyond the value configured in HEALTH_TEST_WINDOW.FIPS_WINDOW.

Software should check this bit when running in Firmware Override: Observe mode as dropping post-health test entropy bits in this mode may cause the entropy bits observed from the Observe FIFO to be non-contiguous.

Writing a zero resets this status bit.

RECOV_ALERT_STS . RNG_FIPS_FIELD_ALERT

This bit is set when the RNG_FIPS field in the CONF register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . FIPS_FLAG_FIELD_ALERT

This bit is set when the FIPS_FLAG field in the CONF register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . ES_FW_OV_DISABLE_ALERT

This bit is set when FW_OV_SHA3_START has been set to kMultiBitBool4False, without waiting for the bypass packer FIFO to clear. The final entropy entry in the FIFO will not be included in the SHA3 digest. (Rather it will be added to the subsequent SHA3 digest.) To avoid this alert, monitor FW_OV_WR_FIFO_FULL before clearing FW_OV_SHA3_START. This alert only applies when both FW_OV_CONTROL.FW_OV_MODE and FW_OV_CONTROL.FW_OV_ENTROPY_INSERT are set to kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . ES_FW_OV_WR_ALERT

This bit is set when the packer FIFO has been written but was full at the time, and in both FW_OV_MODE and FW_OV_ENTROPY_INSERT modes. This alert would normally be the result of not monitoring the FW_OV_WR_FIFO_FULL register before each write to the FW_OV_WR_DATA register. Writing a zero resets this status bit.

RECOV_ALERT_STS . ES_THRESH_CFG_ALERT

This bit is set when the ALERT_THRESHOLD register is not configured properly. The upper field must be the exact inverse of the lower field. Writing a zero resets this status bit.

RECOV_ALERT_STS . ES_BUS_CMP_ALERT

This bit is set when the interal entropy bus value is equal to the prior valid value on the bus, indicating a possible attack. Writing a zero resets this status bit.

RECOV_ALERT_STS . ES_MAIN_SM_ALERT

This bit is set when the main state machine detects a threshhold failure state. Writing a zero resets this status bit.

RECOV_ALERT_STS . ES_TYPE_FIELD_ALERT

This bit is set when the ES_TYPE field in the ENTROPY_CONTROL register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . ES_ROUTE_FIELD_ALERT

This bit is set when the ES_ROUTE field in the ENTROPY_CONTROL register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . FW_OV_ENTROPY_INSERT_FIELD_ALERT

This bit is set when the FW_OV_ENTROPY_INSERT field in the FW_OV_CONTROL register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . FW_OV_MODE_FIELD_ALERT

This bit is set when the FW_OV_MODE field in the FW_OV_CONTROL register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . FW_OV_SHA3_START_FIELD_ALERT

This bit is set when the FW_OV_SHA3_START field in the FW_OV_SHA3_START register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . RNG_BIT_ENABLE_FIELD_ALERT

This bit is set when the RNG_BIT_ENABLE field in the CONF register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . THRESHOLD_SCOPE_FIELD_ALERT

This bit is set when the THRESHOLD_SCOPE field in the CONF register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . MODULE_ENABLE_FIELD_ALERT

This bit is set when the MODULE_ENABLE field in the MODULE_ENABLE register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . ENTROPY_DATA_REG_EN_FIELD_ALERT

This bit is set when the ENTROPY_DATA_REG_ENABLE field in the CONF register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . FIPS_ENABLE_FIELD_ALERT

This bit is set when the FIPS_ENABLE field in the CONF register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

ERR_CODE

Hardware detection of error conditions status register

• Offset: 0xd8
• Reset default: 0x0
• Reset mask: 0x71f0000f

Fields

{"reg": [{"name": "SFIFO_ESRNG_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_DISTR_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_OBSERVE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_ESFINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 16}, {"name": "ES_ACK_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ES_MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ES_CNTR_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SHA3_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SHA3_RST_STORAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 3}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

ERR_CODE . FIFO_STATE_ERR

This bit will be set to one when any of the source bits (bits 0 through 3 of this register) are asserted as a result of an error pulse generated from any FIFO where either both the empty and full status bits are set or in case of error conditions inside the hardened counters. This bit will stay set until the next reset.

ERR_CODE . FIFO_READ_ERR

This bit will be set to one when any of the source bits (bits 0 through 3 of this register) are asserted as a result of an error pulse generated from any empty FIFO that has received a read pulse. This bit will stay set until the next reset.

ERR_CODE . FIFO_WRITE_ERR

This bit will be set to one when any of the source bits (bits 0 through 3 of this register) are asserted as a result of an error pulse generated from any full FIFO that has been received a write pulse. This bit will stay set until the next reset.

ERR_CODE . SHA3_RST_STORAGE_ERR

This bit will be set to one when a SHA3_RST_STORAGE_ERR signal being active has been detected. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . SHA3_STATE_ERR

This bit will be set to one when a SHA3 state error has been detected. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . ES_CNTR_ERR

This bit will be set to one when a hardened counter has detected an error condition. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . ES_MAIN_SM_ERR

This bit will be set to one when an illegal state has been detected for the ES main stage state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . ES_ACK_SM_ERR

This bit will be set to one when an illegal state has been detected for the ES ack stage state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . SFIFO_ESFINAL_ERR

This bit will be set to one when an error has been detected for the esfinal FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_OBSERVE_ERR

This bit will be set to one when an error has been detected for the observe FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_DISTR_ERR

This bit will be set to one when an error has been detected for the distribution FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_ESRNG_ERR

This bit will be set to one when an error has been detected for the esrng FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE_TEST

Test error conditions register

• Offset: 0xdc
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "ERR_CODE_TEST", "bits": 5, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

ERR_CODE_TEST . ERR_CODE_TEST

Setting this field will set the bit number for which an error will be forced in the hardware. This bit number is that same one found in the ERR_CODE register. The action of writing this register will force an error pulse. The sole purpose of this register is to test that any error properly propagates to either an interrupt or an alert.

MAIN_SM_STATE

Main state machine state debug register

• Offset: 0xe0
• Reset default: 0xf5
• Reset mask: 0x1ff

Fields

{"reg": [{"name": "MAIN_SM_STATE", "bits": 9, "attr": ["ro"], "rotate": 0}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}