- Verify all LC_CTRL IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- Verify TileLink device protocol compliance with an SVA based testbench
For detailed information on LC_CTRL design features, please see the LC_CTRL HWIP technical specification.
LC_CTRL testbench has been constructed based on the CIP testbench architecture.
Top level testbench is located at
hw/ip/lc_ctrl/dv/tb/tb.sv. It instantiates the LC_CTRL DUT module
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into
- Clock and reset interface
- TileLink host interface
- LC_CTRL IOs
- Interrupts (
- Alerts (
- Devmode (
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
[list compile time configurations, if any and what are they used for]
All common types and methods defined at the package level can be found in
LC_CTRL testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into LC_CTRL device.
jtag_riscv_agent is used to read and write LC_CTRL registers via the JTAG interface. It contains an embedded instance of [jtag_agent] ../../../dv/sv/jtag_agent/README.md which uses the jtag_if interface in the testbench.
push_pull_agent is used to emulate the Token and OTP programming interfaces.
The LC_CTRL RAL model is created with the
ralgen FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking
All test sequences reside in
lc_ctrl_base_vseq virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
- err_inj_cg: indicates what error conditions have been injected.
lc_ctrl_scoreboard is primarily used for end to end checking.
It creates the following analysis exports to retrieve the data monitored by corresponding interface agents:
- tl_[a_chan, d_chan, dir]_fifo_lc_ctrl_reg_block.analysis_export: TileLink CSR reads/writes.
- jtag_riscv_fifo.analysis_export: JTAG CSR reads/writes
- alert_fifo[fatal_bus_integ_error, fatal_prog_error, fatal_state_error].analysis_export: Alert traffic from DUT
- otp_prog_fifo.analysis_export: OTP program data from LC_CTRL and response to LC_CTRL.
- otp_token_fifo.analysis_export: OTP token data from LC_CTRL and response to LC_CTRL.
- TL CSR data is used to check against expected values predicted by the scoreboard. It also updates the UVM register model.
- JTAG CSR data is used to check against expected values predicted by the scoreboard. It also updates the UVM register model.
- Alert data is decoded and used to indicate an alert has occurred
- TLUL assertions: The
tlul_assertassertions to the IP to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/lc_ctrl/dv/lc_ctrl_sim_cfg.hjson -i lc_ctrl_smoke