Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module alert_handler has the following hardware interfaces defined

• Primary Clock: clk_i
• Other Clocks: clk_edn_i
• Bus Device Interfaces (TL-UL): tl
• Bus Host Interfaces (TL-UL): none
• Peripheral Pins for Chip IO: none
• Security Alerts: none

Inter-Module Signals

Interrupts

Security Countermeasures

Registers

Summary

INTR_STATE

Interrupt State Register

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0xf

Fields

{"reg": [{"name": "classa", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "classb", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "classc", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "classd", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_ENABLE

Interrupt Enable Register

• Offset: 0x4
• Reset default: 0x0
• Reset mask: 0xf

Fields

{"reg": [{"name": "classa", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "classb", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "classc", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "classd", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_TEST

Interrupt Test Register

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0xf

Fields

{"reg": [{"name": "classa", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "classb", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "classc", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "classd", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PING_TIMER_REGWEN

Register write enable for PING_TIMEOUT_CYC_SHADOWED and PING_TIMER_EN_SHADOWED.

• Offset: 0xc
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "PING_TIMER_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}

PING_TIMER_REGWEN . PING_TIMER_REGWEN

When true, the PING_TIMEOUT_CYC_SHADOWED and PING_TIMER_EN_SHADOWED registers can be modified. When false, they become read-only. Defaults true, write one to clear. This should be cleared once the alert handler has been configured and the ping timer mechanism has been kicked off.

PING_TIMEOUT_CYC_SHADOWED

Ping timeout cycle count.

• Offset: 0x10
• Reset default: 0x100
• Reset mask: 0xffff
• Register enable: PING_TIMER_REGWEN

Fields

{"reg": [{"name": "PING_TIMEOUT_CYC_SHADOWED", "bits": 16, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PING_TIMEOUT_CYC_SHADOWED . PING_TIMEOUT_CYC_SHADOWED

Timeout value in cycles. If an alert receiver or an escalation sender does not respond to a ping within this timeout window, a pingfail alert will be raised. It is recommended to set this value to the equivalent of 256 cycles of the slowest alert sender clock domain in the system (or greater).

PING_TIMER_EN_SHADOWED

Ping timer enable.

• Offset: 0x14
• Reset default: 0x0
• Reset mask: 0x1
• Register enable: PING_TIMER_REGWEN

Fields

{"reg": [{"name": "PING_TIMER_EN_SHADOWED", "bits": 1, "attr": ["rw1s"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}

ALERT_REGWEN

Register write enable for alert enable bits.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ALERT_REGWEN . EN

Alert configuration write enable bit. If this is cleared to 0, the corresponding ALERT_EN_SHADOWED and ALERT_CLASS_SHADOWED bits are not writable anymore.

Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.

ALERT_EN_SHADOWED

Enable register for alerts.

• Reset default: 0x0
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "EN_A", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ALERT_CLASS_SHADOWED

Class assignment of alerts.

• Reset default: 0x0
• Reset mask: 0x3

Instances

Fields

{"reg": [{"name": "CLASS_A", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}

ALERT_CLASS_SHADOWED . CLASS_A

Classification

ALERT_CAUSE

Alert Cause Register

• Reset default: 0x0
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "A", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

LOC_ALERT_REGWEN

Register write enable for alert enable bits.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

LOC_ALERT_REGWEN . EN

Alert configuration write enable bit. If this is cleared to 0, the corresponding LOC_ALERT_EN_SHADOWED and LOC_ALERT_CLASS_SHADOWED bits are not writable anymore.

Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.

LOC_ALERT_EN_SHADOWED

Enable register for the local alerts “alert pingfail” (0), “escalation pingfail” (1), “alert integfail” (2), “escalation integfail” (3), “bus integrity failure” (4), “shadow reg update error” (5) and “shadow reg storage error” (6).

• Reset default: 0x0
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "EN_LA", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

LOC_ALERT_CLASS_SHADOWED

Class assignment of the local alerts “alert pingfail” (0), “escalation pingfail” (1), “alert integfail” (2), “escalation integfail” (3), “bus integrity failure” (4), “shadow reg update error” (5) and “shadow reg storage error” (6).

• Reset default: 0x0
• Reset mask: 0x3

Instances

Fields

{"reg": [{"name": "CLASS_LA", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}

LOC_ALERT_CLASS_SHADOWED . CLASS_LA

Classification

LOC_ALERT_CAUSE

Alert Cause Register for the local alerts “alert pingfail” (0), “escalation pingfail” (1), “alert integfail” (2), “escalation integfail” (3), “bus integrity failure” (4), “shadow reg update error” (5) and “shadow reg storage error” (6).

• Reset default: 0x0
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "LA", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSA_REGWEN

Lock bit for Class A configuration.

• Offset: 0x498
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSA_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

CLASSA_CTRL_SHADOWED

Escalation control register for alert Class A. Can not be modified if CLASSA_REGWEN is false.

• Offset: 0x49c
• Reset default: 0x393c
• Reset mask: 0x3fff
• Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LOCK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E0", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E1", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E2", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E3", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 18}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSA_CLR_REGWEN

Clear enable for escalation protocol of Class A alerts.

• Offset: 0x4a0
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSA_CLR_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}

CLASSA_CLR_SHADOWED

Clear for escalation protocol of Class A.

• Offset: 0x4a4
• Reset default: 0x0
• Reset mask: 0x1
• Register enable: CLASSA_CLR_REGWEN

Fields

{"reg": [{"name": "CLASSA_CLR_SHADOWED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}

CLASSA_ACCUM_CNT

Current accumulation value for alert Class A. Software can clear this register with a write to CLASSA_CLR_SHADOWED register unless CLASSA_CLR_REGWEN is false.

• Offset: 0x4a8
• Reset default: 0x0
• Reset mask: 0xffff

Fields

{"reg": [{"name": "CLASSA_ACCUM_CNT", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSA_ACCUM_THRESH_SHADOWED

Accumulation threshold value for alert Class A.

• Offset: 0x4ac
• Reset default: 0x0
• Reset mask: 0xffff
• Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "CLASSA_ACCUM_THRESH_SHADOWED", "bits": 16, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSA_TIMEOUT_CYC_SHADOWED

Interrupt timeout in cycles.

• Offset: 0x4b0
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "CLASSA_TIMEOUT_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSA_TIMEOUT_CYC_SHADOWED . CLASSA_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class A. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSA_REGWEN is false.

CLASSA_CRASHDUMP_TRIGGER_SHADOWED

Crashdump trigger configuration for Class A.

• Offset: 0x4b4
• Reset default: 0x0
• Reset mask: 0x3
• Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "CLASSA_CRASHDUMP_TRIGGER_SHADOWED", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 350}}

CLASSA_CRASHDUMP_TRIGGER_SHADOWED . CLASSA_CRASHDUMP_TRIGGER_SHADOWED

Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation timer states. It is recommended to capture the crashdump upon entering the first escalation phase that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order to prevent spurious alert events from masking the original alert causes. Note that this register can not be modified if CLASSA_REGWEN is false.

CLASSA_PHASE0_CYC_SHADOWED

Duration of escalation phase 0 for Class A.

• Offset: 0x4b8
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "CLASSA_PHASE0_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSA_PHASE1_CYC_SHADOWED

Duration of escalation phase 1 for Class A.

• Offset: 0x4bc
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "CLASSA_PHASE1_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSA_PHASE2_CYC_SHADOWED

Duration of escalation phase 2 for Class A.

• Offset: 0x4c0
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "CLASSA_PHASE2_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSA_PHASE3_CYC_SHADOWED

Duration of escalation phase 3 for Class A.

• Offset: 0x4c4
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "CLASSA_PHASE3_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSA_ESC_CNT

Escalation counter in cycles for Class A.

• Offset: 0x4c8
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "CLASSA_ESC_CNT", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSA_ESC_CNT . CLASSA_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSA_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSA_CLR_SHADOWED. Note however that has no effect if CLASSA_REGWEN is set to false (either by SW or by HW via the CLASSA_CTRL_SHADOWED.LOCK feature).

CLASSA_STATE

Current escalation state of Class A. See also CLASSA_ESC_CNT.

• Offset: 0x4cc
• Reset default: 0x0
• Reset mask: 0x7

Fields

{"reg": [{"name": "CLASSA_STATE", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}}

CLASSA_STATE . CLASSA_STATE

CLASSB_REGWEN

Lock bit for Class B configuration.

• Offset: 0x4d0
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSB_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

CLASSB_CTRL_SHADOWED

Escalation control register for alert Class B. Can not be modified if CLASSB_REGWEN is false.

• Offset: 0x4d4
• Reset default: 0x393c
• Reset mask: 0x3fff
• Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LOCK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E0", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E1", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E2", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E3", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 18}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSB_CLR_REGWEN

Clear enable for escalation protocol of Class B alerts.

• Offset: 0x4d8
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSB_CLR_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}

CLASSB_CLR_SHADOWED

Clear for escalation protocol of Class B.

• Offset: 0x4dc
• Reset default: 0x0
• Reset mask: 0x1
• Register enable: CLASSB_CLR_REGWEN

Fields

{"reg": [{"name": "CLASSB_CLR_SHADOWED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}

CLASSB_ACCUM_CNT

Current accumulation value for alert Class B. Software can clear this register with a write to CLASSB_CLR_SHADOWED register unless CLASSB_CLR_REGWEN is false.

• Offset: 0x4e0
• Reset default: 0x0
• Reset mask: 0xffff

Fields

{"reg": [{"name": "CLASSB_ACCUM_CNT", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSB_ACCUM_THRESH_SHADOWED

Accumulation threshold value for alert Class B.

• Offset: 0x4e4
• Reset default: 0x0
• Reset mask: 0xffff
• Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "CLASSB_ACCUM_THRESH_SHADOWED", "bits": 16, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSB_TIMEOUT_CYC_SHADOWED

Interrupt timeout in cycles.

• Offset: 0x4e8
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "CLASSB_TIMEOUT_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSB_TIMEOUT_CYC_SHADOWED . CLASSB_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class B. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSB_REGWEN is false.

CLASSB_CRASHDUMP_TRIGGER_SHADOWED

Crashdump trigger configuration for Class B.

• Offset: 0x4ec
• Reset default: 0x0
• Reset mask: 0x3
• Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "CLASSB_CRASHDUMP_TRIGGER_SHADOWED", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 350}}

CLASSB_CRASHDUMP_TRIGGER_SHADOWED . CLASSB_CRASHDUMP_TRIGGER_SHADOWED

Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation timer states. It is recommended to capture the crashdump upon entering the first escalation phase that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order to prevent spurious alert events from masking the original alert causes. Note that this register can not be modified if CLASSB_REGWEN is false.

CLASSB_PHASE0_CYC_SHADOWED

Duration of escalation phase 0 for Class B.

• Offset: 0x4f0
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "CLASSB_PHASE0_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSB_PHASE1_CYC_SHADOWED

Duration of escalation phase 1 for Class B.

• Offset: 0x4f4
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "CLASSB_PHASE1_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSB_PHASE2_CYC_SHADOWED

Duration of escalation phase 2 for Class B.

• Offset: 0x4f8
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "CLASSB_PHASE2_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSB_PHASE3_CYC_SHADOWED

Duration of escalation phase 3 for Class B.

• Offset: 0x4fc
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "CLASSB_PHASE3_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSB_ESC_CNT

Escalation counter in cycles for Class B.

• Offset: 0x500
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "CLASSB_ESC_CNT", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSB_ESC_CNT . CLASSB_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSB_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSB_CLR_SHADOWED. Note however that has no effect if CLASSB_REGWEN is set to false (either by SW or by HW via the CLASSB_CTRL_SHADOWED.LOCK feature).

CLASSB_STATE

Current escalation state of Class B. See also CLASSB_ESC_CNT.

• Offset: 0x504
• Reset default: 0x0
• Reset mask: 0x7

Fields

{"reg": [{"name": "CLASSB_STATE", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}}

CLASSB_STATE . CLASSB_STATE

CLASSC_REGWEN

Lock bit for Class C configuration.

• Offset: 0x508
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSC_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

CLASSC_CTRL_SHADOWED

Escalation control register for alert Class C. Can not be modified if CLASSC_REGWEN is false.

• Offset: 0x50c
• Reset default: 0x393c
• Reset mask: 0x3fff
• Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LOCK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E0", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E1", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E2", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E3", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 18}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSC_CLR_REGWEN

Clear enable for escalation protocol of Class C alerts.

• Offset: 0x510
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSC_CLR_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}

CLASSC_CLR_SHADOWED

Clear for escalation protocol of Class C.

• Offset: 0x514
• Reset default: 0x0
• Reset mask: 0x1
• Register enable: CLASSC_CLR_REGWEN

Fields

{"reg": [{"name": "CLASSC_CLR_SHADOWED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}

CLASSC_ACCUM_CNT

Current accumulation value for alert Class C. Software can clear this register with a write to CLASSC_CLR_SHADOWED register unless CLASSC_CLR_REGWEN is false.

• Offset: 0x518
• Reset default: 0x0
• Reset mask: 0xffff

Fields

{"reg": [{"name": "CLASSC_ACCUM_CNT", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSC_ACCUM_THRESH_SHADOWED

Accumulation threshold value for alert Class C.

• Offset: 0x51c
• Reset default: 0x0
• Reset mask: 0xffff
• Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "CLASSC_ACCUM_THRESH_SHADOWED", "bits": 16, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSC_TIMEOUT_CYC_SHADOWED

Interrupt timeout in cycles.

• Offset: 0x520
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "CLASSC_TIMEOUT_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSC_TIMEOUT_CYC_SHADOWED . CLASSC_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class C. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSC_REGWEN is false.

CLASSC_CRASHDUMP_TRIGGER_SHADOWED

Crashdump trigger configuration for Class C.

• Offset: 0x524
• Reset default: 0x0
• Reset mask: 0x3
• Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "CLASSC_CRASHDUMP_TRIGGER_SHADOWED", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 350}}

CLASSC_CRASHDUMP_TRIGGER_SHADOWED . CLASSC_CRASHDUMP_TRIGGER_SHADOWED

Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation timer states. It is recommended to capture the crashdump upon entering the first escalation phase that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order to prevent spurious alert events from masking the original alert causes. Note that this register can not be modified if CLASSC_REGWEN is false.

CLASSC_PHASE0_CYC_SHADOWED

Duration of escalation phase 0 for Class C.

• Offset: 0x528
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "CLASSC_PHASE0_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSC_PHASE1_CYC_SHADOWED

Duration of escalation phase 1 for Class C.

• Offset: 0x52c
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "CLASSC_PHASE1_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSC_PHASE2_CYC_SHADOWED

Duration of escalation phase 2 for Class C.

• Offset: 0x530
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "CLASSC_PHASE2_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSC_PHASE3_CYC_SHADOWED

Duration of escalation phase 3 for Class C.

• Offset: 0x534
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "CLASSC_PHASE3_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSC_ESC_CNT

Escalation counter in cycles for Class C.

• Offset: 0x538
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "CLASSC_ESC_CNT", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSC_ESC_CNT . CLASSC_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSC_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSC_CLR_SHADOWED. Note however that has no effect if CLASSC_REGWEN is set to false (either by SW or by HW via the CLASSC_CTRL_SHADOWED.LOCK feature).

CLASSC_STATE

Current escalation state of Class C. See also CLASSC_ESC_CNT.

• Offset: 0x53c
• Reset default: 0x0
• Reset mask: 0x7

Fields

{"reg": [{"name": "CLASSC_STATE", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}}

CLASSC_STATE . CLASSC_STATE

CLASSD_REGWEN

Lock bit for Class D configuration.

• Offset: 0x540
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSD_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

CLASSD_CTRL_SHADOWED

Escalation control register for alert Class D. Can not be modified if CLASSD_REGWEN is false.

• Offset: 0x544
• Reset default: 0x393c
• Reset mask: 0x3fff
• Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LOCK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E0", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E1", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E2", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E3", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 18}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSD_CLR_REGWEN

Clear enable for escalation protocol of Class D alerts.

• Offset: 0x548
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSD_CLR_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}

CLASSD_CLR_SHADOWED

Clear for escalation protocol of Class D.

• Offset: 0x54c
• Reset default: 0x0
• Reset mask: 0x1
• Register enable: CLASSD_CLR_REGWEN

Fields

{"reg": [{"name": "CLASSD_CLR_SHADOWED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}

CLASSD_ACCUM_CNT

Current accumulation value for alert Class D. Software can clear this register with a write to CLASSD_CLR_SHADOWED register unless CLASSD_CLR_REGWEN is false.

• Offset: 0x550
• Reset default: 0x0
• Reset mask: 0xffff

Fields

{"reg": [{"name": "CLASSD_ACCUM_CNT", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSD_ACCUM_THRESH_SHADOWED

Accumulation threshold value for alert Class D.

• Offset: 0x554
• Reset default: 0x0
• Reset mask: 0xffff
• Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "CLASSD_ACCUM_THRESH_SHADOWED", "bits": 16, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSD_TIMEOUT_CYC_SHADOWED

Interrupt timeout in cycles.

• Offset: 0x558
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "CLASSD_TIMEOUT_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSD_TIMEOUT_CYC_SHADOWED . CLASSD_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class D. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSD_REGWEN is false.

CLASSD_CRASHDUMP_TRIGGER_SHADOWED

Crashdump trigger configuration for Class D.

• Offset: 0x55c
• Reset default: 0x0
• Reset mask: 0x3
• Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "CLASSD_CRASHDUMP_TRIGGER_SHADOWED", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 350}}

CLASSD_CRASHDUMP_TRIGGER_SHADOWED . CLASSD_CRASHDUMP_TRIGGER_SHADOWED

Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation timer states. It is recommended to capture the crashdump upon entering the first escalation phase that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order to prevent spurious alert events from masking the original alert causes. Note that this register can not be modified if CLASSD_REGWEN is false.

CLASSD_PHASE0_CYC_SHADOWED

Duration of escalation phase 0 for Class D.

• Offset: 0x560
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "CLASSD_PHASE0_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSD_PHASE1_CYC_SHADOWED

Duration of escalation phase 1 for Class D.

• Offset: 0x564
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "CLASSD_PHASE1_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSD_PHASE2_CYC_SHADOWED

Duration of escalation phase 2 for Class D.

• Offset: 0x568
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "CLASSD_PHASE2_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSD_PHASE3_CYC_SHADOWED

Duration of escalation phase 3 for Class D.

• Offset: 0x56c
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "CLASSD_PHASE3_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSD_ESC_CNT

Escalation counter in cycles for Class D.

• Offset: 0x570
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "CLASSD_ESC_CNT", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLASSD_ESC_CNT . CLASSD_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSD_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSD_CLR_SHADOWED. Note however that has no effect if CLASSD_REGWEN is set to false (either by SW or by HW via the CLASSD_CTRL_SHADOWED.LOCK feature).

CLASSD_STATE

Current escalation state of Class D. See also CLASSD_ESC_CNT.

• Offset: 0x574
• Reset default: 0x0
• Reset mask: 0x7

Fields

{"reg": [{"name": "CLASSD_STATE", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}}

CLASSD_STATE . CLASSD_STATE