Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module alert_handler has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_edn_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
crashdump alert_pkg::alert_crashdump uni req 1
edn edn_pkg::edn req_rsp req 1
esc_rx prim_esc_pkg::esc_rx uni rcv 4
esc_tx prim_esc_pkg::esc_tx uni req 4
tl tlul_pkg::tl req_rsp rsp 1

Interrupts:

Interrupt NameTypeDescription
classaEvent

Interrupt state bit of Class A. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.

classbEvent

Interrupt state bit of Class B. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.

classcEvent

Interrupt state bit of Class C. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.

classdEvent

Interrupt state bit of Class D. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.

Security Alerts: none

Security Countermeasures:

Countermeasure IDDescription
ALERT_HANDLER.BUS.INTEGRITY

End-to-end bus integrity scheme.

ALERT_HANDLER.CONFIG.SHADOW

Important CSRs are shadowed.

ALERT_HANDLER.PING_TIMER.CONFIG.REGWEN

The ping timer configuration registers are REGWEN protected.

ALERT_HANDLER.ALERT.CONFIG.REGWEN

The individual alert enables are REGWEN protected.

ALERT_HANDLER.ALERT_LOC.CONFIG.REGWEN

The individual local alert enables are REGWEN protected.

ALERT_HANDLER.CLASS.CONFIG.REGWEN

The class configuration registers are REGWEN protected.

ALERT_HANDLER.ALERT.INTERSIG.DIFF

Differentially encoded alert channels.

ALERT_HANDLER.LPG.INTERSIG.MUBI

LPG signals are encoded with MUBI types.

ALERT_HANDLER.ESC.INTERSIG.DIFF

Differentially encoded escalation channels.

ALERT_HANDLER.ALERT_RX.INTERSIG.BKGN_CHK

Periodic background checks on alert channels (ping mechanism).

ALERT_HANDLER.ESC_TX.INTERSIG.BKGN_CHK

Periodic background checks on escalation channels (ping mechanism).

ALERT_HANDLER.ESC_RX.INTERSIG.BKGN_CHK

Escalation receivers can detect absence of periodic ping requests.

ALERT_HANDLER.ESC_TIMER.FSM.SPARSE

Escalation timer FSMs are sparsely encoded.

ALERT_HANDLER.PING_TIMER.FSM.SPARSE

Ping timer FSM is sparsely encoded.

ALERT_HANDLER.ESC_TIMER.FSM.LOCAL_ESC

Escalation timer FSMs move into an invalid state upon local escalation.

ALERT_HANDLER.PING_TIMER.FSM.LOCAL_ESC

Ping timer FSM moves into an invalid state upon local escalation.

ALERT_HANDLER.ESC_TIMER.FSM.GLOBAL_ESC

The escalation timer FSMs are the root of global escalation, hence if any of them moves into an invalid state by virtue of ESC_TIMER.FSM.LOCAL_ESC, this will trigger all escalation actions and thereby global escalation as well.

ALERT_HANDLER.ACCU.CTR.REDUN

Accumulator counters employ a cross-counter implementation.

ALERT_HANDLER.ESC_TIMER.CTR.REDUN

Escalation timer counters employ a duplicated counter implementation.

ALERT_HANDLER.PING_TIMER.CTR.REDUN

Ping timer counters employ a duplicated counter implementation.

ALERT_HANDLER.PING_TIMER.LFSR.REDUN

Ping timer LFSR is redundant.

Registers

Summary
Name Offset Length Description
alert_handler.INTR_STATE 0x0 4

Interrupt State Register

alert_handler.INTR_ENABLE 0x4 4

Interrupt Enable Register

alert_handler.INTR_TEST 0x8 4

Interrupt Test Register

alert_handler.PING_TIMER_REGWEN 0xc 4

Register write enable for PING_TIMEOUT_CYC_SHADOWED and PING_TIMER_EN_SHADOWED.

alert_handler.PING_TIMEOUT_CYC_SHADOWED 0x10 4

Ping timeout cycle count.

alert_handler.PING_TIMER_EN_SHADOWED 0x14 4

Ping timer enable.

alert_handler.ALERT_REGWEN_0 0x18 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_1 0x1c 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_2 0x20 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_3 0x24 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_4 0x28 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_5 0x2c 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_6 0x30 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_7 0x34 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_8 0x38 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_9 0x3c 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_10 0x40 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_11 0x44 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_12 0x48 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_13 0x4c 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_14 0x50 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_15 0x54 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_16 0x58 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_17 0x5c 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_18 0x60 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_19 0x64 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_20 0x68 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_21 0x6c 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_22 0x70 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_23 0x74 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_24 0x78 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_25 0x7c 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_26 0x80 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_27 0x84 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_28 0x88 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_29 0x8c 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_30 0x90 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_31 0x94 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_32 0x98 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_33 0x9c 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_34 0xa0 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_35 0xa4 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_36 0xa8 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_37 0xac 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_38 0xb0 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_39 0xb4 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_40 0xb8 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_41 0xbc 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_42 0xc0 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_43 0xc4 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_44 0xc8 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_45 0xcc 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_46 0xd0 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_47 0xd4 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_48 0xd8 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_49 0xdc 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_50 0xe0 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_51 0xe4 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_52 0xe8 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_53 0xec 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_54 0xf0 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_55 0xf4 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_56 0xf8 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_57 0xfc 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_58 0x100 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_59 0x104 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_60 0x108 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_61 0x10c 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_62 0x110 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_63 0x114 4

Register write enable for alert enable bits.

alert_handler.ALERT_REGWEN_64 0x118 4

Register write enable for alert enable bits.

alert_handler.ALERT_EN_SHADOWED_0 0x11c 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_1 0x120 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_2 0x124 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_3 0x128 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_4 0x12c 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_5 0x130 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_6 0x134 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_7 0x138 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_8 0x13c 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_9 0x140 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_10 0x144 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_11 0x148 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_12 0x14c 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_13 0x150 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_14 0x154 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_15 0x158 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_16 0x15c 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_17 0x160 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_18 0x164 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_19 0x168 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_20 0x16c 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_21 0x170 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_22 0x174 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_23 0x178 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_24 0x17c 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_25 0x180 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_26 0x184 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_27 0x188 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_28 0x18c 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_29 0x190 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_30 0x194 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_31 0x198 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_32 0x19c 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_33 0x1a0 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_34 0x1a4 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_35 0x1a8 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_36 0x1ac 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_37 0x1b0 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_38 0x1b4 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_39 0x1b8 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_40 0x1bc 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_41 0x1c0 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_42 0x1c4 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_43 0x1c8 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_44 0x1cc 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_45 0x1d0 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_46 0x1d4 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_47 0x1d8 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_48 0x1dc 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_49 0x1e0 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_50 0x1e4 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_51 0x1e8 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_52 0x1ec 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_53 0x1f0 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_54 0x1f4 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_55 0x1f8 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_56 0x1fc 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_57 0x200 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_58 0x204 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_59 0x208 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_60 0x20c 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_61 0x210 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_62 0x214 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_63 0x218 4

Enable register for alerts.

alert_handler.ALERT_EN_SHADOWED_64 0x21c 4

Enable register for alerts.

alert_handler.ALERT_CLASS_SHADOWED_0 0x220 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_1 0x224 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_2 0x228 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_3 0x22c 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_4 0x230 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_5 0x234 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_6 0x238 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_7 0x23c 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_8 0x240 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_9 0x244 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_10 0x248 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_11 0x24c 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_12 0x250 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_13 0x254 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_14 0x258 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_15 0x25c 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_16 0x260 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_17 0x264 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_18 0x268 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_19 0x26c 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_20 0x270 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_21 0x274 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_22 0x278 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_23 0x27c 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_24 0x280 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_25 0x284 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_26 0x288 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_27 0x28c 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_28 0x290 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_29 0x294 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_30 0x298 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_31 0x29c 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_32 0x2a0 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_33 0x2a4 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_34 0x2a8 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_35 0x2ac 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_36 0x2b0 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_37 0x2b4 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_38 0x2b8 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_39 0x2bc 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_40 0x2c0 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_41 0x2c4 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_42 0x2c8 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_43 0x2cc 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_44 0x2d0 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_45 0x2d4 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_46 0x2d8 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_47 0x2dc 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_48 0x2e0 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_49 0x2e4 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_50 0x2e8 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_51 0x2ec 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_52 0x2f0 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_53 0x2f4 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_54 0x2f8 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_55 0x2fc 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_56 0x300 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_57 0x304 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_58 0x308 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_59 0x30c 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_60 0x310 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_61 0x314 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_62 0x318 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_63 0x31c 4

Class assignment of alerts.

alert_handler.ALERT_CLASS_SHADOWED_64 0x320 4

Class assignment of alerts.

alert_handler.ALERT_CAUSE_0 0x324 4

Alert Cause Register

alert_handler.ALERT_CAUSE_1 0x328 4

Alert Cause Register

alert_handler.ALERT_CAUSE_2 0x32c 4

Alert Cause Register

alert_handler.ALERT_CAUSE_3 0x330 4

Alert Cause Register

alert_handler.ALERT_CAUSE_4 0x334 4

Alert Cause Register

alert_handler.ALERT_CAUSE_5 0x338 4

Alert Cause Register

alert_handler.ALERT_CAUSE_6 0x33c 4

Alert Cause Register

alert_handler.ALERT_CAUSE_7 0x340 4

Alert Cause Register

alert_handler.ALERT_CAUSE_8 0x344 4

Alert Cause Register

alert_handler.ALERT_CAUSE_9 0x348 4

Alert Cause Register

alert_handler.ALERT_CAUSE_10 0x34c 4

Alert Cause Register

alert_handler.ALERT_CAUSE_11 0x350 4

Alert Cause Register

alert_handler.ALERT_CAUSE_12 0x354 4

Alert Cause Register

alert_handler.ALERT_CAUSE_13 0x358 4

Alert Cause Register

alert_handler.ALERT_CAUSE_14 0x35c 4

Alert Cause Register

alert_handler.ALERT_CAUSE_15 0x360 4

Alert Cause Register

alert_handler.ALERT_CAUSE_16 0x364 4

Alert Cause Register

alert_handler.ALERT_CAUSE_17 0x368 4

Alert Cause Register

alert_handler.ALERT_CAUSE_18 0x36c 4

Alert Cause Register

alert_handler.ALERT_CAUSE_19 0x370 4

Alert Cause Register

alert_handler.ALERT_CAUSE_20 0x374 4

Alert Cause Register

alert_handler.ALERT_CAUSE_21 0x378 4

Alert Cause Register

alert_handler.ALERT_CAUSE_22 0x37c 4

Alert Cause Register

alert_handler.ALERT_CAUSE_23 0x380 4

Alert Cause Register

alert_handler.ALERT_CAUSE_24 0x384 4

Alert Cause Register

alert_handler.ALERT_CAUSE_25 0x388 4

Alert Cause Register

alert_handler.ALERT_CAUSE_26 0x38c 4

Alert Cause Register

alert_handler.ALERT_CAUSE_27 0x390 4

Alert Cause Register

alert_handler.ALERT_CAUSE_28 0x394 4

Alert Cause Register

alert_handler.ALERT_CAUSE_29 0x398 4

Alert Cause Register

alert_handler.ALERT_CAUSE_30 0x39c 4

Alert Cause Register

alert_handler.ALERT_CAUSE_31 0x3a0 4

Alert Cause Register

alert_handler.ALERT_CAUSE_32 0x3a4 4

Alert Cause Register

alert_handler.ALERT_CAUSE_33 0x3a8 4

Alert Cause Register

alert_handler.ALERT_CAUSE_34 0x3ac 4

Alert Cause Register

alert_handler.ALERT_CAUSE_35 0x3b0 4

Alert Cause Register

alert_handler.ALERT_CAUSE_36 0x3b4 4

Alert Cause Register

alert_handler.ALERT_CAUSE_37 0x3b8 4

Alert Cause Register

alert_handler.ALERT_CAUSE_38 0x3bc 4

Alert Cause Register

alert_handler.ALERT_CAUSE_39 0x3c0 4

Alert Cause Register

alert_handler.ALERT_CAUSE_40 0x3c4 4

Alert Cause Register

alert_handler.ALERT_CAUSE_41 0x3c8 4

Alert Cause Register

alert_handler.ALERT_CAUSE_42 0x3cc 4

Alert Cause Register

alert_handler.ALERT_CAUSE_43 0x3d0 4

Alert Cause Register

alert_handler.ALERT_CAUSE_44 0x3d4 4

Alert Cause Register

alert_handler.ALERT_CAUSE_45 0x3d8 4

Alert Cause Register

alert_handler.ALERT_CAUSE_46 0x3dc 4

Alert Cause Register

alert_handler.ALERT_CAUSE_47 0x3e0 4

Alert Cause Register

alert_handler.ALERT_CAUSE_48 0x3e4 4

Alert Cause Register

alert_handler.ALERT_CAUSE_49 0x3e8 4

Alert Cause Register

alert_handler.ALERT_CAUSE_50 0x3ec 4

Alert Cause Register

alert_handler.ALERT_CAUSE_51 0x3f0 4

Alert Cause Register

alert_handler.ALERT_CAUSE_52 0x3f4 4

Alert Cause Register

alert_handler.ALERT_CAUSE_53 0x3f8 4

Alert Cause Register

alert_handler.ALERT_CAUSE_54 0x3fc 4

Alert Cause Register

alert_handler.ALERT_CAUSE_55 0x400 4

Alert Cause Register

alert_handler.ALERT_CAUSE_56 0x404 4

Alert Cause Register

alert_handler.ALERT_CAUSE_57 0x408 4

Alert Cause Register

alert_handler.ALERT_CAUSE_58 0x40c 4

Alert Cause Register

alert_handler.ALERT_CAUSE_59 0x410 4

Alert Cause Register

alert_handler.ALERT_CAUSE_60 0x414 4

Alert Cause Register

alert_handler.ALERT_CAUSE_61 0x418 4

Alert Cause Register

alert_handler.ALERT_CAUSE_62 0x41c 4

Alert Cause Register

alert_handler.ALERT_CAUSE_63 0x420 4

Alert Cause Register

alert_handler.ALERT_CAUSE_64 0x424 4

Alert Cause Register

alert_handler.LOC_ALERT_REGWEN_0 0x428 4

Register write enable for alert enable bits.

alert_handler.LOC_ALERT_REGWEN_1 0x42c 4

Register write enable for alert enable bits.

alert_handler.LOC_ALERT_REGWEN_2 0x430 4

Register write enable for alert enable bits.

alert_handler.LOC_ALERT_REGWEN_3 0x434 4

Register write enable for alert enable bits.

alert_handler.LOC_ALERT_REGWEN_4 0x438 4

Register write enable for alert enable bits.

alert_handler.LOC_ALERT_REGWEN_5 0x43c 4

Register write enable for alert enable bits.

alert_handler.LOC_ALERT_REGWEN_6 0x440 4

Register write enable for alert enable bits.

alert_handler.LOC_ALERT_EN_SHADOWED_0 0x444 4

Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_EN_SHADOWED_1 0x448 4

Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_EN_SHADOWED_2 0x44c 4

Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_EN_SHADOWED_3 0x450 4

Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_EN_SHADOWED_4 0x454 4

Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_EN_SHADOWED_5 0x458 4

Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_EN_SHADOWED_6 0x45c 4

Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_CLASS_SHADOWED_0 0x460 4

Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_CLASS_SHADOWED_1 0x464 4

Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_CLASS_SHADOWED_2 0x468 4

Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_CLASS_SHADOWED_3 0x46c 4

Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_CLASS_SHADOWED_4 0x470 4

Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_CLASS_SHADOWED_5 0x474 4

Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_CLASS_SHADOWED_6 0x478 4

Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_CAUSE_0 0x47c 4

Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_CAUSE_1 0x480 4

Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_CAUSE_2 0x484 4

Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_CAUSE_3 0x488 4

Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_CAUSE_4 0x48c 4

Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_CAUSE_5 0x490 4

Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.LOC_ALERT_CAUSE_6 0x494 4

Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

alert_handler.CLASSA_REGWEN 0x498 4

Lock bit for Class A configuration.

alert_handler.CLASSA_CTRL_SHADOWED 0x49c 4

Escalation control register for alert Class A. Can not be modified if CLASSA_REGWEN is false.

alert_handler.CLASSA_CLR_REGWEN 0x4a0 4

Clear enable for escalation protocol of Class A alerts.

alert_handler.CLASSA_CLR_SHADOWED 0x4a4 4

Clear for escalation protocol of Class A.

alert_handler.CLASSA_ACCUM_CNT 0x4a8 4

Current accumulation value for alert Class A. Software can clear this register with a write to CLASSA_CLR_SHADOWED register unless CLASSA_CLR_REGWEN is false.

alert_handler.CLASSA_ACCUM_THRESH_SHADOWED 0x4ac 4

Accumulation threshold value for alert Class A.

alert_handler.CLASSA_TIMEOUT_CYC_SHADOWED 0x4b0 4

Interrupt timeout in cycles.

alert_handler.CLASSA_CRASHDUMP_TRIGGER_SHADOWED 0x4b4 4

Crashdump trigger configuration for Class A.

alert_handler.CLASSA_PHASE0_CYC_SHADOWED 0x4b8 4

Duration of escalation phase 0 for Class A.

alert_handler.CLASSA_PHASE1_CYC_SHADOWED 0x4bc 4

Duration of escalation phase 1 for Class A.

alert_handler.CLASSA_PHASE2_CYC_SHADOWED 0x4c0 4

Duration of escalation phase 2 for Class A.

alert_handler.CLASSA_PHASE3_CYC_SHADOWED 0x4c4 4

Duration of escalation phase 3 for Class A.

alert_handler.CLASSA_ESC_CNT 0x4c8 4

Escalation counter in cycles for Class A.

alert_handler.CLASSA_STATE 0x4cc 4

Current escalation state of Class A. See also CLASSA_ESC_CNT.

alert_handler.CLASSB_REGWEN 0x4d0 4

Lock bit for Class B configuration.

alert_handler.CLASSB_CTRL_SHADOWED 0x4d4 4

Escalation control register for alert Class B. Can not be modified if CLASSB_REGWEN is false.

alert_handler.CLASSB_CLR_REGWEN 0x4d8 4

Clear enable for escalation protocol of Class B alerts.

alert_handler.CLASSB_CLR_SHADOWED 0x4dc 4

Clear for escalation protocol of Class B.

alert_handler.CLASSB_ACCUM_CNT 0x4e0 4

Current accumulation value for alert Class B. Software can clear this register with a write to CLASSB_CLR_SHADOWED register unless CLASSB_CLR_REGWEN is false.

alert_handler.CLASSB_ACCUM_THRESH_SHADOWED 0x4e4 4

Accumulation threshold value for alert Class B.

alert_handler.CLASSB_TIMEOUT_CYC_SHADOWED 0x4e8 4

Interrupt timeout in cycles.

alert_handler.CLASSB_CRASHDUMP_TRIGGER_SHADOWED 0x4ec 4

Crashdump trigger configuration for Class B.

alert_handler.CLASSB_PHASE0_CYC_SHADOWED 0x4f0 4

Duration of escalation phase 0 for Class B.

alert_handler.CLASSB_PHASE1_CYC_SHADOWED 0x4f4 4

Duration of escalation phase 1 for Class B.

alert_handler.CLASSB_PHASE2_CYC_SHADOWED 0x4f8 4

Duration of escalation phase 2 for Class B.

alert_handler.CLASSB_PHASE3_CYC_SHADOWED 0x4fc 4

Duration of escalation phase 3 for Class B.

alert_handler.CLASSB_ESC_CNT 0x500 4

Escalation counter in cycles for Class B.

alert_handler.CLASSB_STATE 0x504 4

Current escalation state of Class B. See also CLASSB_ESC_CNT.

alert_handler.CLASSC_REGWEN 0x508 4

Lock bit for Class C configuration.

alert_handler.CLASSC_CTRL_SHADOWED 0x50c 4

Escalation control register for alert Class C. Can not be modified if CLASSC_REGWEN is false.

alert_handler.CLASSC_CLR_REGWEN 0x510 4

Clear enable for escalation protocol of Class C alerts.

alert_handler.CLASSC_CLR_SHADOWED 0x514 4

Clear for escalation protocol of Class C.

alert_handler.CLASSC_ACCUM_CNT 0x518 4

Current accumulation value for alert Class C. Software can clear this register with a write to CLASSC_CLR_SHADOWED register unless CLASSC_CLR_REGWEN is false.

alert_handler.CLASSC_ACCUM_THRESH_SHADOWED 0x51c 4

Accumulation threshold value for alert Class C.

alert_handler.CLASSC_TIMEOUT_CYC_SHADOWED 0x520 4

Interrupt timeout in cycles.

alert_handler.CLASSC_CRASHDUMP_TRIGGER_SHADOWED 0x524 4

Crashdump trigger configuration for Class C.

alert_handler.CLASSC_PHASE0_CYC_SHADOWED 0x528 4

Duration of escalation phase 0 for Class C.

alert_handler.CLASSC_PHASE1_CYC_SHADOWED 0x52c 4

Duration of escalation phase 1 for Class C.

alert_handler.CLASSC_PHASE2_CYC_SHADOWED 0x530 4

Duration of escalation phase 2 for Class C.

alert_handler.CLASSC_PHASE3_CYC_SHADOWED 0x534 4

Duration of escalation phase 3 for Class C.

alert_handler.CLASSC_ESC_CNT 0x538 4

Escalation counter in cycles for Class C.

alert_handler.CLASSC_STATE 0x53c 4

Current escalation state of Class C. See also CLASSC_ESC_CNT.

alert_handler.CLASSD_REGWEN 0x540 4

Lock bit for Class D configuration.

alert_handler.CLASSD_CTRL_SHADOWED 0x544 4

Escalation control register for alert Class D. Can not be modified if CLASSD_REGWEN is false.

alert_handler.CLASSD_CLR_REGWEN 0x548 4

Clear enable for escalation protocol of Class D alerts.

alert_handler.CLASSD_CLR_SHADOWED 0x54c 4

Clear for escalation protocol of Class D.

alert_handler.CLASSD_ACCUM_CNT 0x550 4

Current accumulation value for alert Class D. Software can clear this register with a write to CLASSD_CLR_SHADOWED register unless CLASSD_CLR_REGWEN is false.

alert_handler.CLASSD_ACCUM_THRESH_SHADOWED 0x554 4

Accumulation threshold value for alert Class D.

alert_handler.CLASSD_TIMEOUT_CYC_SHADOWED 0x558 4

Interrupt timeout in cycles.

alert_handler.CLASSD_CRASHDUMP_TRIGGER_SHADOWED 0x55c 4

Crashdump trigger configuration for Class D.

alert_handler.CLASSD_PHASE0_CYC_SHADOWED 0x560 4

Duration of escalation phase 0 for Class D.

alert_handler.CLASSD_PHASE1_CYC_SHADOWED 0x564 4

Duration of escalation phase 1 for Class D.

alert_handler.CLASSD_PHASE2_CYC_SHADOWED 0x568 4

Duration of escalation phase 2 for Class D.

alert_handler.CLASSD_PHASE3_CYC_SHADOWED 0x56c 4

Duration of escalation phase 3 for Class D.

alert_handler.CLASSD_ESC_CNT 0x570 4

Escalation counter in cycles for Class D.

alert_handler.CLASSD_STATE 0x574 4

Current escalation state of Class D. See also CLASSD_ESC_CNT.

alert_handler.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0xf
31302928272625242322212019181716
 
1514131211109876543210
  classd classc classb classa
BitsTypeResetNameDescription
0rw1c0x0classa

Interrupt state bit of Class A. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.

1rw1c0x0classb

Interrupt state bit of Class B. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.

2rw1c0x0classc

Interrupt state bit of Class C. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.

3rw1c0x0classd

Interrupt state bit of Class D. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.


alert_handler.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0xf
31302928272625242322212019181716
 
1514131211109876543210
  classd classc classb classa
BitsTypeResetNameDescription
0rw0x0classa

Enable interrupt when INTR_STATE.classa is set.

1rw0x0classb

Enable interrupt when INTR_STATE.classb is set.

2rw0x0classc

Enable interrupt when INTR_STATE.classc is set.

3rw0x0classd

Enable interrupt when INTR_STATE.classd is set.


alert_handler.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0xf
31302928272625242322212019181716
 
1514131211109876543210
  classd classc classb classa
BitsTypeResetNameDescription
0wo0x0classa

Write 1 to force INTR_STATE.classa to 1.

1wo0x0classb

Write 1 to force INTR_STATE.classb to 1.

2wo0x0classc

Write 1 to force INTR_STATE.classc to 1.

3wo0x0classd

Write 1 to force INTR_STATE.classd to 1.


alert_handler.PING_TIMER_REGWEN @ 0xc

Register write enable for PING_TIMEOUT_CYC_SHADOWED and PING_TIMER_EN_SHADOWED.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  PING_TIMER_REGWEN
BitsTypeResetNameDescription
0rw0c0x1PING_TIMER_REGWEN

When true, the PING_TIMEOUT_CYC_SHADOWED and PING_TIMER_EN_SHADOWED registers can be modified. When false, they become read-only. Defaults true, write one to clear. This should be cleared once the alert handler has been configured and the ping timer mechanism has been kicked off.


alert_handler.PING_TIMEOUT_CYC_SHADOWED @ 0x10

Ping timeout cycle count.

Reset default = 0x100, mask 0xffff
Register enable = PING_TIMER_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
PING_TIMEOUT_CYC_SHADOWED
BitsTypeResetNameDescription
15:0rw0x100PING_TIMEOUT_CYC_SHADOWED

Timeout value in cycles. If an alert receiver or an escalation sender does not respond to a ping within this timeout window, a pingfail alert will be raised. It is recommended to set this value to the equivalent of 256 cycles of the slowest alert sender clock domain in the system (or greater).


alert_handler.PING_TIMER_EN_SHADOWED @ 0x14

Ping timer enable.

Reset default = 0x0, mask 0x1
Register enable = PING_TIMER_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  PING_TIMER_EN_SHADOWED
BitsTypeResetNameDescription
0rw1s0x0PING_TIMER_EN_SHADOWED

Setting this to 1 enables the ping timer mechanism. This bit cannot be cleared to 0 once it has been set to 1.

Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.


alert_handler.ALERT_REGWEN_0 @ 0x18

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Alert configuration write enable bit. If this is cleared to 0, the corresponding ALERT_EN_SHADOWED and ALERT_CLASS_SHADOWED bits are not writable anymore.

Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.


alert_handler.ALERT_REGWEN_1 @ 0x1c

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For alert1


alert_handler.ALERT_REGWEN_2 @ 0x20

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_2
BitsTypeResetNameDescription
0rw0c0x1EN_2

For alert2


alert_handler.ALERT_REGWEN_3 @ 0x24

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_3
BitsTypeResetNameDescription
0rw0c0x1EN_3

For alert3


alert_handler.ALERT_REGWEN_4 @ 0x28

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_4
BitsTypeResetNameDescription
0rw0c0x1EN_4

For alert4


alert_handler.ALERT_REGWEN_5 @ 0x2c

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_5
BitsTypeResetNameDescription
0rw0c0x1EN_5

For alert5


alert_handler.ALERT_REGWEN_6 @ 0x30

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_6
BitsTypeResetNameDescription
0rw0c0x1EN_6

For alert6


alert_handler.ALERT_REGWEN_7 @ 0x34

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_7
BitsTypeResetNameDescription
0rw0c0x1EN_7

For alert7


alert_handler.ALERT_REGWEN_8 @ 0x38

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_8
BitsTypeResetNameDescription
0rw0c0x1EN_8

For alert8


alert_handler.ALERT_REGWEN_9 @ 0x3c

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_9
BitsTypeResetNameDescription
0rw0c0x1EN_9

For alert9


alert_handler.ALERT_REGWEN_10 @ 0x40

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_10
BitsTypeResetNameDescription
0rw0c0x1EN_10

For alert10


alert_handler.ALERT_REGWEN_11 @ 0x44

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_11
BitsTypeResetNameDescription
0rw0c0x1EN_11

For alert11


alert_handler.ALERT_REGWEN_12 @ 0x48

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_12
BitsTypeResetNameDescription
0rw0c0x1EN_12

For alert12


alert_handler.ALERT_REGWEN_13 @ 0x4c

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_13
BitsTypeResetNameDescription
0rw0c0x1EN_13

For alert13


alert_handler.ALERT_REGWEN_14 @ 0x50

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_14
BitsTypeResetNameDescription
0rw0c0x1EN_14

For alert14


alert_handler.ALERT_REGWEN_15 @ 0x54

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_15
BitsTypeResetNameDescription
0rw0c0x1EN_15

For alert15


alert_handler.ALERT_REGWEN_16 @ 0x58

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_16
BitsTypeResetNameDescription
0rw0c0x1EN_16

For alert16


alert_handler.ALERT_REGWEN_17 @ 0x5c

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_17
BitsTypeResetNameDescription
0rw0c0x1EN_17

For alert17


alert_handler.ALERT_REGWEN_18 @ 0x60

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_18
BitsTypeResetNameDescription
0rw0c0x1EN_18

For alert18


alert_handler.ALERT_REGWEN_19 @ 0x64

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_19
BitsTypeResetNameDescription
0rw0c0x1EN_19

For alert19


alert_handler.ALERT_REGWEN_20 @ 0x68

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_20
BitsTypeResetNameDescription
0rw0c0x1EN_20

For alert20


alert_handler.ALERT_REGWEN_21 @ 0x6c

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_21
BitsTypeResetNameDescription
0rw0c0x1EN_21

For alert21


alert_handler.ALERT_REGWEN_22 @ 0x70

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_22
BitsTypeResetNameDescription
0rw0c0x1EN_22

For alert22


alert_handler.ALERT_REGWEN_23 @ 0x74

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_23
BitsTypeResetNameDescription
0rw0c0x1EN_23

For alert23


alert_handler.ALERT_REGWEN_24 @ 0x78

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_24
BitsTypeResetNameDescription
0rw0c0x1EN_24

For alert24


alert_handler.ALERT_REGWEN_25 @ 0x7c

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_25
BitsTypeResetNameDescription
0rw0c0x1EN_25

For alert25


alert_handler.ALERT_REGWEN_26 @ 0x80

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_26
BitsTypeResetNameDescription
0rw0c0x1EN_26

For alert26


alert_handler.ALERT_REGWEN_27 @ 0x84

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_27
BitsTypeResetNameDescription
0rw0c0x1EN_27

For alert27


alert_handler.ALERT_REGWEN_28 @ 0x88

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_28
BitsTypeResetNameDescription
0rw0c0x1EN_28

For alert28


alert_handler.ALERT_REGWEN_29 @ 0x8c

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_29
BitsTypeResetNameDescription
0rw0c0x1EN_29

For alert29


alert_handler.ALERT_REGWEN_30 @ 0x90

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_30
BitsTypeResetNameDescription
0rw0c0x1EN_30

For alert30


alert_handler.ALERT_REGWEN_31 @ 0x94

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_31
BitsTypeResetNameDescription
0rw0c0x1EN_31

For alert31


alert_handler.ALERT_REGWEN_32 @ 0x98

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_32
BitsTypeResetNameDescription
0rw0c0x1EN_32

For alert32


alert_handler.ALERT_REGWEN_33 @ 0x9c

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_33
BitsTypeResetNameDescription
0rw0c0x1EN_33

For alert33


alert_handler.ALERT_REGWEN_34 @ 0xa0

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_34
BitsTypeResetNameDescription
0rw0c0x1EN_34

For alert34


alert_handler.ALERT_REGWEN_35 @ 0xa4

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_35
BitsTypeResetNameDescription
0rw0c0x1EN_35

For alert35


alert_handler.ALERT_REGWEN_36 @ 0xa8

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_36
BitsTypeResetNameDescription
0rw0c0x1EN_36

For alert36


alert_handler.ALERT_REGWEN_37 @ 0xac

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_37
BitsTypeResetNameDescription
0rw0c0x1EN_37

For alert37


alert_handler.ALERT_REGWEN_38 @ 0xb0

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_38
BitsTypeResetNameDescription
0rw0c0x1EN_38

For alert38


alert_handler.ALERT_REGWEN_39 @ 0xb4

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_39
BitsTypeResetNameDescription
0rw0c0x1EN_39

For alert39


alert_handler.ALERT_REGWEN_40 @ 0xb8

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_40
BitsTypeResetNameDescription
0rw0c0x1EN_40

For alert40


alert_handler.ALERT_REGWEN_41 @ 0xbc

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_41
BitsTypeResetNameDescription
0rw0c0x1EN_41

For alert41


alert_handler.ALERT_REGWEN_42 @ 0xc0

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_42
BitsTypeResetNameDescription
0rw0c0x1EN_42

For alert42


alert_handler.ALERT_REGWEN_43 @ 0xc4

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_43
BitsTypeResetNameDescription
0rw0c0x1EN_43

For alert43


alert_handler.ALERT_REGWEN_44 @ 0xc8

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_44
BitsTypeResetNameDescription
0rw0c0x1EN_44

For alert44


alert_handler.ALERT_REGWEN_45 @ 0xcc

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_45
BitsTypeResetNameDescription
0rw0c0x1EN_45

For alert45


alert_handler.ALERT_REGWEN_46 @ 0xd0

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_46
BitsTypeResetNameDescription
0rw0c0x1EN_46

For alert46


alert_handler.ALERT_REGWEN_47 @ 0xd4

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_47
BitsTypeResetNameDescription
0rw0c0x1EN_47

For alert47


alert_handler.ALERT_REGWEN_48 @ 0xd8

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_48
BitsTypeResetNameDescription
0rw0c0x1EN_48

For alert48


alert_handler.ALERT_REGWEN_49 @ 0xdc

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_49
BitsTypeResetNameDescription
0rw0c0x1EN_49

For alert49


alert_handler.ALERT_REGWEN_50 @ 0xe0

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_50
BitsTypeResetNameDescription
0rw0c0x1EN_50

For alert50


alert_handler.ALERT_REGWEN_51 @ 0xe4

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_51
BitsTypeResetNameDescription
0rw0c0x1EN_51

For alert51


alert_handler.ALERT_REGWEN_52 @ 0xe8

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_52
BitsTypeResetNameDescription
0rw0c0x1EN_52

For alert52


alert_handler.ALERT_REGWEN_53 @ 0xec

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_53
BitsTypeResetNameDescription
0rw0c0x1EN_53

For alert53


alert_handler.ALERT_REGWEN_54 @ 0xf0

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_54
BitsTypeResetNameDescription
0rw0c0x1EN_54

For alert54


alert_handler.ALERT_REGWEN_55 @ 0xf4

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_55
BitsTypeResetNameDescription
0rw0c0x1EN_55

For alert55


alert_handler.ALERT_REGWEN_56 @ 0xf8

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_56
BitsTypeResetNameDescription
0rw0c0x1EN_56

For alert56


alert_handler.ALERT_REGWEN_57 @ 0xfc

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_57
BitsTypeResetNameDescription
0rw0c0x1EN_57

For alert57


alert_handler.ALERT_REGWEN_58 @ 0x100

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_58
BitsTypeResetNameDescription
0rw0c0x1EN_58

For alert58


alert_handler.ALERT_REGWEN_59 @ 0x104

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_59
BitsTypeResetNameDescription
0rw0c0x1EN_59

For alert59


alert_handler.ALERT_REGWEN_60 @ 0x108

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_60
BitsTypeResetNameDescription
0rw0c0x1EN_60

For alert60


alert_handler.ALERT_REGWEN_61 @ 0x10c

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_61
BitsTypeResetNameDescription
0rw0c0x1EN_61

For alert61


alert_handler.ALERT_REGWEN_62 @ 0x110

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_62
BitsTypeResetNameDescription
0rw0c0x1EN_62

For alert62


alert_handler.ALERT_REGWEN_63 @ 0x114

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_63
BitsTypeResetNameDescription
0rw0c0x1EN_63

For alert63


alert_handler.ALERT_REGWEN_64 @ 0x118

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_64
BitsTypeResetNameDescription
0rw0c0x1EN_64

For alert64


alert_handler.ALERT_EN_SHADOWED_0 @ 0x11c

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_0
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_0
BitsTypeResetNameDescription
0rw0x0EN_A_0

Alert enable bit.

Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.


alert_handler.ALERT_EN_SHADOWED_1 @ 0x120

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_1
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_1
BitsTypeResetNameDescription
0rw0x0EN_A_1

For alert1


alert_handler.ALERT_EN_SHADOWED_2 @ 0x124

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_2
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_2
BitsTypeResetNameDescription
0rw0x0EN_A_2

For alert2


alert_handler.ALERT_EN_SHADOWED_3 @ 0x128

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_3
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_3
BitsTypeResetNameDescription
0rw0x0EN_A_3

For alert3


alert_handler.ALERT_EN_SHADOWED_4 @ 0x12c

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_4
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_4
BitsTypeResetNameDescription
0rw0x0EN_A_4

For alert4


alert_handler.ALERT_EN_SHADOWED_5 @ 0x130

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_5
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_5
BitsTypeResetNameDescription
0rw0x0EN_A_5

For alert5


alert_handler.ALERT_EN_SHADOWED_6 @ 0x134

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_6
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_6
BitsTypeResetNameDescription
0rw0x0EN_A_6

For alert6


alert_handler.ALERT_EN_SHADOWED_7 @ 0x138

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_7
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_7
BitsTypeResetNameDescription
0rw0x0EN_A_7

For alert7


alert_handler.ALERT_EN_SHADOWED_8 @ 0x13c

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_8
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_8
BitsTypeResetNameDescription
0rw0x0EN_A_8

For alert8


alert_handler.ALERT_EN_SHADOWED_9 @ 0x140

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_9
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_9
BitsTypeResetNameDescription
0rw0x0EN_A_9

For alert9


alert_handler.ALERT_EN_SHADOWED_10 @ 0x144

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_10
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_10
BitsTypeResetNameDescription
0rw0x0EN_A_10

For alert10


alert_handler.ALERT_EN_SHADOWED_11 @ 0x148

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_11
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_11
BitsTypeResetNameDescription
0rw0x0EN_A_11

For alert11


alert_handler.ALERT_EN_SHADOWED_12 @ 0x14c

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_12
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_12
BitsTypeResetNameDescription
0rw0x0EN_A_12

For alert12


alert_handler.ALERT_EN_SHADOWED_13 @ 0x150

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_13
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_13
BitsTypeResetNameDescription
0rw0x0EN_A_13

For alert13


alert_handler.ALERT_EN_SHADOWED_14 @ 0x154

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_14
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_14
BitsTypeResetNameDescription
0rw0x0EN_A_14

For alert14


alert_handler.ALERT_EN_SHADOWED_15 @ 0x158

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_15
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_15
BitsTypeResetNameDescription
0rw0x0EN_A_15

For alert15


alert_handler.ALERT_EN_SHADOWED_16 @ 0x15c

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_16
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_16
BitsTypeResetNameDescription
0rw0x0EN_A_16

For alert16


alert_handler.ALERT_EN_SHADOWED_17 @ 0x160

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_17
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_17
BitsTypeResetNameDescription
0rw0x0EN_A_17

For alert17


alert_handler.ALERT_EN_SHADOWED_18 @ 0x164

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_18
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_18
BitsTypeResetNameDescription
0rw0x0EN_A_18

For alert18


alert_handler.ALERT_EN_SHADOWED_19 @ 0x168

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_19
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_19
BitsTypeResetNameDescription
0rw0x0EN_A_19

For alert19


alert_handler.ALERT_EN_SHADOWED_20 @ 0x16c

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_20
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_20
BitsTypeResetNameDescription
0rw0x0EN_A_20

For alert20


alert_handler.ALERT_EN_SHADOWED_21 @ 0x170

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_21
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_21
BitsTypeResetNameDescription
0rw0x0EN_A_21

For alert21


alert_handler.ALERT_EN_SHADOWED_22 @ 0x174

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_22
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_22
BitsTypeResetNameDescription
0rw0x0EN_A_22

For alert22


alert_handler.ALERT_EN_SHADOWED_23 @ 0x178

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_23
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_23
BitsTypeResetNameDescription
0rw0x0EN_A_23

For alert23


alert_handler.ALERT_EN_SHADOWED_24 @ 0x17c

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_24
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_24
BitsTypeResetNameDescription
0rw0x0EN_A_24

For alert24


alert_handler.ALERT_EN_SHADOWED_25 @ 0x180

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_25
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_25
BitsTypeResetNameDescription
0rw0x0EN_A_25

For alert25


alert_handler.ALERT_EN_SHADOWED_26 @ 0x184

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_26
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_26
BitsTypeResetNameDescription
0rw0x0EN_A_26

For alert26


alert_handler.ALERT_EN_SHADOWED_27 @ 0x188

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_27
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_27
BitsTypeResetNameDescription
0rw0x0EN_A_27

For alert27


alert_handler.ALERT_EN_SHADOWED_28 @ 0x18c

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_28
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_28
BitsTypeResetNameDescription
0rw0x0EN_A_28

For alert28


alert_handler.ALERT_EN_SHADOWED_29 @ 0x190

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_29
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_29
BitsTypeResetNameDescription
0rw0x0EN_A_29

For alert29


alert_handler.ALERT_EN_SHADOWED_30 @ 0x194

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_30
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_30
BitsTypeResetNameDescription
0rw0x0EN_A_30

For alert30


alert_handler.ALERT_EN_SHADOWED_31 @ 0x198

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_31
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_31
BitsTypeResetNameDescription
0rw0x0EN_A_31

For alert31


alert_handler.ALERT_EN_SHADOWED_32 @ 0x19c

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_32
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_32
BitsTypeResetNameDescription
0rw0x0EN_A_32

For alert32


alert_handler.ALERT_EN_SHADOWED_33 @ 0x1a0

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_33
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_33
BitsTypeResetNameDescription
0rw0x0EN_A_33

For alert33


alert_handler.ALERT_EN_SHADOWED_34 @ 0x1a4

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_34
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_34
BitsTypeResetNameDescription
0rw0x0EN_A_34

For alert34


alert_handler.ALERT_EN_SHADOWED_35 @ 0x1a8

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_35
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_35
BitsTypeResetNameDescription
0rw0x0EN_A_35

For alert35


alert_handler.ALERT_EN_SHADOWED_36 @ 0x1ac

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_36
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_36
BitsTypeResetNameDescription
0rw0x0EN_A_36

For alert36


alert_handler.ALERT_EN_SHADOWED_37 @ 0x1b0

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_37
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_37
BitsTypeResetNameDescription
0rw0x0EN_A_37

For alert37


alert_handler.ALERT_EN_SHADOWED_38 @ 0x1b4

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_38
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_38
BitsTypeResetNameDescription
0rw0x0EN_A_38

For alert38


alert_handler.ALERT_EN_SHADOWED_39 @ 0x1b8

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_39
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_39
BitsTypeResetNameDescription
0rw0x0EN_A_39

For alert39


alert_handler.ALERT_EN_SHADOWED_40 @ 0x1bc

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_40
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_40
BitsTypeResetNameDescription
0rw0x0EN_A_40

For alert40


alert_handler.ALERT_EN_SHADOWED_41 @ 0x1c0

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_41
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_41
BitsTypeResetNameDescription
0rw0x0EN_A_41

For alert41


alert_handler.ALERT_EN_SHADOWED_42 @ 0x1c4

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_42
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_42
BitsTypeResetNameDescription
0rw0x0EN_A_42

For alert42


alert_handler.ALERT_EN_SHADOWED_43 @ 0x1c8

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_43
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_43
BitsTypeResetNameDescription
0rw0x0EN_A_43

For alert43


alert_handler.ALERT_EN_SHADOWED_44 @ 0x1cc

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_44
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_44
BitsTypeResetNameDescription
0rw0x0EN_A_44

For alert44


alert_handler.ALERT_EN_SHADOWED_45 @ 0x1d0

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_45
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_45
BitsTypeResetNameDescription
0rw0x0EN_A_45

For alert45


alert_handler.ALERT_EN_SHADOWED_46 @ 0x1d4

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_46
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_46
BitsTypeResetNameDescription
0rw0x0EN_A_46

For alert46


alert_handler.ALERT_EN_SHADOWED_47 @ 0x1d8

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_47
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_47
BitsTypeResetNameDescription
0rw0x0EN_A_47

For alert47


alert_handler.ALERT_EN_SHADOWED_48 @ 0x1dc

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_48
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_48
BitsTypeResetNameDescription
0rw0x0EN_A_48

For alert48


alert_handler.ALERT_EN_SHADOWED_49 @ 0x1e0

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_49
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_49
BitsTypeResetNameDescription
0rw0x0EN_A_49

For alert49


alert_handler.ALERT_EN_SHADOWED_50 @ 0x1e4

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_50
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_50
BitsTypeResetNameDescription
0rw0x0EN_A_50

For alert50


alert_handler.ALERT_EN_SHADOWED_51 @ 0x1e8

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_51
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_51
BitsTypeResetNameDescription
0rw0x0EN_A_51

For alert51


alert_handler.ALERT_EN_SHADOWED_52 @ 0x1ec

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_52
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_52
BitsTypeResetNameDescription
0rw0x0EN_A_52

For alert52


alert_handler.ALERT_EN_SHADOWED_53 @ 0x1f0

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_53
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_53
BitsTypeResetNameDescription
0rw0x0EN_A_53

For alert53


alert_handler.ALERT_EN_SHADOWED_54 @ 0x1f4

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_54
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_54
BitsTypeResetNameDescription
0rw0x0EN_A_54

For alert54


alert_handler.ALERT_EN_SHADOWED_55 @ 0x1f8

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_55
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_55
BitsTypeResetNameDescription
0rw0x0EN_A_55

For alert55


alert_handler.ALERT_EN_SHADOWED_56 @ 0x1fc

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_56
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_56
BitsTypeResetNameDescription
0rw0x0EN_A_56

For alert56


alert_handler.ALERT_EN_SHADOWED_57 @ 0x200

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_57
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_57
BitsTypeResetNameDescription
0rw0x0EN_A_57

For alert57


alert_handler.ALERT_EN_SHADOWED_58 @ 0x204

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_58
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_58
BitsTypeResetNameDescription
0rw0x0EN_A_58

For alert58


alert_handler.ALERT_EN_SHADOWED_59 @ 0x208

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_59
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_59
BitsTypeResetNameDescription
0rw0x0EN_A_59

For alert59


alert_handler.ALERT_EN_SHADOWED_60 @ 0x20c

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_60
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_60
BitsTypeResetNameDescription
0rw0x0EN_A_60

For alert60


alert_handler.ALERT_EN_SHADOWED_61 @ 0x210

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_61
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_61
BitsTypeResetNameDescription
0rw0x0EN_A_61

For alert61


alert_handler.ALERT_EN_SHADOWED_62 @ 0x214

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_62
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_62
BitsTypeResetNameDescription
0rw0x0EN_A_62

For alert62


alert_handler.ALERT_EN_SHADOWED_63 @ 0x218

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_63
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_63
BitsTypeResetNameDescription
0rw0x0EN_A_63

For alert63


alert_handler.ALERT_EN_SHADOWED_64 @ 0x21c

Enable register for alerts.

Reset default = 0x0, mask 0x1
Register enable = ALERT_REGWEN_64
31302928272625242322212019181716
 
1514131211109876543210
  EN_A_64
BitsTypeResetNameDescription
0rw0x0EN_A_64

For alert64


alert_handler.ALERT_CLASS_SHADOWED_0 @ 0x220

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_0
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_0
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_0

Classification

0x0ClassA

0x1ClassB

0x2ClassC

0x3ClassD


alert_handler.ALERT_CLASS_SHADOWED_1 @ 0x224

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_1
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_1
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_1

For alert1


alert_handler.ALERT_CLASS_SHADOWED_2 @ 0x228

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_2
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_2
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_2

For alert2


alert_handler.ALERT_CLASS_SHADOWED_3 @ 0x22c

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_3
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_3
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_3

For alert3


alert_handler.ALERT_CLASS_SHADOWED_4 @ 0x230

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_4
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_4
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_4

For alert4


alert_handler.ALERT_CLASS_SHADOWED_5 @ 0x234

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_5
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_5
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_5

For alert5


alert_handler.ALERT_CLASS_SHADOWED_6 @ 0x238

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_6
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_6
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_6

For alert6


alert_handler.ALERT_CLASS_SHADOWED_7 @ 0x23c

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_7
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_7
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_7

For alert7


alert_handler.ALERT_CLASS_SHADOWED_8 @ 0x240

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_8
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_8
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_8

For alert8


alert_handler.ALERT_CLASS_SHADOWED_9 @ 0x244

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_9
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_9
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_9

For alert9


alert_handler.ALERT_CLASS_SHADOWED_10 @ 0x248

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_10
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_10
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_10

For alert10


alert_handler.ALERT_CLASS_SHADOWED_11 @ 0x24c

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_11
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_11
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_11

For alert11


alert_handler.ALERT_CLASS_SHADOWED_12 @ 0x250

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_12
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_12
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_12

For alert12


alert_handler.ALERT_CLASS_SHADOWED_13 @ 0x254

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_13
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_13
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_13

For alert13


alert_handler.ALERT_CLASS_SHADOWED_14 @ 0x258

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_14
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_14
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_14

For alert14


alert_handler.ALERT_CLASS_SHADOWED_15 @ 0x25c

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_15
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_15
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_15

For alert15


alert_handler.ALERT_CLASS_SHADOWED_16 @ 0x260

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_16
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_16
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_16

For alert16


alert_handler.ALERT_CLASS_SHADOWED_17 @ 0x264

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_17
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_17
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_17

For alert17


alert_handler.ALERT_CLASS_SHADOWED_18 @ 0x268

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_18
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_18
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_18

For alert18


alert_handler.ALERT_CLASS_SHADOWED_19 @ 0x26c

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_19
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_19
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_19

For alert19


alert_handler.ALERT_CLASS_SHADOWED_20 @ 0x270

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_20
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_20
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_20

For alert20


alert_handler.ALERT_CLASS_SHADOWED_21 @ 0x274

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_21
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_21
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_21

For alert21


alert_handler.ALERT_CLASS_SHADOWED_22 @ 0x278

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_22
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_22
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_22

For alert22


alert_handler.ALERT_CLASS_SHADOWED_23 @ 0x27c

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_23
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_23
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_23

For alert23


alert_handler.ALERT_CLASS_SHADOWED_24 @ 0x280

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_24
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_24
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_24

For alert24


alert_handler.ALERT_CLASS_SHADOWED_25 @ 0x284

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_25
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_25
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_25

For alert25


alert_handler.ALERT_CLASS_SHADOWED_26 @ 0x288

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_26
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_26
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_26

For alert26


alert_handler.ALERT_CLASS_SHADOWED_27 @ 0x28c

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_27
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_27
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_27

For alert27


alert_handler.ALERT_CLASS_SHADOWED_28 @ 0x290

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_28
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_28
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_28

For alert28


alert_handler.ALERT_CLASS_SHADOWED_29 @ 0x294

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_29
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_29
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_29

For alert29


alert_handler.ALERT_CLASS_SHADOWED_30 @ 0x298

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_30
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_30
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_30

For alert30


alert_handler.ALERT_CLASS_SHADOWED_31 @ 0x29c

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_31
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_31
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_31

For alert31


alert_handler.ALERT_CLASS_SHADOWED_32 @ 0x2a0

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_32
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_32
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_32

For alert32


alert_handler.ALERT_CLASS_SHADOWED_33 @ 0x2a4

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_33
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_33
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_33

For alert33


alert_handler.ALERT_CLASS_SHADOWED_34 @ 0x2a8

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_34
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_34
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_34

For alert34


alert_handler.ALERT_CLASS_SHADOWED_35 @ 0x2ac

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_35
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_35
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_35

For alert35


alert_handler.ALERT_CLASS_SHADOWED_36 @ 0x2b0

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_36
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_36
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_36

For alert36


alert_handler.ALERT_CLASS_SHADOWED_37 @ 0x2b4

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_37
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_37
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_37

For alert37


alert_handler.ALERT_CLASS_SHADOWED_38 @ 0x2b8

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_38
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_38
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_38

For alert38


alert_handler.ALERT_CLASS_SHADOWED_39 @ 0x2bc

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_39
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_39
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_39

For alert39


alert_handler.ALERT_CLASS_SHADOWED_40 @ 0x2c0

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_40
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_40
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_40

For alert40


alert_handler.ALERT_CLASS_SHADOWED_41 @ 0x2c4

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_41
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_41
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_41

For alert41


alert_handler.ALERT_CLASS_SHADOWED_42 @ 0x2c8

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_42
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_42
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_42

For alert42


alert_handler.ALERT_CLASS_SHADOWED_43 @ 0x2cc

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_43
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_43
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_43

For alert43


alert_handler.ALERT_CLASS_SHADOWED_44 @ 0x2d0

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_44
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_44
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_44

For alert44


alert_handler.ALERT_CLASS_SHADOWED_45 @ 0x2d4

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_45
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_45
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_45

For alert45


alert_handler.ALERT_CLASS_SHADOWED_46 @ 0x2d8

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_46
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_46
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_46

For alert46


alert_handler.ALERT_CLASS_SHADOWED_47 @ 0x2dc

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_47
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_47
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_47

For alert47


alert_handler.ALERT_CLASS_SHADOWED_48 @ 0x2e0

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_48
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_48
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_48

For alert48


alert_handler.ALERT_CLASS_SHADOWED_49 @ 0x2e4

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_49
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_49
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_49

For alert49


alert_handler.ALERT_CLASS_SHADOWED_50 @ 0x2e8

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_50
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_50
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_50

For alert50


alert_handler.ALERT_CLASS_SHADOWED_51 @ 0x2ec

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_51
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_51
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_51

For alert51


alert_handler.ALERT_CLASS_SHADOWED_52 @ 0x2f0

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_52
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_52
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_52

For alert52


alert_handler.ALERT_CLASS_SHADOWED_53 @ 0x2f4

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_53
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_53
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_53

For alert53


alert_handler.ALERT_CLASS_SHADOWED_54 @ 0x2f8

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_54
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_54
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_54

For alert54


alert_handler.ALERT_CLASS_SHADOWED_55 @ 0x2fc

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_55
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_55
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_55

For alert55


alert_handler.ALERT_CLASS_SHADOWED_56 @ 0x300

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_56
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_56
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_56

For alert56


alert_handler.ALERT_CLASS_SHADOWED_57 @ 0x304

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_57
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_57
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_57

For alert57


alert_handler.ALERT_CLASS_SHADOWED_58 @ 0x308

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_58
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_58
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_58

For alert58


alert_handler.ALERT_CLASS_SHADOWED_59 @ 0x30c

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_59
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_59
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_59

For alert59


alert_handler.ALERT_CLASS_SHADOWED_60 @ 0x310

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_60
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_60
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_60

For alert60


alert_handler.ALERT_CLASS_SHADOWED_61 @ 0x314

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_61
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_61
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_61

For alert61


alert_handler.ALERT_CLASS_SHADOWED_62 @ 0x318

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_62
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_62
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_62

For alert62


alert_handler.ALERT_CLASS_SHADOWED_63 @ 0x31c

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_63
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_63
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_63

For alert63


alert_handler.ALERT_CLASS_SHADOWED_64 @ 0x320

Class assignment of alerts.

Reset default = 0x0, mask 0x3
Register enable = ALERT_REGWEN_64
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_A_64
BitsTypeResetNameDescription
1:0rw0x0CLASS_A_64

For alert64


alert_handler.ALERT_CAUSE_0 @ 0x324

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_0
BitsTypeResetNameDescription
0rw1c0x0A_0

Cause bit


alert_handler.ALERT_CAUSE_1 @ 0x328

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_1
BitsTypeResetNameDescription
0rw1c0x0A_1

For ALERT1


alert_handler.ALERT_CAUSE_2 @ 0x32c

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_2
BitsTypeResetNameDescription
0rw1c0x0A_2

For ALERT2


alert_handler.ALERT_CAUSE_3 @ 0x330

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_3
BitsTypeResetNameDescription
0rw1c0x0A_3

For ALERT3


alert_handler.ALERT_CAUSE_4 @ 0x334

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_4
BitsTypeResetNameDescription
0rw1c0x0A_4

For ALERT4


alert_handler.ALERT_CAUSE_5 @ 0x338

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_5
BitsTypeResetNameDescription
0rw1c0x0A_5

For ALERT5


alert_handler.ALERT_CAUSE_6 @ 0x33c

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_6
BitsTypeResetNameDescription
0rw1c0x0A_6

For ALERT6


alert_handler.ALERT_CAUSE_7 @ 0x340

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_7
BitsTypeResetNameDescription
0rw1c0x0A_7

For ALERT7


alert_handler.ALERT_CAUSE_8 @ 0x344

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_8
BitsTypeResetNameDescription
0rw1c0x0A_8

For ALERT8


alert_handler.ALERT_CAUSE_9 @ 0x348

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_9
BitsTypeResetNameDescription
0rw1c0x0A_9

For ALERT9


alert_handler.ALERT_CAUSE_10 @ 0x34c

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_10
BitsTypeResetNameDescription
0rw1c0x0A_10

For ALERT10


alert_handler.ALERT_CAUSE_11 @ 0x350

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_11
BitsTypeResetNameDescription
0rw1c0x0A_11

For ALERT11


alert_handler.ALERT_CAUSE_12 @ 0x354

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_12
BitsTypeResetNameDescription
0rw1c0x0A_12

For ALERT12


alert_handler.ALERT_CAUSE_13 @ 0x358

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_13
BitsTypeResetNameDescription
0rw1c0x0A_13

For ALERT13


alert_handler.ALERT_CAUSE_14 @ 0x35c

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_14
BitsTypeResetNameDescription
0rw1c0x0A_14

For ALERT14


alert_handler.ALERT_CAUSE_15 @ 0x360

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_15
BitsTypeResetNameDescription
0rw1c0x0A_15

For ALERT15


alert_handler.ALERT_CAUSE_16 @ 0x364

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_16
BitsTypeResetNameDescription
0rw1c0x0A_16

For ALERT16


alert_handler.ALERT_CAUSE_17 @ 0x368

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_17
BitsTypeResetNameDescription
0rw1c0x0A_17

For ALERT17


alert_handler.ALERT_CAUSE_18 @ 0x36c

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_18
BitsTypeResetNameDescription
0rw1c0x0A_18

For ALERT18


alert_handler.ALERT_CAUSE_19 @ 0x370

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_19
BitsTypeResetNameDescription
0rw1c0x0A_19

For ALERT19


alert_handler.ALERT_CAUSE_20 @ 0x374

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_20
BitsTypeResetNameDescription
0rw1c0x0A_20

For ALERT20


alert_handler.ALERT_CAUSE_21 @ 0x378

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_21
BitsTypeResetNameDescription
0rw1c0x0A_21

For ALERT21


alert_handler.ALERT_CAUSE_22 @ 0x37c

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_22
BitsTypeResetNameDescription
0rw1c0x0A_22

For ALERT22


alert_handler.ALERT_CAUSE_23 @ 0x380

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_23
BitsTypeResetNameDescription
0rw1c0x0A_23

For ALERT23


alert_handler.ALERT_CAUSE_24 @ 0x384

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_24
BitsTypeResetNameDescription
0rw1c0x0A_24

For ALERT24


alert_handler.ALERT_CAUSE_25 @ 0x388

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_25
BitsTypeResetNameDescription
0rw1c0x0A_25

For ALERT25


alert_handler.ALERT_CAUSE_26 @ 0x38c

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_26
BitsTypeResetNameDescription
0rw1c0x0A_26

For ALERT26


alert_handler.ALERT_CAUSE_27 @ 0x390

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_27
BitsTypeResetNameDescription
0rw1c0x0A_27

For ALERT27


alert_handler.ALERT_CAUSE_28 @ 0x394

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_28
BitsTypeResetNameDescription
0rw1c0x0A_28

For ALERT28


alert_handler.ALERT_CAUSE_29 @ 0x398

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_29
BitsTypeResetNameDescription
0rw1c0x0A_29

For ALERT29


alert_handler.ALERT_CAUSE_30 @ 0x39c

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_30
BitsTypeResetNameDescription
0rw1c0x0A_30

For ALERT30


alert_handler.ALERT_CAUSE_31 @ 0x3a0

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_31
BitsTypeResetNameDescription
0rw1c0x0A_31

For ALERT31


alert_handler.ALERT_CAUSE_32 @ 0x3a4

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_32
BitsTypeResetNameDescription
0rw1c0x0A_32

For ALERT32


alert_handler.ALERT_CAUSE_33 @ 0x3a8

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_33
BitsTypeResetNameDescription
0rw1c0x0A_33

For ALERT33


alert_handler.ALERT_CAUSE_34 @ 0x3ac

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_34
BitsTypeResetNameDescription
0rw1c0x0A_34

For ALERT34


alert_handler.ALERT_CAUSE_35 @ 0x3b0

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_35
BitsTypeResetNameDescription
0rw1c0x0A_35

For ALERT35


alert_handler.ALERT_CAUSE_36 @ 0x3b4

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_36
BitsTypeResetNameDescription
0rw1c0x0A_36

For ALERT36


alert_handler.ALERT_CAUSE_37 @ 0x3b8

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_37
BitsTypeResetNameDescription
0rw1c0x0A_37

For ALERT37


alert_handler.ALERT_CAUSE_38 @ 0x3bc

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_38
BitsTypeResetNameDescription
0rw1c0x0A_38

For ALERT38


alert_handler.ALERT_CAUSE_39 @ 0x3c0

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_39
BitsTypeResetNameDescription
0rw1c0x0A_39

For ALERT39


alert_handler.ALERT_CAUSE_40 @ 0x3c4

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_40
BitsTypeResetNameDescription
0rw1c0x0A_40

For ALERT40


alert_handler.ALERT_CAUSE_41 @ 0x3c8

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_41
BitsTypeResetNameDescription
0rw1c0x0A_41

For ALERT41


alert_handler.ALERT_CAUSE_42 @ 0x3cc

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_42
BitsTypeResetNameDescription
0rw1c0x0A_42

For ALERT42


alert_handler.ALERT_CAUSE_43 @ 0x3d0

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_43
BitsTypeResetNameDescription
0rw1c0x0A_43

For ALERT43


alert_handler.ALERT_CAUSE_44 @ 0x3d4

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_44
BitsTypeResetNameDescription
0rw1c0x0A_44

For ALERT44


alert_handler.ALERT_CAUSE_45 @ 0x3d8

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_45
BitsTypeResetNameDescription
0rw1c0x0A_45

For ALERT45


alert_handler.ALERT_CAUSE_46 @ 0x3dc

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_46
BitsTypeResetNameDescription
0rw1c0x0A_46

For ALERT46


alert_handler.ALERT_CAUSE_47 @ 0x3e0

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_47
BitsTypeResetNameDescription
0rw1c0x0A_47

For ALERT47


alert_handler.ALERT_CAUSE_48 @ 0x3e4

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_48
BitsTypeResetNameDescription
0rw1c0x0A_48

For ALERT48


alert_handler.ALERT_CAUSE_49 @ 0x3e8

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_49
BitsTypeResetNameDescription
0rw1c0x0A_49

For ALERT49


alert_handler.ALERT_CAUSE_50 @ 0x3ec

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_50
BitsTypeResetNameDescription
0rw1c0x0A_50

For ALERT50


alert_handler.ALERT_CAUSE_51 @ 0x3f0

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_51
BitsTypeResetNameDescription
0rw1c0x0A_51

For ALERT51


alert_handler.ALERT_CAUSE_52 @ 0x3f4

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_52
BitsTypeResetNameDescription
0rw1c0x0A_52

For ALERT52


alert_handler.ALERT_CAUSE_53 @ 0x3f8

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_53
BitsTypeResetNameDescription
0rw1c0x0A_53

For ALERT53


alert_handler.ALERT_CAUSE_54 @ 0x3fc

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_54
BitsTypeResetNameDescription
0rw1c0x0A_54

For ALERT54


alert_handler.ALERT_CAUSE_55 @ 0x400

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_55
BitsTypeResetNameDescription
0rw1c0x0A_55

For ALERT55


alert_handler.ALERT_CAUSE_56 @ 0x404

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_56
BitsTypeResetNameDescription
0rw1c0x0A_56

For ALERT56


alert_handler.ALERT_CAUSE_57 @ 0x408

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_57
BitsTypeResetNameDescription
0rw1c0x0A_57

For ALERT57


alert_handler.ALERT_CAUSE_58 @ 0x40c

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_58
BitsTypeResetNameDescription
0rw1c0x0A_58

For ALERT58


alert_handler.ALERT_CAUSE_59 @ 0x410

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_59
BitsTypeResetNameDescription
0rw1c0x0A_59

For ALERT59


alert_handler.ALERT_CAUSE_60 @ 0x414

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_60
BitsTypeResetNameDescription
0rw1c0x0A_60

For ALERT60


alert_handler.ALERT_CAUSE_61 @ 0x418

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_61
BitsTypeResetNameDescription
0rw1c0x0A_61

For ALERT61


alert_handler.ALERT_CAUSE_62 @ 0x41c

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_62
BitsTypeResetNameDescription
0rw1c0x0A_62

For ALERT62


alert_handler.ALERT_CAUSE_63 @ 0x420

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_63
BitsTypeResetNameDescription
0rw1c0x0A_63

For ALERT63


alert_handler.ALERT_CAUSE_64 @ 0x424

Alert Cause Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  A_64
BitsTypeResetNameDescription
0rw1c0x0A_64

For ALERT64


alert_handler.LOC_ALERT_REGWEN_0 @ 0x428

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Alert configuration write enable bit. If this is cleared to 0, the corresponding LOC_ALERT_EN_SHADOWED and LOC_ALERT_CLASS_SHADOWED bits are not writable anymore.

Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.


alert_handler.LOC_ALERT_REGWEN_1 @ 0x42c

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For LOC_ALERT1


alert_handler.LOC_ALERT_REGWEN_2 @ 0x430

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_2
BitsTypeResetNameDescription
0rw0c0x1EN_2

For LOC_ALERT2


alert_handler.LOC_ALERT_REGWEN_3 @ 0x434

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_3
BitsTypeResetNameDescription
0rw0c0x1EN_3

For LOC_ALERT3


alert_handler.LOC_ALERT_REGWEN_4 @ 0x438

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_4
BitsTypeResetNameDescription
0rw0c0x1EN_4

For LOC_ALERT4


alert_handler.LOC_ALERT_REGWEN_5 @ 0x43c

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_5
BitsTypeResetNameDescription
0rw0c0x1EN_5

For LOC_ALERT5


alert_handler.LOC_ALERT_REGWEN_6 @ 0x440

Register write enable for alert enable bits.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_6
BitsTypeResetNameDescription
0rw0c0x1EN_6

For LOC_ALERT6


alert_handler.LOC_ALERT_EN_SHADOWED_0 @ 0x444

Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1
Register enable = LOC_ALERT_REGWEN_0
31302928272625242322212019181716
 
1514131211109876543210
  EN_LA_0
BitsTypeResetNameDescription
0rw0x0EN_LA_0

Alert enable bit.

Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.


alert_handler.LOC_ALERT_EN_SHADOWED_1 @ 0x448

Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1
Register enable = LOC_ALERT_REGWEN_1
31302928272625242322212019181716
 
1514131211109876543210
  EN_LA_1
BitsTypeResetNameDescription
0rw0x0EN_LA_1

For LOC_ALERT1


alert_handler.LOC_ALERT_EN_SHADOWED_2 @ 0x44c

Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1
Register enable = LOC_ALERT_REGWEN_2
31302928272625242322212019181716
 
1514131211109876543210
  EN_LA_2
BitsTypeResetNameDescription
0rw0x0EN_LA_2

For LOC_ALERT2


alert_handler.LOC_ALERT_EN_SHADOWED_3 @ 0x450

Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1
Register enable = LOC_ALERT_REGWEN_3
31302928272625242322212019181716
 
1514131211109876543210
  EN_LA_3
BitsTypeResetNameDescription
0rw0x0EN_LA_3

For LOC_ALERT3


alert_handler.LOC_ALERT_EN_SHADOWED_4 @ 0x454

Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1
Register enable = LOC_ALERT_REGWEN_4
31302928272625242322212019181716
 
1514131211109876543210
  EN_LA_4
BitsTypeResetNameDescription
0rw0x0EN_LA_4

For LOC_ALERT4


alert_handler.LOC_ALERT_EN_SHADOWED_5 @ 0x458

Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1
Register enable = LOC_ALERT_REGWEN_5
31302928272625242322212019181716
 
1514131211109876543210
  EN_LA_5
BitsTypeResetNameDescription
0rw0x0EN_LA_5

For LOC_ALERT5


alert_handler.LOC_ALERT_EN_SHADOWED_6 @ 0x45c

Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1
Register enable = LOC_ALERT_REGWEN_6
31302928272625242322212019181716
 
1514131211109876543210
  EN_LA_6
BitsTypeResetNameDescription
0rw0x0EN_LA_6

For LOC_ALERT6


alert_handler.LOC_ALERT_CLASS_SHADOWED_0 @ 0x460

Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x3
Register enable = LOC_ALERT_REGWEN_0
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_LA_0
BitsTypeResetNameDescription
1:0rw0x0CLASS_LA_0

Classification

0x0ClassA

0x1ClassB

0x2ClassC

0x3ClassD


alert_handler.LOC_ALERT_CLASS_SHADOWED_1 @ 0x464

Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x3
Register enable = LOC_ALERT_REGWEN_1
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_LA_1
BitsTypeResetNameDescription
1:0rw0x0CLASS_LA_1

For LOC_ALERT1


alert_handler.LOC_ALERT_CLASS_SHADOWED_2 @ 0x468

Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x3
Register enable = LOC_ALERT_REGWEN_2
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_LA_2
BitsTypeResetNameDescription
1:0rw0x0CLASS_LA_2

For LOC_ALERT2


alert_handler.LOC_ALERT_CLASS_SHADOWED_3 @ 0x46c

Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x3
Register enable = LOC_ALERT_REGWEN_3
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_LA_3
BitsTypeResetNameDescription
1:0rw0x0CLASS_LA_3

For LOC_ALERT3


alert_handler.LOC_ALERT_CLASS_SHADOWED_4 @ 0x470

Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x3
Register enable = LOC_ALERT_REGWEN_4
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_LA_4
BitsTypeResetNameDescription
1:0rw0x0CLASS_LA_4

For LOC_ALERT4


alert_handler.LOC_ALERT_CLASS_SHADOWED_5 @ 0x474

Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x3
Register enable = LOC_ALERT_REGWEN_5
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_LA_5
BitsTypeResetNameDescription
1:0rw0x0CLASS_LA_5

For LOC_ALERT5


alert_handler.LOC_ALERT_CLASS_SHADOWED_6 @ 0x478

Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x3
Register enable = LOC_ALERT_REGWEN_6
31302928272625242322212019181716
 
1514131211109876543210
  CLASS_LA_6
BitsTypeResetNameDescription
1:0rw0x0CLASS_LA_6

For LOC_ALERT6


alert_handler.LOC_ALERT_CAUSE_0 @ 0x47c

Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  LA_0
BitsTypeResetNameDescription
0rw1c0x0LA_0

Cause bit


alert_handler.LOC_ALERT_CAUSE_1 @ 0x480

Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  LA_1
BitsTypeResetNameDescription
0rw1c0x0LA_1

For LOC_ALERT1


alert_handler.LOC_ALERT_CAUSE_2 @ 0x484

Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  LA_2
BitsTypeResetNameDescription
0rw1c0x0LA_2

For LOC_ALERT2


alert_handler.LOC_ALERT_CAUSE_3 @ 0x488

Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  LA_3
BitsTypeResetNameDescription
0rw1c0x0LA_3

For LOC_ALERT3


alert_handler.LOC_ALERT_CAUSE_4 @ 0x48c

Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  LA_4
BitsTypeResetNameDescription
0rw1c0x0LA_4

For LOC_ALERT4


alert_handler.LOC_ALERT_CAUSE_5 @ 0x490

Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  LA_5
BitsTypeResetNameDescription
0rw1c0x0LA_5

For LOC_ALERT5


alert_handler.LOC_ALERT_CAUSE_6 @ 0x494

Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  LA_6
BitsTypeResetNameDescription
0rw1c0x0LA_6

For LOC_ALERT6


alert_handler.CLASSA_REGWEN @ 0x498

Lock bit for Class A configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  CLASSA_REGWEN
BitsTypeResetNameDescription
0rw0c0x1CLASSA_REGWEN

Class configuration enable bit. If this is cleared to 0, the corresponding class configuration registers cannot be written anymore.


alert_handler.CLASSA_CTRL_SHADOWED @ 0x49c

Escalation control register for alert Class A. Can not be modified if CLASSA_REGWEN is false.

Reset default = 0x393c, mask 0x3fff
Register enable = CLASSA_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  MAP_E3 MAP_E2 MAP_E1 MAP_E0 EN_E3 EN_E2 EN_E1 EN_E0 LOCK EN
BitsTypeResetNameDescription
0rw0x0EN

Enable escalation mechanisms (accumulation and interrupt timeout) for Class A. Note that interrupts can fire regardless of whether the escalation mechanisms are enabled for this class or not.

1rw0x0LOCK

Enable automatic locking of escalation counter for class A. If true, there is no way to stop the escalation protocol for class A once it has been triggered.

2rw0x1EN_E0

Enable escalation signal 0 for Class A

3rw0x1EN_E1

Enable escalation signal 1 for Class A

4rw0x1EN_E2

Enable escalation signal 2 for Class A

5rw0x1EN_E3

Enable escalation signal 3 for Class A

7:6rw0x0MAP_E0

Determines in which escalation phase escalation signal 0 shall be asserted.

9:8rw0x1MAP_E1

Determines in which escalation phase escalation signal 1 shall be asserted.

11:10rw0x2MAP_E2

Determines in which escalation phase escalation signal 2 shall be asserted.

13:12rw0x3MAP_E3

Determines in which escalation phase escalation signal 3 shall be asserted.


alert_handler.CLASSA_CLR_REGWEN @ 0x4a0

Clear enable for escalation protocol of Class A alerts.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  CLASSA_CLR_REGWEN
BitsTypeResetNameDescription
0rw0c0x1CLASSA_CLR_REGWEN

Register defaults to true, can only be cleared. This register is set to false by the hardware if the escalation protocol has been triggered and the bit CLASSA_CTRL_SHADOWED.LOCK is true.


alert_handler.CLASSA_CLR_SHADOWED @ 0x4a4

Clear for escalation protocol of Class A.

Reset default = 0x0, mask 0x1
Register enable = CLASSA_CLR_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  CLASSA_CLR_SHADOWED
BitsTypeResetNameDescription
0rw0x0CLASSA_CLR_SHADOWED

Writing 1 to this register clears the accumulator and aborts escalation (if it has been triggered). This clear is disabled if CLASSA_CLR_REGWEN is false.


alert_handler.CLASSA_ACCUM_CNT @ 0x4a8

Current accumulation value for alert Class A. Software can clear this register with a write to CLASSA_CLR_SHADOWED register unless CLASSA_CLR_REGWEN is false.

Reset default = 0x0, mask 0xffff
31302928272625242322212019181716
 
1514131211109876543210
CLASSA_ACCUM_CNT
BitsTypeResetNameDescription
15:0roxCLASSA_ACCUM_CNT

alert_handler.CLASSA_ACCUM_THRESH_SHADOWED @ 0x4ac

Accumulation threshold value for alert Class A.

Reset default = 0x0, mask 0xffff
Register enable = CLASSA_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
CLASSA_ACCUM_THRESH_SHADOWED
BitsTypeResetNameDescription
15:0rw0x0CLASSA_ACCUM_THRESH_SHADOWED

Once the accumulation value register is equal to the threshold escalation will be triggered on the next alert occurrence within this class A begins. Note that this register can not be modified if CLASSA_REGWEN is false.


alert_handler.CLASSA_TIMEOUT_CYC_SHADOWED @ 0x4b0

Interrupt timeout in cycles.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSA_REGWEN
31302928272625242322212019181716
CLASSA_TIMEOUT_CYC_SHADOWED...
1514131211109876543210
...CLASSA_TIMEOUT_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSA_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class A. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSA_REGWEN is false.


alert_handler.CLASSA_CRASHDUMP_TRIGGER_SHADOWED @ 0x4b4

Crashdump trigger configuration for Class A.

Reset default = 0x0, mask 0x3
Register enable = CLASSA_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  CLASSA_CRASHDUMP_TRIGGER_SHADOWED
BitsTypeResetNameDescription
1:0rw0x0CLASSA_CRASHDUMP_TRIGGER_SHADOWED

Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation timer states. It is recommended to capture the crashdump upon entering the first escalation phase that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order to prevent spurious alert events from masking the original alert causes. Note that this register can not be modified if CLASSA_REGWEN is false.


alert_handler.CLASSA_PHASE0_CYC_SHADOWED @ 0x4b8

Duration of escalation phase 0 for Class A.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSA_REGWEN
31302928272625242322212019181716
CLASSA_PHASE0_CYC_SHADOWED...
1514131211109876543210
...CLASSA_PHASE0_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSA_PHASE0_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSA_REGWEN is false.


alert_handler.CLASSA_PHASE1_CYC_SHADOWED @ 0x4bc

Duration of escalation phase 1 for Class A.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSA_REGWEN
31302928272625242322212019181716
CLASSA_PHASE1_CYC_SHADOWED...
1514131211109876543210
...CLASSA_PHASE1_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSA_PHASE1_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSA_REGWEN is false.


alert_handler.CLASSA_PHASE2_CYC_SHADOWED @ 0x4c0

Duration of escalation phase 2 for Class A.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSA_REGWEN
31302928272625242322212019181716
CLASSA_PHASE2_CYC_SHADOWED...
1514131211109876543210
...CLASSA_PHASE2_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSA_PHASE2_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSA_REGWEN is false.


alert_handler.CLASSA_PHASE3_CYC_SHADOWED @ 0x4c4

Duration of escalation phase 3 for Class A.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSA_REGWEN
31302928272625242322212019181716
CLASSA_PHASE3_CYC_SHADOWED...
1514131211109876543210
...CLASSA_PHASE3_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSA_PHASE3_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSA_REGWEN is false.


alert_handler.CLASSA_ESC_CNT @ 0x4c8

Escalation counter in cycles for Class A.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
CLASSA_ESC_CNT...
1514131211109876543210
...CLASSA_ESC_CNT
BitsTypeResetNameDescription
31:0roxCLASSA_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSA_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSA_CLR_SHADOWED. Note however that has no effect if CLASSA_REGWEN is set to false (either by SW or by HW via the CLASSA_CTRL_SHADOWED.LOCK feature).


alert_handler.CLASSA_STATE @ 0x4cc

Current escalation state of Class A. See also CLASSA_ESC_CNT.

Reset default = 0x0, mask 0x7
31302928272625242322212019181716
 
1514131211109876543210
  CLASSA_STATE
BitsTypeResetNameDescription
2:0roxCLASSA_STATE
0x0Idle

No timeout or escalation triggered.

0x1Timeout

IRQ timeout counter is active.

0x2FsmError

Terminal error state if FSM has been glitched.

0x3Terminal

Terminal state after escalation protocol.

0x4Phase0

Escalation Phase0 is active.

0x5Phase1

Escalation Phase1 is active.

0x6Phase2

Escalation Phase2 is active.

0x7Phase3

Escalation Phase3 is active.


alert_handler.CLASSB_REGWEN @ 0x4d0

Lock bit for Class B configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  CLASSB_REGWEN
BitsTypeResetNameDescription
0rw0c0x1CLASSB_REGWEN

Class configuration enable bit. If this is cleared to 0, the corresponding class configuration registers cannot be written anymore.


alert_handler.CLASSB_CTRL_SHADOWED @ 0x4d4

Escalation control register for alert Class B. Can not be modified if CLASSB_REGWEN is false.

Reset default = 0x393c, mask 0x3fff
Register enable = CLASSB_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  MAP_E3 MAP_E2 MAP_E1 MAP_E0 EN_E3 EN_E2 EN_E1 EN_E0 LOCK EN
BitsTypeResetNameDescription
0rw0x0EN

Enable escalation mechanisms (accumulation and interrupt timeout) for Class B. Note that interrupts can fire regardless of whether the escalation mechanisms are enabled for this class or not.

1rw0x0LOCK

Enable automatic locking of escalation counter for class B. If true, there is no way to stop the escalation protocol for class B once it has been triggered.

2rw0x1EN_E0

Enable escalation signal 0 for Class B

3rw0x1EN_E1

Enable escalation signal 1 for Class B

4rw0x1EN_E2

Enable escalation signal 2 for Class B

5rw0x1EN_E3

Enable escalation signal 3 for Class B

7:6rw0x0MAP_E0

Determines in which escalation phase escalation signal 0 shall be asserted.

9:8rw0x1MAP_E1

Determines in which escalation phase escalation signal 1 shall be asserted.

11:10rw0x2MAP_E2

Determines in which escalation phase escalation signal 2 shall be asserted.

13:12rw0x3MAP_E3

Determines in which escalation phase escalation signal 3 shall be asserted.


alert_handler.CLASSB_CLR_REGWEN @ 0x4d8

Clear enable for escalation protocol of Class B alerts.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  CLASSB_CLR_REGWEN
BitsTypeResetNameDescription
0rw0c0x1CLASSB_CLR_REGWEN

Register defaults to true, can only be cleared. This register is set to false by the hardware if the escalation protocol has been triggered and the bit CLASSB_CTRL_SHADOWED.LOCK is true.


alert_handler.CLASSB_CLR_SHADOWED @ 0x4dc

Clear for escalation protocol of Class B.

Reset default = 0x0, mask 0x1
Register enable = CLASSB_CLR_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  CLASSB_CLR_SHADOWED
BitsTypeResetNameDescription
0rw0x0CLASSB_CLR_SHADOWED

Writing 1 to this register clears the accumulator and aborts escalation (if it has been triggered). This clear is disabled if CLASSB_CLR_REGWEN is false.


alert_handler.CLASSB_ACCUM_CNT @ 0x4e0

Current accumulation value for alert Class B. Software can clear this register with a write to CLASSB_CLR_SHADOWED register unless CLASSB_CLR_REGWEN is false.

Reset default = 0x0, mask 0xffff
31302928272625242322212019181716
 
1514131211109876543210
CLASSB_ACCUM_CNT
BitsTypeResetNameDescription
15:0roxCLASSB_ACCUM_CNT

alert_handler.CLASSB_ACCUM_THRESH_SHADOWED @ 0x4e4

Accumulation threshold value for alert Class B.

Reset default = 0x0, mask 0xffff
Register enable = CLASSB_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
CLASSB_ACCUM_THRESH_SHADOWED
BitsTypeResetNameDescription
15:0rw0x0CLASSB_ACCUM_THRESH_SHADOWED

Once the accumulation value register is equal to the threshold escalation will be triggered on the next alert occurrence within this class B begins. Note that this register can not be modified if CLASSB_REGWEN is false.


alert_handler.CLASSB_TIMEOUT_CYC_SHADOWED @ 0x4e8

Interrupt timeout in cycles.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSB_REGWEN
31302928272625242322212019181716
CLASSB_TIMEOUT_CYC_SHADOWED...
1514131211109876543210
...CLASSB_TIMEOUT_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSB_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class B. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSB_REGWEN is false.


alert_handler.CLASSB_CRASHDUMP_TRIGGER_SHADOWED @ 0x4ec

Crashdump trigger configuration for Class B.

Reset default = 0x0, mask 0x3
Register enable = CLASSB_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  CLASSB_CRASHDUMP_TRIGGER_SHADOWED
BitsTypeResetNameDescription
1:0rw0x0CLASSB_CRASHDUMP_TRIGGER_SHADOWED

Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation timer states. It is recommended to capture the crashdump upon entering the first escalation phase that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order to prevent spurious alert events from masking the original alert causes. Note that this register can not be modified if CLASSB_REGWEN is false.


alert_handler.CLASSB_PHASE0_CYC_SHADOWED @ 0x4f0

Duration of escalation phase 0 for Class B.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSB_REGWEN
31302928272625242322212019181716
CLASSB_PHASE0_CYC_SHADOWED...
1514131211109876543210
...CLASSB_PHASE0_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSB_PHASE0_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSB_REGWEN is false.


alert_handler.CLASSB_PHASE1_CYC_SHADOWED @ 0x4f4

Duration of escalation phase 1 for Class B.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSB_REGWEN
31302928272625242322212019181716
CLASSB_PHASE1_CYC_SHADOWED...
1514131211109876543210
...CLASSB_PHASE1_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSB_PHASE1_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSB_REGWEN is false.


alert_handler.CLASSB_PHASE2_CYC_SHADOWED @ 0x4f8

Duration of escalation phase 2 for Class B.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSB_REGWEN
31302928272625242322212019181716
CLASSB_PHASE2_CYC_SHADOWED...
1514131211109876543210
...CLASSB_PHASE2_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSB_PHASE2_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSB_REGWEN is false.


alert_handler.CLASSB_PHASE3_CYC_SHADOWED @ 0x4fc

Duration of escalation phase 3 for Class B.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSB_REGWEN
31302928272625242322212019181716
CLASSB_PHASE3_CYC_SHADOWED...
1514131211109876543210
...CLASSB_PHASE3_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSB_PHASE3_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSB_REGWEN is false.


alert_handler.CLASSB_ESC_CNT @ 0x500

Escalation counter in cycles for Class B.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
CLASSB_ESC_CNT...
1514131211109876543210
...CLASSB_ESC_CNT
BitsTypeResetNameDescription
31:0roxCLASSB_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSB_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSB_CLR_SHADOWED. Note however that has no effect if CLASSB_REGWEN is set to false (either by SW or by HW via the CLASSB_CTRL_SHADOWED.LOCK feature).


alert_handler.CLASSB_STATE @ 0x504

Current escalation state of Class B. See also CLASSB_ESC_CNT.

Reset default = 0x0, mask 0x7
31302928272625242322212019181716
 
1514131211109876543210
  CLASSB_STATE
BitsTypeResetNameDescription
2:0roxCLASSB_STATE
0x0Idle

No timeout or escalation triggered.

0x1Timeout

IRQ timeout counter is active.

0x2FsmError

Terminal error state if FSM has been glitched.

0x3Terminal

Terminal state after escalation protocol.

0x4Phase0

Escalation Phase0 is active.

0x5Phase1

Escalation Phase1 is active.

0x6Phase2

Escalation Phase2 is active.

0x7Phase3

Escalation Phase3 is active.


alert_handler.CLASSC_REGWEN @ 0x508

Lock bit for Class C configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  CLASSC_REGWEN
BitsTypeResetNameDescription
0rw0c0x1CLASSC_REGWEN

Class configuration enable bit. If this is cleared to 0, the corresponding class configuration registers cannot be written anymore.


alert_handler.CLASSC_CTRL_SHADOWED @ 0x50c

Escalation control register for alert Class C. Can not be modified if CLASSC_REGWEN is false.

Reset default = 0x393c, mask 0x3fff
Register enable = CLASSC_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  MAP_E3 MAP_E2 MAP_E1 MAP_E0 EN_E3 EN_E2 EN_E1 EN_E0 LOCK EN
BitsTypeResetNameDescription
0rw0x0EN

Enable escalation mechanisms (accumulation and interrupt timeout) for Class C. Note that interrupts can fire regardless of whether the escalation mechanisms are enabled for this class or not.

1rw0x0LOCK

Enable automatic locking of escalation counter for class C. If true, there is no way to stop the escalation protocol for class C once it has been triggered.

2rw0x1EN_E0

Enable escalation signal 0 for Class C

3rw0x1EN_E1

Enable escalation signal 1 for Class C

4rw0x1EN_E2

Enable escalation signal 2 for Class C

5rw0x1EN_E3

Enable escalation signal 3 for Class C

7:6rw0x0MAP_E0

Determines in which escalation phase escalation signal 0 shall be asserted.

9:8rw0x1MAP_E1

Determines in which escalation phase escalation signal 1 shall be asserted.

11:10rw0x2MAP_E2

Determines in which escalation phase escalation signal 2 shall be asserted.

13:12rw0x3MAP_E3

Determines in which escalation phase escalation signal 3 shall be asserted.


alert_handler.CLASSC_CLR_REGWEN @ 0x510

Clear enable for escalation protocol of Class C alerts.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  CLASSC_CLR_REGWEN
BitsTypeResetNameDescription
0rw0c0x1CLASSC_CLR_REGWEN

Register defaults to true, can only be cleared. This register is set to false by the hardware if the escalation protocol has been triggered and the bit CLASSC_CTRL_SHADOWED.LOCK is true.


alert_handler.CLASSC_CLR_SHADOWED @ 0x514

Clear for escalation protocol of Class C.

Reset default = 0x0, mask 0x1
Register enable = CLASSC_CLR_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  CLASSC_CLR_SHADOWED
BitsTypeResetNameDescription
0rw0x0CLASSC_CLR_SHADOWED

Writing 1 to this register clears the accumulator and aborts escalation (if it has been triggered). This clear is disabled if CLASSC_CLR_REGWEN is false.


alert_handler.CLASSC_ACCUM_CNT @ 0x518

Current accumulation value for alert Class C. Software can clear this register with a write to CLASSC_CLR_SHADOWED register unless CLASSC_CLR_REGWEN is false.

Reset default = 0x0, mask 0xffff
31302928272625242322212019181716
 
1514131211109876543210
CLASSC_ACCUM_CNT
BitsTypeResetNameDescription
15:0roxCLASSC_ACCUM_CNT

alert_handler.CLASSC_ACCUM_THRESH_SHADOWED @ 0x51c

Accumulation threshold value for alert Class C.

Reset default = 0x0, mask 0xffff
Register enable = CLASSC_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
CLASSC_ACCUM_THRESH_SHADOWED
BitsTypeResetNameDescription
15:0rw0x0CLASSC_ACCUM_THRESH_SHADOWED

Once the accumulation value register is equal to the threshold escalation will be triggered on the next alert occurrence within this class C begins. Note that this register can not be modified if CLASSC_REGWEN is false.


alert_handler.CLASSC_TIMEOUT_CYC_SHADOWED @ 0x520

Interrupt timeout in cycles.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSC_REGWEN
31302928272625242322212019181716
CLASSC_TIMEOUT_CYC_SHADOWED...
1514131211109876543210
...CLASSC_TIMEOUT_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSC_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class C. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSC_REGWEN is false.


alert_handler.CLASSC_CRASHDUMP_TRIGGER_SHADOWED @ 0x524

Crashdump trigger configuration for Class C.

Reset default = 0x0, mask 0x3
Register enable = CLASSC_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  CLASSC_CRASHDUMP_TRIGGER_SHADOWED
BitsTypeResetNameDescription
1:0rw0x0CLASSC_CRASHDUMP_TRIGGER_SHADOWED

Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation timer states. It is recommended to capture the crashdump upon entering the first escalation phase that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order to prevent spurious alert events from masking the original alert causes. Note that this register can not be modified if CLASSC_REGWEN is false.


alert_handler.CLASSC_PHASE0_CYC_SHADOWED @ 0x528

Duration of escalation phase 0 for Class C.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSC_REGWEN
31302928272625242322212019181716
CLASSC_PHASE0_CYC_SHADOWED...
1514131211109876543210
...CLASSC_PHASE0_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSC_PHASE0_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSC_REGWEN is false.


alert_handler.CLASSC_PHASE1_CYC_SHADOWED @ 0x52c

Duration of escalation phase 1 for Class C.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSC_REGWEN
31302928272625242322212019181716
CLASSC_PHASE1_CYC_SHADOWED...
1514131211109876543210
...CLASSC_PHASE1_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSC_PHASE1_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSC_REGWEN is false.


alert_handler.CLASSC_PHASE2_CYC_SHADOWED @ 0x530

Duration of escalation phase 2 for Class C.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSC_REGWEN
31302928272625242322212019181716
CLASSC_PHASE2_CYC_SHADOWED...
1514131211109876543210
...CLASSC_PHASE2_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSC_PHASE2_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSC_REGWEN is false.


alert_handler.CLASSC_PHASE3_CYC_SHADOWED @ 0x534

Duration of escalation phase 3 for Class C.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSC_REGWEN
31302928272625242322212019181716
CLASSC_PHASE3_CYC_SHADOWED...
1514131211109876543210
...CLASSC_PHASE3_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSC_PHASE3_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSC_REGWEN is false.


alert_handler.CLASSC_ESC_CNT @ 0x538

Escalation counter in cycles for Class C.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
CLASSC_ESC_CNT...
1514131211109876543210
...CLASSC_ESC_CNT
BitsTypeResetNameDescription
31:0roxCLASSC_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSC_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSC_CLR_SHADOWED. Note however that has no effect if CLASSC_REGWEN is set to false (either by SW or by HW via the CLASSC_CTRL_SHADOWED.LOCK feature).


alert_handler.CLASSC_STATE @ 0x53c

Current escalation state of Class C. See also CLASSC_ESC_CNT.

Reset default = 0x0, mask 0x7
31302928272625242322212019181716
 
1514131211109876543210
  CLASSC_STATE
BitsTypeResetNameDescription
2:0roxCLASSC_STATE
0x0Idle

No timeout or escalation triggered.

0x1Timeout

IRQ timeout counter is active.

0x2FsmError

Terminal error state if FSM has been glitched.

0x3Terminal

Terminal state after escalation protocol.

0x4Phase0

Escalation Phase0 is active.

0x5Phase1

Escalation Phase1 is active.

0x6Phase2

Escalation Phase2 is active.

0x7Phase3

Escalation Phase3 is active.


alert_handler.CLASSD_REGWEN @ 0x540

Lock bit for Class D configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  CLASSD_REGWEN
BitsTypeResetNameDescription
0rw0c0x1CLASSD_REGWEN

Class configuration enable bit. If this is cleared to 0, the corresponding class configuration registers cannot be written anymore.


alert_handler.CLASSD_CTRL_SHADOWED @ 0x544

Escalation control register for alert Class D. Can not be modified if CLASSD_REGWEN is false.

Reset default = 0x393c, mask 0x3fff
Register enable = CLASSD_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  MAP_E3 MAP_E2 MAP_E1 MAP_E0 EN_E3 EN_E2 EN_E1 EN_E0 LOCK EN
BitsTypeResetNameDescription
0rw0x0EN

Enable escalation mechanisms (accumulation and interrupt timeout) for Class D. Note that interrupts can fire regardless of whether the escalation mechanisms are enabled for this class or not.

1rw0x0LOCK

Enable automatic locking of escalation counter for class D. If true, there is no way to stop the escalation protocol for class D once it has been triggered.

2rw0x1EN_E0

Enable escalation signal 0 for Class D

3rw0x1EN_E1

Enable escalation signal 1 for Class D

4rw0x1EN_E2

Enable escalation signal 2 for Class D

5rw0x1EN_E3

Enable escalation signal 3 for Class D

7:6rw0x0MAP_E0

Determines in which escalation phase escalation signal 0 shall be asserted.

9:8rw0x1MAP_E1

Determines in which escalation phase escalation signal 1 shall be asserted.

11:10rw0x2MAP_E2

Determines in which escalation phase escalation signal 2 shall be asserted.

13:12rw0x3MAP_E3

Determines in which escalation phase escalation signal 3 shall be asserted.


alert_handler.CLASSD_CLR_REGWEN @ 0x548

Clear enable for escalation protocol of Class D alerts.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  CLASSD_CLR_REGWEN
BitsTypeResetNameDescription
0rw0c0x1CLASSD_CLR_REGWEN

Register defaults to true, can only be cleared. This register is set to false by the hardware if the escalation protocol has been triggered and the bit CLASSD_CTRL_SHADOWED.LOCK is true.


alert_handler.CLASSD_CLR_SHADOWED @ 0x54c

Clear for escalation protocol of Class D.

Reset default = 0x0, mask 0x1
Register enable = CLASSD_CLR_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  CLASSD_CLR_SHADOWED
BitsTypeResetNameDescription
0rw0x0CLASSD_CLR_SHADOWED

Writing 1 to this register clears the accumulator and aborts escalation (if it has been triggered). This clear is disabled if CLASSD_CLR_REGWEN is false.


alert_handler.CLASSD_ACCUM_CNT @ 0x550

Current accumulation value for alert Class D. Software can clear this register with a write to CLASSD_CLR_SHADOWED register unless CLASSD_CLR_REGWEN is false.

Reset default = 0x0, mask 0xffff
31302928272625242322212019181716
 
1514131211109876543210
CLASSD_ACCUM_CNT
BitsTypeResetNameDescription
15:0roxCLASSD_ACCUM_CNT

alert_handler.CLASSD_ACCUM_THRESH_SHADOWED @ 0x554

Accumulation threshold value for alert Class D.

Reset default = 0x0, mask 0xffff
Register enable = CLASSD_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
CLASSD_ACCUM_THRESH_SHADOWED
BitsTypeResetNameDescription
15:0rw0x0CLASSD_ACCUM_THRESH_SHADOWED

Once the accumulation value register is equal to the threshold escalation will be triggered on the next alert occurrence within this class D begins. Note that this register can not be modified if CLASSD_REGWEN is false.


alert_handler.CLASSD_TIMEOUT_CYC_SHADOWED @ 0x558

Interrupt timeout in cycles.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSD_REGWEN
31302928272625242322212019181716
CLASSD_TIMEOUT_CYC_SHADOWED...
1514131211109876543210
...CLASSD_TIMEOUT_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSD_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class D. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSD_REGWEN is false.


alert_handler.CLASSD_CRASHDUMP_TRIGGER_SHADOWED @ 0x55c

Crashdump trigger configuration for Class D.

Reset default = 0x0, mask 0x3
Register enable = CLASSD_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  CLASSD_CRASHDUMP_TRIGGER_SHADOWED
BitsTypeResetNameDescription
1:0rw0x0CLASSD_CRASHDUMP_TRIGGER_SHADOWED

Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation timer states. It is recommended to capture the crashdump upon entering the first escalation phase that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order to prevent spurious alert events from masking the original alert causes. Note that this register can not be modified if CLASSD_REGWEN is false.


alert_handler.CLASSD_PHASE0_CYC_SHADOWED @ 0x560

Duration of escalation phase 0 for Class D.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSD_REGWEN
31302928272625242322212019181716
CLASSD_PHASE0_CYC_SHADOWED...
1514131211109876543210
...CLASSD_PHASE0_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSD_PHASE0_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSD_REGWEN is false.


alert_handler.CLASSD_PHASE1_CYC_SHADOWED @ 0x564

Duration of escalation phase 1 for Class D.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSD_REGWEN
31302928272625242322212019181716
CLASSD_PHASE1_CYC_SHADOWED...
1514131211109876543210
...CLASSD_PHASE1_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSD_PHASE1_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSD_REGWEN is false.


alert_handler.CLASSD_PHASE2_CYC_SHADOWED @ 0x568

Duration of escalation phase 2 for Class D.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSD_REGWEN
31302928272625242322212019181716
CLASSD_PHASE2_CYC_SHADOWED...
1514131211109876543210
...CLASSD_PHASE2_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSD_PHASE2_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSD_REGWEN is false.


alert_handler.CLASSD_PHASE3_CYC_SHADOWED @ 0x56c

Duration of escalation phase 3 for Class D.

Reset default = 0x0, mask 0xffffffff
Register enable = CLASSD_REGWEN
31302928272625242322212019181716
CLASSD_PHASE3_CYC_SHADOWED...
1514131211109876543210
...CLASSD_PHASE3_CYC_SHADOWED
BitsTypeResetNameDescription
31:0rw0x0CLASSD_PHASE3_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSD_REGWEN is false.


alert_handler.CLASSD_ESC_CNT @ 0x570

Escalation counter in cycles for Class D.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
CLASSD_ESC_CNT...
1514131211109876543210
...CLASSD_ESC_CNT
BitsTypeResetNameDescription
31:0roxCLASSD_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSD_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSD_CLR_SHADOWED. Note however that has no effect if CLASSD_REGWEN is set to false (either by SW or by HW via the CLASSD_CTRL_SHADOWED.LOCK feature).


alert_handler.CLASSD_STATE @ 0x574

Current escalation state of Class D. See also CLASSD_ESC_CNT.

Reset default = 0x0, mask 0x7
31302928272625242322212019181716
 
1514131211109876543210
  CLASSD_STATE
BitsTypeResetNameDescription
2:0roxCLASSD_STATE
0x0Idle

No timeout or escalation triggered.

0x1Timeout

IRQ timeout counter is active.

0x2FsmError

Terminal error state if FSM has been glitched.

0x3Terminal

Terminal state after escalation protocol.

0x4Phase0

Escalation Phase0 is active.

0x5Phase1

Escalation Phase1 is active.

0x6Phase2

Escalation Phase2 is active.

0x7Phase3

Escalation Phase3 is active.