Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module alert_handler has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: clk_edn_i
  • Bus Device Interfaces (TL-UL): tl
  • Bus Host Interfaces (TL-UL): none
  • Peripheral Pins for Chip IO: none
  • Security Alerts: none

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription
crashdumpalert_pkg::alert_crashdumpunireq1
ednedn_pkg::ednreq_rspreq1
esc_rxprim_esc_pkg::esc_rxunircv4
esc_txprim_esc_pkg::esc_txunireq4
tltlul_pkg::tlreq_rsprsp1

Interrupts

Interrupt NameTypeDescription
classaEventInterrupt state bit of Class A. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
classbEventInterrupt state bit of Class B. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
classcEventInterrupt state bit of Class C. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
classdEventInterrupt state bit of Class D. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.

Security Countermeasures

Countermeasure IDDescription
ALERT_HANDLER.BUS.INTEGRITYEnd-to-end bus integrity scheme.
ALERT_HANDLER.CONFIG.SHADOWImportant CSRs are shadowed.
ALERT_HANDLER.PING_TIMER.CONFIG.REGWENThe ping timer configuration registers are REGWEN protected.
ALERT_HANDLER.ALERT.CONFIG.REGWENThe individual alert enables are REGWEN protected.
ALERT_HANDLER.ALERT_LOC.CONFIG.REGWENThe individual local alert enables are REGWEN protected.
ALERT_HANDLER.CLASS.CONFIG.REGWENThe class configuration registers are REGWEN protected.
ALERT_HANDLER.ALERT.INTERSIG.DIFFDifferentially encoded alert channels.
ALERT_HANDLER.LPG.INTERSIG.MUBILPG signals are encoded with MUBI types.
ALERT_HANDLER.ESC.INTERSIG.DIFFDifferentially encoded escalation channels.
ALERT_HANDLER.ALERT_RX.INTERSIG.BKGN_CHKPeriodic background checks on alert channels (ping mechanism).
ALERT_HANDLER.ESC_TX.INTERSIG.BKGN_CHKPeriodic background checks on escalation channels (ping mechanism).
ALERT_HANDLER.ESC_RX.INTERSIG.BKGN_CHKEscalation receivers can detect absence of periodic ping requests.
ALERT_HANDLER.ESC_TIMER.FSM.SPARSEEscalation timer FSMs are sparsely encoded.
ALERT_HANDLER.PING_TIMER.FSM.SPARSEPing timer FSM is sparsely encoded.
ALERT_HANDLER.ESC_TIMER.FSM.LOCAL_ESCEscalation timer FSMs move into an invalid state upon local escalation.
ALERT_HANDLER.PING_TIMER.FSM.LOCAL_ESCPing timer FSM moves into an invalid state upon local escalation.
ALERT_HANDLER.ESC_TIMER.FSM.GLOBAL_ESCThe escalation timer FSMs are the root of global escalation, hence if any of them moves into an invalid state by virtue of ESC_TIMER.FSM.LOCAL_ESC, this will trigger all escalation actions and thereby global escalation as well.
ALERT_HANDLER.ACCU.CTR.REDUNAccumulator counters employ a cross-counter implementation.
ALERT_HANDLER.ESC_TIMER.CTR.REDUNEscalation timer counters employ a duplicated counter implementation.
ALERT_HANDLER.PING_TIMER.CTR.REDUNPing timer counters employ a duplicated counter implementation.
ALERT_HANDLER.PING_TIMER.LFSR.REDUNPing timer LFSR is redundant.

Registers

Summary

NameOffsetLengthDescription
alert_handler.INTR_STATE0x04Interrupt State Register
alert_handler.INTR_ENABLE0x44Interrupt Enable Register
alert_handler.INTR_TEST0x84Interrupt Test Register
alert_handler.PING_TIMER_REGWEN0xc4Register write enable for !!PING_TIMEOUT_CYC_SHADOWED and !!PING_TIMER_EN_SHADOWED.
alert_handler.PING_TIMEOUT_CYC_SHADOWED0x104Ping timeout cycle count.
alert_handler.PING_TIMER_EN_SHADOWED0x144Ping timer enable.
alert_handler.ALERT_REGWEN_00x184Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_10x1c4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_20x204Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_30x244Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_40x284Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_50x2c4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_60x304Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_70x344Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_80x384Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_90x3c4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_100x404Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_110x444Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_120x484Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_130x4c4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_140x504Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_150x544Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_160x584Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_170x5c4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_180x604Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_190x644Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_200x684Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_210x6c4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_220x704Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_230x744Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_240x784Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_250x7c4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_260x804Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_270x844Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_280x884Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_290x8c4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_300x904Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_310x944Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_320x984Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_330x9c4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_340xa04Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_350xa44Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_360xa84Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_370xac4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_380xb04Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_390xb44Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_400xb84Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_410xbc4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_420xc04Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_430xc44Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_440xc84Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_450xcc4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_460xd04Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_470xd44Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_480xd84Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_490xdc4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_500xe04Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_510xe44Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_520xe84Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_530xec4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_540xf04Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_550xf44Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_560xf84Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_570xfc4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_580x1004Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_590x1044Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_600x1084Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_610x10c4Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_620x1104Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_630x1144Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_640x1184Register write enable for alert enable bits.
alert_handler.ALERT_EN_SHADOWED_00x11c4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_10x1204Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_20x1244Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_30x1284Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_40x12c4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_50x1304Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_60x1344Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_70x1384Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_80x13c4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_90x1404Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_100x1444Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_110x1484Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_120x14c4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_130x1504Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_140x1544Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_150x1584Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_160x15c4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_170x1604Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_180x1644Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_190x1684Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_200x16c4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_210x1704Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_220x1744Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_230x1784Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_240x17c4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_250x1804Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_260x1844Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_270x1884Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_280x18c4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_290x1904Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_300x1944Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_310x1984Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_320x19c4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_330x1a04Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_340x1a44Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_350x1a84Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_360x1ac4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_370x1b04Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_380x1b44Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_390x1b84Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_400x1bc4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_410x1c04Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_420x1c44Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_430x1c84Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_440x1cc4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_450x1d04Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_460x1d44Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_470x1d84Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_480x1dc4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_490x1e04Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_500x1e44Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_510x1e84Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_520x1ec4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_530x1f04Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_540x1f44Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_550x1f84Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_560x1fc4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_570x2004Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_580x2044Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_590x2084Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_600x20c4Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_610x2104Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_620x2144Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_630x2184Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_640x21c4Enable register for alerts.
alert_handler.ALERT_CLASS_SHADOWED_00x2204Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_10x2244Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_20x2284Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_30x22c4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_40x2304Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_50x2344Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_60x2384Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_70x23c4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_80x2404Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_90x2444Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_100x2484Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_110x24c4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_120x2504Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_130x2544Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_140x2584Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_150x25c4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_160x2604Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_170x2644Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_180x2684Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_190x26c4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_200x2704Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_210x2744Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_220x2784Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_230x27c4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_240x2804Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_250x2844Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_260x2884Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_270x28c4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_280x2904Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_290x2944Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_300x2984Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_310x29c4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_320x2a04Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_330x2a44Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_340x2a84Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_350x2ac4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_360x2b04Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_370x2b44Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_380x2b84Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_390x2bc4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_400x2c04Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_410x2c44Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_420x2c84Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_430x2cc4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_440x2d04Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_450x2d44Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_460x2d84Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_470x2dc4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_480x2e04Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_490x2e44Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_500x2e84Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_510x2ec4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_520x2f04Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_530x2f44Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_540x2f84Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_550x2fc4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_560x3004Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_570x3044Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_580x3084Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_590x30c4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_600x3104Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_610x3144Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_620x3184Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_630x31c4Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_640x3204Class assignment of alerts.
alert_handler.ALERT_CAUSE_00x3244Alert Cause Register
alert_handler.ALERT_CAUSE_10x3284Alert Cause Register
alert_handler.ALERT_CAUSE_20x32c4Alert Cause Register
alert_handler.ALERT_CAUSE_30x3304Alert Cause Register
alert_handler.ALERT_CAUSE_40x3344Alert Cause Register
alert_handler.ALERT_CAUSE_50x3384Alert Cause Register
alert_handler.ALERT_CAUSE_60x33c4Alert Cause Register
alert_handler.ALERT_CAUSE_70x3404Alert Cause Register
alert_handler.ALERT_CAUSE_80x3444Alert Cause Register
alert_handler.ALERT_CAUSE_90x3484Alert Cause Register
alert_handler.ALERT_CAUSE_100x34c4Alert Cause Register
alert_handler.ALERT_CAUSE_110x3504Alert Cause Register
alert_handler.ALERT_CAUSE_120x3544Alert Cause Register
alert_handler.ALERT_CAUSE_130x3584Alert Cause Register
alert_handler.ALERT_CAUSE_140x35c4Alert Cause Register
alert_handler.ALERT_CAUSE_150x3604Alert Cause Register
alert_handler.ALERT_CAUSE_160x3644Alert Cause Register
alert_handler.ALERT_CAUSE_170x3684Alert Cause Register
alert_handler.ALERT_CAUSE_180x36c4Alert Cause Register
alert_handler.ALERT_CAUSE_190x3704Alert Cause Register
alert_handler.ALERT_CAUSE_200x3744Alert Cause Register
alert_handler.ALERT_CAUSE_210x3784Alert Cause Register
alert_handler.ALERT_CAUSE_220x37c4Alert Cause Register
alert_handler.ALERT_CAUSE_230x3804Alert Cause Register
alert_handler.ALERT_CAUSE_240x3844Alert Cause Register
alert_handler.ALERT_CAUSE_250x3884Alert Cause Register
alert_handler.ALERT_CAUSE_260x38c4Alert Cause Register
alert_handler.ALERT_CAUSE_270x3904Alert Cause Register
alert_handler.ALERT_CAUSE_280x3944Alert Cause Register
alert_handler.ALERT_CAUSE_290x3984Alert Cause Register
alert_handler.ALERT_CAUSE_300x39c4Alert Cause Register
alert_handler.ALERT_CAUSE_310x3a04Alert Cause Register
alert_handler.ALERT_CAUSE_320x3a44Alert Cause Register
alert_handler.ALERT_CAUSE_330x3a84Alert Cause Register
alert_handler.ALERT_CAUSE_340x3ac4Alert Cause Register
alert_handler.ALERT_CAUSE_350x3b04Alert Cause Register
alert_handler.ALERT_CAUSE_360x3b44Alert Cause Register
alert_handler.ALERT_CAUSE_370x3b84Alert Cause Register
alert_handler.ALERT_CAUSE_380x3bc4Alert Cause Register
alert_handler.ALERT_CAUSE_390x3c04Alert Cause Register
alert_handler.ALERT_CAUSE_400x3c44Alert Cause Register
alert_handler.ALERT_CAUSE_410x3c84Alert Cause Register
alert_handler.ALERT_CAUSE_420x3cc4Alert Cause Register
alert_handler.ALERT_CAUSE_430x3d04Alert Cause Register
alert_handler.ALERT_CAUSE_440x3d44Alert Cause Register
alert_handler.ALERT_CAUSE_450x3d84Alert Cause Register
alert_handler.ALERT_CAUSE_460x3dc4Alert Cause Register
alert_handler.ALERT_CAUSE_470x3e04Alert Cause Register
alert_handler.ALERT_CAUSE_480x3e44Alert Cause Register
alert_handler.ALERT_CAUSE_490x3e84Alert Cause Register
alert_handler.ALERT_CAUSE_500x3ec4Alert Cause Register
alert_handler.ALERT_CAUSE_510x3f04Alert Cause Register
alert_handler.ALERT_CAUSE_520x3f44Alert Cause Register
alert_handler.ALERT_CAUSE_530x3f84Alert Cause Register
alert_handler.ALERT_CAUSE_540x3fc4Alert Cause Register
alert_handler.ALERT_CAUSE_550x4004Alert Cause Register
alert_handler.ALERT_CAUSE_560x4044Alert Cause Register
alert_handler.ALERT_CAUSE_570x4084Alert Cause Register
alert_handler.ALERT_CAUSE_580x40c4Alert Cause Register
alert_handler.ALERT_CAUSE_590x4104Alert Cause Register
alert_handler.ALERT_CAUSE_600x4144Alert Cause Register
alert_handler.ALERT_CAUSE_610x4184Alert Cause Register
alert_handler.ALERT_CAUSE_620x41c4Alert Cause Register
alert_handler.ALERT_CAUSE_630x4204Alert Cause Register
alert_handler.ALERT_CAUSE_640x4244Alert Cause Register
alert_handler.LOC_ALERT_REGWEN_00x4284Register write enable for alert enable bits.
alert_handler.LOC_ALERT_REGWEN_10x42c4Register write enable for alert enable bits.
alert_handler.LOC_ALERT_REGWEN_20x4304Register write enable for alert enable bits.
alert_handler.LOC_ALERT_REGWEN_30x4344Register write enable for alert enable bits.
alert_handler.LOC_ALERT_REGWEN_40x4384Register write enable for alert enable bits.
alert_handler.LOC_ALERT_REGWEN_50x43c4Register write enable for alert enable bits.
alert_handler.LOC_ALERT_REGWEN_60x4404Register write enable for alert enable bits.
alert_handler.LOC_ALERT_EN_SHADOWED_00x4444Enable register for the local alerts
alert_handler.LOC_ALERT_EN_SHADOWED_10x4484Enable register for the local alerts
alert_handler.LOC_ALERT_EN_SHADOWED_20x44c4Enable register for the local alerts
alert_handler.LOC_ALERT_EN_SHADOWED_30x4504Enable register for the local alerts
alert_handler.LOC_ALERT_EN_SHADOWED_40x4544Enable register for the local alerts
alert_handler.LOC_ALERT_EN_SHADOWED_50x4584Enable register for the local alerts
alert_handler.LOC_ALERT_EN_SHADOWED_60x45c4Enable register for the local alerts
alert_handler.LOC_ALERT_CLASS_SHADOWED_00x4604Class assignment of the local alerts
alert_handler.LOC_ALERT_CLASS_SHADOWED_10x4644Class assignment of the local alerts
alert_handler.LOC_ALERT_CLASS_SHADOWED_20x4684Class assignment of the local alerts
alert_handler.LOC_ALERT_CLASS_SHADOWED_30x46c4Class assignment of the local alerts
alert_handler.LOC_ALERT_CLASS_SHADOWED_40x4704Class assignment of the local alerts
alert_handler.LOC_ALERT_CLASS_SHADOWED_50x4744Class assignment of the local alerts
alert_handler.LOC_ALERT_CLASS_SHADOWED_60x4784Class assignment of the local alerts
alert_handler.LOC_ALERT_CAUSE_00x47c4Alert Cause Register for the local alerts
alert_handler.LOC_ALERT_CAUSE_10x4804Alert Cause Register for the local alerts
alert_handler.LOC_ALERT_CAUSE_20x4844Alert Cause Register for the local alerts
alert_handler.LOC_ALERT_CAUSE_30x4884Alert Cause Register for the local alerts
alert_handler.LOC_ALERT_CAUSE_40x48c4Alert Cause Register for the local alerts
alert_handler.LOC_ALERT_CAUSE_50x4904Alert Cause Register for the local alerts
alert_handler.LOC_ALERT_CAUSE_60x4944Alert Cause Register for the local alerts
alert_handler.CLASSA_REGWEN0x4984Lock bit for Class A configuration.
alert_handler.CLASSA_CTRL_SHADOWED0x49c4Escalation control register for alert Class A. Can not be modified if !!CLASSA_REGWEN is false.
alert_handler.CLASSA_CLR_REGWEN0x4a04Clear enable for escalation protocol of Class A alerts.
alert_handler.CLASSA_CLR_SHADOWED0x4a44Clear for escalation protocol of Class A.
alert_handler.CLASSA_ACCUM_CNT0x4a84Current accumulation value for alert Class A. Software can clear this register
alert_handler.CLASSA_ACCUM_THRESH_SHADOWED0x4ac4Accumulation threshold value for alert Class A.
alert_handler.CLASSA_TIMEOUT_CYC_SHADOWED0x4b04Interrupt timeout in cycles.
alert_handler.CLASSA_CRASHDUMP_TRIGGER_SHADOWED0x4b44Crashdump trigger configuration for Class A.
alert_handler.CLASSA_PHASE0_CYC_SHADOWED0x4b84Duration of escalation phase 0 for Class A.
alert_handler.CLASSA_PHASE1_CYC_SHADOWED0x4bc4Duration of escalation phase 1 for Class A.
alert_handler.CLASSA_PHASE2_CYC_SHADOWED0x4c04Duration of escalation phase 2 for Class A.
alert_handler.CLASSA_PHASE3_CYC_SHADOWED0x4c44Duration of escalation phase 3 for Class A.
alert_handler.CLASSA_ESC_CNT0x4c84Escalation counter in cycles for Class A.
alert_handler.CLASSA_STATE0x4cc4Current escalation state of Class A. See also !!CLASSA_ESC_CNT.
alert_handler.CLASSB_REGWEN0x4d04Lock bit for Class B configuration.
alert_handler.CLASSB_CTRL_SHADOWED0x4d44Escalation control register for alert Class B. Can not be modified if !!CLASSB_REGWEN is false.
alert_handler.CLASSB_CLR_REGWEN0x4d84Clear enable for escalation protocol of Class B alerts.
alert_handler.CLASSB_CLR_SHADOWED0x4dc4Clear for escalation protocol of Class B.
alert_handler.CLASSB_ACCUM_CNT0x4e04Current accumulation value for alert Class B. Software can clear this register
alert_handler.CLASSB_ACCUM_THRESH_SHADOWED0x4e44Accumulation threshold value for alert Class B.
alert_handler.CLASSB_TIMEOUT_CYC_SHADOWED0x4e84Interrupt timeout in cycles.
alert_handler.CLASSB_CRASHDUMP_TRIGGER_SHADOWED0x4ec4Crashdump trigger configuration for Class B.
alert_handler.CLASSB_PHASE0_CYC_SHADOWED0x4f04Duration of escalation phase 0 for Class B.
alert_handler.CLASSB_PHASE1_CYC_SHADOWED0x4f44Duration of escalation phase 1 for Class B.
alert_handler.CLASSB_PHASE2_CYC_SHADOWED0x4f84Duration of escalation phase 2 for Class B.
alert_handler.CLASSB_PHASE3_CYC_SHADOWED0x4fc4Duration of escalation phase 3 for Class B.
alert_handler.CLASSB_ESC_CNT0x5004Escalation counter in cycles for Class B.
alert_handler.CLASSB_STATE0x5044Current escalation state of Class B. See also !!CLASSB_ESC_CNT.
alert_handler.CLASSC_REGWEN0x5084Lock bit for Class C configuration.
alert_handler.CLASSC_CTRL_SHADOWED0x50c4Escalation control register for alert Class C. Can not be modified if !!CLASSC_REGWEN is false.
alert_handler.CLASSC_CLR_REGWEN0x5104Clear enable for escalation protocol of Class C alerts.
alert_handler.CLASSC_CLR_SHADOWED0x5144Clear for escalation protocol of Class C.
alert_handler.CLASSC_ACCUM_CNT0x5184Current accumulation value for alert Class C. Software can clear this register
alert_handler.CLASSC_ACCUM_THRESH_SHADOWED0x51c4Accumulation threshold value for alert Class C.
alert_handler.CLASSC_TIMEOUT_CYC_SHADOWED0x5204Interrupt timeout in cycles.
alert_handler.CLASSC_CRASHDUMP_TRIGGER_SHADOWED0x5244Crashdump trigger configuration for Class C.
alert_handler.CLASSC_PHASE0_CYC_SHADOWED0x5284Duration of escalation phase 0 for Class C.
alert_handler.CLASSC_PHASE1_CYC_SHADOWED0x52c4Duration of escalation phase 1 for Class C.
alert_handler.CLASSC_PHASE2_CYC_SHADOWED0x5304Duration of escalation phase 2 for Class C.
alert_handler.CLASSC_PHASE3_CYC_SHADOWED0x5344Duration of escalation phase 3 for Class C.
alert_handler.CLASSC_ESC_CNT0x5384Escalation counter in cycles for Class C.
alert_handler.CLASSC_STATE0x53c4Current escalation state of Class C. See also !!CLASSC_ESC_CNT.
alert_handler.CLASSD_REGWEN0x5404Lock bit for Class D configuration.
alert_handler.CLASSD_CTRL_SHADOWED0x5444Escalation control register for alert Class D. Can not be modified if !!CLASSD_REGWEN is false.
alert_handler.CLASSD_CLR_REGWEN0x5484Clear enable for escalation protocol of Class D alerts.
alert_handler.CLASSD_CLR_SHADOWED0x54c4Clear for escalation protocol of Class D.
alert_handler.CLASSD_ACCUM_CNT0x5504Current accumulation value for alert Class D. Software can clear this register
alert_handler.CLASSD_ACCUM_THRESH_SHADOWED0x5544Accumulation threshold value for alert Class D.
alert_handler.CLASSD_TIMEOUT_CYC_SHADOWED0x5584Interrupt timeout in cycles.
alert_handler.CLASSD_CRASHDUMP_TRIGGER_SHADOWED0x55c4Crashdump trigger configuration for Class D.
alert_handler.CLASSD_PHASE0_CYC_SHADOWED0x5604Duration of escalation phase 0 for Class D.
alert_handler.CLASSD_PHASE1_CYC_SHADOWED0x5644Duration of escalation phase 1 for Class D.
alert_handler.CLASSD_PHASE2_CYC_SHADOWED0x5684Duration of escalation phase 2 for Class D.
alert_handler.CLASSD_PHASE3_CYC_SHADOWED0x56c4Duration of escalation phase 3 for Class D.
alert_handler.CLASSD_ESC_CNT0x5704Escalation counter in cycles for Class D.
alert_handler.CLASSD_STATE0x5744Current escalation state of Class D. See also !!CLASSD_ESC_CNT.

INTR_STATE

Interrupt State Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

{"reg": [{"name": "classa", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "classb", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "classc", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "classd", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:4Reserved
3rw1c0x0classdInterrupt state bit of Class D. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
2rw1c0x0classcInterrupt state bit of Class C. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
1rw1c0x0classbInterrupt state bit of Class B. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
0rw1c0x0classaInterrupt state bit of Class A. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

{"reg": [{"name": "classa", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "classb", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "classc", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "classd", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:4Reserved
3rw0x0classdEnable interrupt when INTR_STATE.classd is set.
2rw0x0classcEnable interrupt when INTR_STATE.classc is set.
1rw0x0classbEnable interrupt when INTR_STATE.classb is set.
0rw0x0classaEnable interrupt when INTR_STATE.classa is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

{"reg": [{"name": "classa", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "classb", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "classc", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "classd", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:4Reserved
3wo0x0classdWrite 1 to force INTR_STATE.classd to 1.
2wo0x0classcWrite 1 to force INTR_STATE.classc to 1.
1wo0x0classbWrite 1 to force INTR_STATE.classb to 1.
0wo0x0classaWrite 1 to force INTR_STATE.classa to 1.

PING_TIMER_REGWEN

Register write enable for PING_TIMEOUT_CYC_SHADOWED and PING_TIMER_EN_SHADOWED.

  • Offset: 0xc
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

{"reg": [{"name": "PING_TIMER_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
BitsTypeResetName
31:1Reserved
0rw0c0x1PING_TIMER_REGWEN

PING_TIMER_REGWEN . PING_TIMER_REGWEN

When true, the PING_TIMEOUT_CYC_SHADOWED and PING_TIMER_EN_SHADOWED registers can be modified. When false, they become read-only. Defaults true, write one to clear. This should be cleared once the alert handler has been configured and the ping timer mechanism has been kicked off.

PING_TIMEOUT_CYC_SHADOWED

Ping timeout cycle count.

  • Offset: 0x10
  • Reset default: 0x100
  • Reset mask: 0xffff
  • Register enable: PING_TIMER_REGWEN

Fields

{"reg": [{"name": "PING_TIMEOUT_CYC_SHADOWED", "bits": 16, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:16Reserved
15:0rw0x100PING_TIMEOUT_CYC_SHADOWED

PING_TIMEOUT_CYC_SHADOWED . PING_TIMEOUT_CYC_SHADOWED

Timeout value in cycles. If an alert receiver or an escalation sender does not respond to a ping within this timeout window, a pingfail alert will be raised. It is recommended to set this value to the equivalent of 256 cycles of the slowest alert sender clock domain in the system (or greater).

PING_TIMER_EN_SHADOWED

Ping timer enable.

Fields

{"reg": [{"name": "PING_TIMER_EN_SHADOWED", "bits": 1, "attr": ["rw1s"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}
BitsTypeResetNameDescription
31:1Reserved
0rw1s0x0PING_TIMER_EN_SHADOWEDSetting this to 1 enables the ping timer mechanism. This bit cannot be cleared to 0 once it has been set to 1. Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.

ALERT_REGWEN

Register write enable for alert enable bits.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
ALERT_REGWEN_00x18
ALERT_REGWEN_10x1c
ALERT_REGWEN_20x20
ALERT_REGWEN_30x24
ALERT_REGWEN_40x28
ALERT_REGWEN_50x2c
ALERT_REGWEN_60x30
ALERT_REGWEN_70x34
ALERT_REGWEN_80x38
ALERT_REGWEN_90x3c
ALERT_REGWEN_100x40
ALERT_REGWEN_110x44
ALERT_REGWEN_120x48
ALERT_REGWEN_130x4c
ALERT_REGWEN_140x50
ALERT_REGWEN_150x54
ALERT_REGWEN_160x58
ALERT_REGWEN_170x5c
ALERT_REGWEN_180x60
ALERT_REGWEN_190x64
ALERT_REGWEN_200x68
ALERT_REGWEN_210x6c
ALERT_REGWEN_220x70
ALERT_REGWEN_230x74
ALERT_REGWEN_240x78
ALERT_REGWEN_250x7c
ALERT_REGWEN_260x80
ALERT_REGWEN_270x84
ALERT_REGWEN_280x88
ALERT_REGWEN_290x8c
ALERT_REGWEN_300x90
ALERT_REGWEN_310x94
ALERT_REGWEN_320x98
ALERT_REGWEN_330x9c
ALERT_REGWEN_340xa0
ALERT_REGWEN_350xa4
ALERT_REGWEN_360xa8
ALERT_REGWEN_370xac
ALERT_REGWEN_380xb0
ALERT_REGWEN_390xb4
ALERT_REGWEN_400xb8
ALERT_REGWEN_410xbc
ALERT_REGWEN_420xc0
ALERT_REGWEN_430xc4
ALERT_REGWEN_440xc8
ALERT_REGWEN_450xcc
ALERT_REGWEN_460xd0
ALERT_REGWEN_470xd4
ALERT_REGWEN_480xd8
ALERT_REGWEN_490xdc
ALERT_REGWEN_500xe0
ALERT_REGWEN_510xe4
ALERT_REGWEN_520xe8
ALERT_REGWEN_530xec
ALERT_REGWEN_540xf0
ALERT_REGWEN_550xf4
ALERT_REGWEN_560xf8
ALERT_REGWEN_570xfc
ALERT_REGWEN_580x100
ALERT_REGWEN_590x104
ALERT_REGWEN_600x108
ALERT_REGWEN_610x10c
ALERT_REGWEN_620x110
ALERT_REGWEN_630x114
ALERT_REGWEN_640x118

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:1Reserved
0rw0c0x1EN

ALERT_REGWEN . EN

Alert configuration write enable bit. If this is cleared to 0, the corresponding ALERT_EN_SHADOWED and ALERT_CLASS_SHADOWED bits are not writable anymore.

Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.

ALERT_EN_SHADOWED

Enable register for alerts.

  • Reset default: 0x0
  • Reset mask: 0x1

Instances

NameOffset
ALERT_EN_SHADOWED_00x11c
ALERT_EN_SHADOWED_10x120
ALERT_EN_SHADOWED_20x124
ALERT_EN_SHADOWED_30x128
ALERT_EN_SHADOWED_40x12c
ALERT_EN_SHADOWED_50x130
ALERT_EN_SHADOWED_60x134
ALERT_EN_SHADOWED_70x138
ALERT_EN_SHADOWED_80x13c
ALERT_EN_SHADOWED_90x140
ALERT_EN_SHADOWED_100x144
ALERT_EN_SHADOWED_110x148
ALERT_EN_SHADOWED_120x14c
ALERT_EN_SHADOWED_130x150
ALERT_EN_SHADOWED_140x154
ALERT_EN_SHADOWED_150x158
ALERT_EN_SHADOWED_160x15c
ALERT_EN_SHADOWED_170x160
ALERT_EN_SHADOWED_180x164
ALERT_EN_SHADOWED_190x168
ALERT_EN_SHADOWED_200x16c
ALERT_EN_SHADOWED_210x170
ALERT_EN_SHADOWED_220x174
ALERT_EN_SHADOWED_230x178
ALERT_EN_SHADOWED_240x17c
ALERT_EN_SHADOWED_250x180
ALERT_EN_SHADOWED_260x184
ALERT_EN_SHADOWED_270x188
ALERT_EN_SHADOWED_280x18c
ALERT_EN_SHADOWED_290x190
ALERT_EN_SHADOWED_300x194
ALERT_EN_SHADOWED_310x198
ALERT_EN_SHADOWED_320x19c
ALERT_EN_SHADOWED_330x1a0
ALERT_EN_SHADOWED_340x1a4
ALERT_EN_SHADOWED_350x1a8
ALERT_EN_SHADOWED_360x1ac
ALERT_EN_SHADOWED_370x1b0
ALERT_EN_SHADOWED_380x1b4
ALERT_EN_SHADOWED_390x1b8
ALERT_EN_SHADOWED_400x1bc
ALERT_EN_SHADOWED_410x1c0
ALERT_EN_SHADOWED_420x1c4
ALERT_EN_SHADOWED_430x1c8
ALERT_EN_SHADOWED_440x1cc
ALERT_EN_SHADOWED_450x1d0
ALERT_EN_SHADOWED_460x1d4
ALERT_EN_SHADOWED_470x1d8
ALERT_EN_SHADOWED_480x1dc
ALERT_EN_SHADOWED_490x1e0
ALERT_EN_SHADOWED_500x1e4
ALERT_EN_SHADOWED_510x1e8
ALERT_EN_SHADOWED_520x1ec
ALERT_EN_SHADOWED_530x1f0
ALERT_EN_SHADOWED_540x1f4
ALERT_EN_SHADOWED_550x1f8
ALERT_EN_SHADOWED_560x1fc
ALERT_EN_SHADOWED_570x200
ALERT_EN_SHADOWED_580x204
ALERT_EN_SHADOWED_590x208
ALERT_EN_SHADOWED_600x20c
ALERT_EN_SHADOWED_610x210
ALERT_EN_SHADOWED_620x214
ALERT_EN_SHADOWED_630x218
ALERT_EN_SHADOWED_640x21c

Fields

{"reg": [{"name": "EN_A", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw0x0EN_AAlert enable bit. Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.

ALERT_CLASS_SHADOWED

Class assignment of alerts.

  • Reset default: 0x0
  • Reset mask: 0x3

Instances

NameOffset
ALERT_CLASS_SHADOWED_00x220
ALERT_CLASS_SHADOWED_10x224
ALERT_CLASS_SHADOWED_20x228
ALERT_CLASS_SHADOWED_30x22c
ALERT_CLASS_SHADOWED_40x230
ALERT_CLASS_SHADOWED_50x234
ALERT_CLASS_SHADOWED_60x238
ALERT_CLASS_SHADOWED_70x23c
ALERT_CLASS_SHADOWED_80x240
ALERT_CLASS_SHADOWED_90x244
ALERT_CLASS_SHADOWED_100x248
ALERT_CLASS_SHADOWED_110x24c
ALERT_CLASS_SHADOWED_120x250
ALERT_CLASS_SHADOWED_130x254
ALERT_CLASS_SHADOWED_140x258
ALERT_CLASS_SHADOWED_150x25c
ALERT_CLASS_SHADOWED_160x260
ALERT_CLASS_SHADOWED_170x264
ALERT_CLASS_SHADOWED_180x268
ALERT_CLASS_SHADOWED_190x26c
ALERT_CLASS_SHADOWED_200x270
ALERT_CLASS_SHADOWED_210x274
ALERT_CLASS_SHADOWED_220x278
ALERT_CLASS_SHADOWED_230x27c
ALERT_CLASS_SHADOWED_240x280
ALERT_CLASS_SHADOWED_250x284
ALERT_CLASS_SHADOWED_260x288
ALERT_CLASS_SHADOWED_270x28c
ALERT_CLASS_SHADOWED_280x290
ALERT_CLASS_SHADOWED_290x294
ALERT_CLASS_SHADOWED_300x298
ALERT_CLASS_SHADOWED_310x29c
ALERT_CLASS_SHADOWED_320x2a0
ALERT_CLASS_SHADOWED_330x2a4
ALERT_CLASS_SHADOWED_340x2a8
ALERT_CLASS_SHADOWED_350x2ac
ALERT_CLASS_SHADOWED_360x2b0
ALERT_CLASS_SHADOWED_370x2b4
ALERT_CLASS_SHADOWED_380x2b8
ALERT_CLASS_SHADOWED_390x2bc
ALERT_CLASS_SHADOWED_400x2c0
ALERT_CLASS_SHADOWED_410x2c4
ALERT_CLASS_SHADOWED_420x2c8
ALERT_CLASS_SHADOWED_430x2cc
ALERT_CLASS_SHADOWED_440x2d0
ALERT_CLASS_SHADOWED_450x2d4
ALERT_CLASS_SHADOWED_460x2d8
ALERT_CLASS_SHADOWED_470x2dc
ALERT_CLASS_SHADOWED_480x2e0
ALERT_CLASS_SHADOWED_490x2e4
ALERT_CLASS_SHADOWED_500x2e8
ALERT_CLASS_SHADOWED_510x2ec
ALERT_CLASS_SHADOWED_520x2f0
ALERT_CLASS_SHADOWED_530x2f4
ALERT_CLASS_SHADOWED_540x2f8
ALERT_CLASS_SHADOWED_550x2fc
ALERT_CLASS_SHADOWED_560x300
ALERT_CLASS_SHADOWED_570x304
ALERT_CLASS_SHADOWED_580x308
ALERT_CLASS_SHADOWED_590x30c
ALERT_CLASS_SHADOWED_600x310
ALERT_CLASS_SHADOWED_610x314
ALERT_CLASS_SHADOWED_620x318
ALERT_CLASS_SHADOWED_630x31c
ALERT_CLASS_SHADOWED_640x320

Fields

{"reg": [{"name": "CLASS_A", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
BitsTypeResetName
31:2Reserved
1:0rw0x0CLASS_A

ALERT_CLASS_SHADOWED . CLASS_A

Classification

ValueNameDescription
0x0ClassA
0x1ClassB
0x2ClassC
0x3ClassD

ALERT_CAUSE

Alert Cause Register

  • Reset default: 0x0
  • Reset mask: 0x1

Instances

NameOffset
ALERT_CAUSE_00x324
ALERT_CAUSE_10x328
ALERT_CAUSE_20x32c
ALERT_CAUSE_30x330
ALERT_CAUSE_40x334
ALERT_CAUSE_50x338
ALERT_CAUSE_60x33c
ALERT_CAUSE_70x340
ALERT_CAUSE_80x344
ALERT_CAUSE_90x348
ALERT_CAUSE_100x34c
ALERT_CAUSE_110x350
ALERT_CAUSE_120x354
ALERT_CAUSE_130x358
ALERT_CAUSE_140x35c
ALERT_CAUSE_150x360
ALERT_CAUSE_160x364
ALERT_CAUSE_170x368
ALERT_CAUSE_180x36c
ALERT_CAUSE_190x370
ALERT_CAUSE_200x374
ALERT_CAUSE_210x378
ALERT_CAUSE_220x37c
ALERT_CAUSE_230x380
ALERT_CAUSE_240x384
ALERT_CAUSE_250x388
ALERT_CAUSE_260x38c
ALERT_CAUSE_270x390
ALERT_CAUSE_280x394
ALERT_CAUSE_290x398
ALERT_CAUSE_300x39c
ALERT_CAUSE_310x3a0
ALERT_CAUSE_320x3a4
ALERT_CAUSE_330x3a8
ALERT_CAUSE_340x3ac
ALERT_CAUSE_350x3b0
ALERT_CAUSE_360x3b4
ALERT_CAUSE_370x3b8
ALERT_CAUSE_380x3bc
ALERT_CAUSE_390x3c0
ALERT_CAUSE_400x3c4
ALERT_CAUSE_410x3c8
ALERT_CAUSE_420x3cc
ALERT_CAUSE_430x3d0
ALERT_CAUSE_440x3d4
ALERT_CAUSE_450x3d8
ALERT_CAUSE_460x3dc
ALERT_CAUSE_470x3e0
ALERT_CAUSE_480x3e4
ALERT_CAUSE_490x3e8
ALERT_CAUSE_500x3ec
ALERT_CAUSE_510x3f0
ALERT_CAUSE_520x3f4
ALERT_CAUSE_530x3f8
ALERT_CAUSE_540x3fc
ALERT_CAUSE_550x400
ALERT_CAUSE_560x404
ALERT_CAUSE_570x408
ALERT_CAUSE_580x40c
ALERT_CAUSE_590x410
ALERT_CAUSE_600x414
ALERT_CAUSE_610x418
ALERT_CAUSE_620x41c
ALERT_CAUSE_630x420
ALERT_CAUSE_640x424

Fields

{"reg": [{"name": "A", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw1c0x0ACause bit

LOC_ALERT_REGWEN

Register write enable for alert enable bits.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
LOC_ALERT_REGWEN_00x428
LOC_ALERT_REGWEN_10x42c
LOC_ALERT_REGWEN_20x430
LOC_ALERT_REGWEN_30x434
LOC_ALERT_REGWEN_40x438
LOC_ALERT_REGWEN_50x43c
LOC_ALERT_REGWEN_60x440

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:1Reserved
0rw0c0x1EN

LOC_ALERT_REGWEN . EN

Alert configuration write enable bit. If this is cleared to 0, the corresponding LOC_ALERT_EN_SHADOWED and LOC_ALERT_CLASS_SHADOWED bits are not writable anymore.

Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.

LOC_ALERT_EN_SHADOWED

Enable register for the local alerts “alert pingfail” (0), “escalation pingfail” (1), “alert integfail” (2), “escalation integfail” (3), “bus integrity failure” (4), “shadow reg update error” (5) and “shadow reg storage error” (6).

  • Reset default: 0x0
  • Reset mask: 0x1

Instances

NameOffset
LOC_ALERT_EN_SHADOWED_00x444
LOC_ALERT_EN_SHADOWED_10x448
LOC_ALERT_EN_SHADOWED_20x44c
LOC_ALERT_EN_SHADOWED_30x450
LOC_ALERT_EN_SHADOWED_40x454
LOC_ALERT_EN_SHADOWED_50x458
LOC_ALERT_EN_SHADOWED_60x45c

Fields

{"reg": [{"name": "EN_LA", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw0x0EN_LAAlert enable bit. Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.

LOC_ALERT_CLASS_SHADOWED

Class assignment of the local alerts “alert pingfail” (0), “escalation pingfail” (1), “alert integfail” (2), “escalation integfail” (3), “bus integrity failure” (4), “shadow reg update error” (5) and “shadow reg storage error” (6).

  • Reset default: 0x0
  • Reset mask: 0x3

Instances

NameOffset
LOC_ALERT_CLASS_SHADOWED_00x460
LOC_ALERT_CLASS_SHADOWED_10x464
LOC_ALERT_CLASS_SHADOWED_20x468
LOC_ALERT_CLASS_SHADOWED_30x46c
LOC_ALERT_CLASS_SHADOWED_40x470
LOC_ALERT_CLASS_SHADOWED_50x474
LOC_ALERT_CLASS_SHADOWED_60x478

Fields

{"reg": [{"name": "CLASS_LA", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
BitsTypeResetName
31:2Reserved
1:0rw0x0CLASS_LA

LOC_ALERT_CLASS_SHADOWED . CLASS_LA

Classification

ValueNameDescription
0x0ClassA
0x1ClassB
0x2ClassC
0x3ClassD

LOC_ALERT_CAUSE

Alert Cause Register for the local alerts “alert pingfail” (0), “escalation pingfail” (1), “alert integfail” (2), “escalation integfail” (3), “bus integrity failure” (4), “shadow reg update error” (5) and “shadow reg storage error” (6).

  • Reset default: 0x0
  • Reset mask: 0x1

Instances

NameOffset
LOC_ALERT_CAUSE_00x47c
LOC_ALERT_CAUSE_10x480
LOC_ALERT_CAUSE_20x484
LOC_ALERT_CAUSE_30x488
LOC_ALERT_CAUSE_40x48c
LOC_ALERT_CAUSE_50x490
LOC_ALERT_CAUSE_60x494

Fields

{"reg": [{"name": "LA", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw1c0x0LACause bit

CLASSA_REGWEN

Lock bit for Class A configuration.

  • Offset: 0x498
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSA_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1CLASSA_REGWENClass configuration enable bit. If this is cleared to 0, the corresponding class configuration registers cannot be written anymore.

CLASSA_CTRL_SHADOWED

Escalation control register for alert Class A. Can not be modified if CLASSA_REGWEN is false.

  • Offset: 0x49c
  • Reset default: 0x393c
  • Reset mask: 0x3fff
  • Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LOCK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E0", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E1", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E2", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E3", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 18}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:14Reserved
13:12rw0x3MAP_E3Determines in which escalation phase escalation signal 3 shall be asserted.
11:10rw0x2MAP_E2Determines in which escalation phase escalation signal 2 shall be asserted.
9:8rw0x1MAP_E1Determines in which escalation phase escalation signal 1 shall be asserted.
7:6rw0x0MAP_E0Determines in which escalation phase escalation signal 0 shall be asserted.
5rw0x1EN_E3Enable escalation signal 3 for Class A
4rw0x1EN_E2Enable escalation signal 2 for Class A
3rw0x1EN_E1Enable escalation signal 1 for Class A
2rw0x1EN_E0Enable escalation signal 0 for Class A
1rw0x0LOCKEnable automatic locking of escalation counter for class A. If true, there is no way to stop the escalation protocol for class A once it has been triggered.
0rw0x0ENEnable escalation mechanisms (accumulation and interrupt timeout) for Class A. Note that interrupts can fire regardless of whether the escalation mechanisms are enabled for this class or not.

CLASSA_CLR_REGWEN

Clear enable for escalation protocol of Class A alerts.

  • Offset: 0x4a0
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSA_CLR_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1CLASSA_CLR_REGWENRegister defaults to true, can only be cleared. This register is set to false by the hardware if the escalation protocol has been triggered and the bit CLASSA_CTRL_SHADOWED.LOCK is true.

CLASSA_CLR_SHADOWED

Clear for escalation protocol of Class A.

  • Offset: 0x4a4
  • Reset default: 0x0
  • Reset mask: 0x1
  • Register enable: CLASSA_CLR_REGWEN

Fields

{"reg": [{"name": "CLASSA_CLR_SHADOWED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
BitsTypeResetNameDescription
31:1Reserved
0rw0x0CLASSA_CLR_SHADOWEDWriting 1 to this register clears the accumulator and aborts escalation (if it has been triggered). This clear is disabled if CLASSA_CLR_REGWEN is false.

CLASSA_ACCUM_CNT

Current accumulation value for alert Class A. Software can clear this register with a write to CLASSA_CLR_SHADOWED register unless CLASSA_CLR_REGWEN is false.

  • Offset: 0x4a8
  • Reset default: 0x0
  • Reset mask: 0xffff

Fields

{"reg": [{"name": "CLASSA_ACCUM_CNT", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16Reserved
15:0roxCLASSA_ACCUM_CNT

CLASSA_ACCUM_THRESH_SHADOWED

Accumulation threshold value for alert Class A.

  • Offset: 0x4ac
  • Reset default: 0x0
  • Reset mask: 0xffff
  • Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "CLASSA_ACCUM_THRESH_SHADOWED", "bits": 16, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16Reserved
15:0rw0x0CLASSA_ACCUM_THRESH_SHADOWEDOnce the accumulation value register is equal to the threshold escalation will be triggered on the next alert occurrence within this class A begins. Note that this register can not be modified if CLASSA_REGWEN is false.

CLASSA_TIMEOUT_CYC_SHADOWED

Interrupt timeout in cycles.

  • Offset: 0x4b0
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "CLASSA_TIMEOUT_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:0rw0x0CLASSA_TIMEOUT_CYC_SHADOWED

CLASSA_TIMEOUT_CYC_SHADOWED . CLASSA_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class A. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSA_REGWEN is false.

CLASSA_CRASHDUMP_TRIGGER_SHADOWED

Crashdump trigger configuration for Class A.

  • Offset: 0x4b4
  • Reset default: 0x0
  • Reset mask: 0x3
  • Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "CLASSA_CRASHDUMP_TRIGGER_SHADOWED", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 350}}
BitsTypeResetName
31:2Reserved
1:0rw0x0CLASSA_CRASHDUMP_TRIGGER_SHADOWED

CLASSA_CRASHDUMP_TRIGGER_SHADOWED . CLASSA_CRASHDUMP_TRIGGER_SHADOWED

Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation timer states. It is recommended to capture the crashdump upon entering the first escalation phase that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order to prevent spurious alert events from masking the original alert causes. Note that this register can not be modified if CLASSA_REGWEN is false.

CLASSA_PHASE0_CYC_SHADOWED

Duration of escalation phase 0 for Class A.

  • Offset: 0x4b8
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "CLASSA_PHASE0_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSA_PHASE0_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSA_REGWEN is false.

CLASSA_PHASE1_CYC_SHADOWED

Duration of escalation phase 1 for Class A.

  • Offset: 0x4bc
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "CLASSA_PHASE1_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSA_PHASE1_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSA_REGWEN is false.

CLASSA_PHASE2_CYC_SHADOWED

Duration of escalation phase 2 for Class A.

  • Offset: 0x4c0
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "CLASSA_PHASE2_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSA_PHASE2_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSA_REGWEN is false.

CLASSA_PHASE3_CYC_SHADOWED

Duration of escalation phase 3 for Class A.

  • Offset: 0x4c4
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSA_REGWEN

Fields

{"reg": [{"name": "CLASSA_PHASE3_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSA_PHASE3_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSA_REGWEN is false.

CLASSA_ESC_CNT

Escalation counter in cycles for Class A.

  • Offset: 0x4c8
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "CLASSA_ESC_CNT", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:0roxCLASSA_ESC_CNT

CLASSA_ESC_CNT . CLASSA_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSA_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSA_CLR_SHADOWED. Note however that has no effect if CLASSA_REGWEN is set to false (either by SW or by HW via the CLASSA_CTRL_SHADOWED.LOCK feature).

CLASSA_STATE

Current escalation state of Class A. See also CLASSA_ESC_CNT.

  • Offset: 0x4cc
  • Reset default: 0x0
  • Reset mask: 0x7

Fields

{"reg": [{"name": "CLASSA_STATE", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}}
BitsTypeResetName
31:3Reserved
2:0roxCLASSA_STATE

CLASSA_STATE . CLASSA_STATE

ValueNameDescription
0x0IdleNo timeout or escalation triggered.
0x1TimeoutIRQ timeout counter is active.
0x2FsmErrorTerminal error state if FSM has been glitched.
0x3TerminalTerminal state after escalation protocol.
0x4Phase0Escalation Phase0 is active.
0x5Phase1Escalation Phase1 is active.
0x6Phase2Escalation Phase2 is active.
0x7Phase3Escalation Phase3 is active.

CLASSB_REGWEN

Lock bit for Class B configuration.

  • Offset: 0x4d0
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSB_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1CLASSB_REGWENClass configuration enable bit. If this is cleared to 0, the corresponding class configuration registers cannot be written anymore.

CLASSB_CTRL_SHADOWED

Escalation control register for alert Class B. Can not be modified if CLASSB_REGWEN is false.

  • Offset: 0x4d4
  • Reset default: 0x393c
  • Reset mask: 0x3fff
  • Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LOCK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E0", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E1", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E2", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E3", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 18}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:14Reserved
13:12rw0x3MAP_E3Determines in which escalation phase escalation signal 3 shall be asserted.
11:10rw0x2MAP_E2Determines in which escalation phase escalation signal 2 shall be asserted.
9:8rw0x1MAP_E1Determines in which escalation phase escalation signal 1 shall be asserted.
7:6rw0x0MAP_E0Determines in which escalation phase escalation signal 0 shall be asserted.
5rw0x1EN_E3Enable escalation signal 3 for Class B
4rw0x1EN_E2Enable escalation signal 2 for Class B
3rw0x1EN_E1Enable escalation signal 1 for Class B
2rw0x1EN_E0Enable escalation signal 0 for Class B
1rw0x0LOCKEnable automatic locking of escalation counter for class B. If true, there is no way to stop the escalation protocol for class B once it has been triggered.
0rw0x0ENEnable escalation mechanisms (accumulation and interrupt timeout) for Class B. Note that interrupts can fire regardless of whether the escalation mechanisms are enabled for this class or not.

CLASSB_CLR_REGWEN

Clear enable for escalation protocol of Class B alerts.

  • Offset: 0x4d8
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSB_CLR_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1CLASSB_CLR_REGWENRegister defaults to true, can only be cleared. This register is set to false by the hardware if the escalation protocol has been triggered and the bit CLASSB_CTRL_SHADOWED.LOCK is true.

CLASSB_CLR_SHADOWED

Clear for escalation protocol of Class B.

  • Offset: 0x4dc
  • Reset default: 0x0
  • Reset mask: 0x1
  • Register enable: CLASSB_CLR_REGWEN

Fields

{"reg": [{"name": "CLASSB_CLR_SHADOWED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
BitsTypeResetNameDescription
31:1Reserved
0rw0x0CLASSB_CLR_SHADOWEDWriting 1 to this register clears the accumulator and aborts escalation (if it has been triggered). This clear is disabled if CLASSB_CLR_REGWEN is false.

CLASSB_ACCUM_CNT

Current accumulation value for alert Class B. Software can clear this register with a write to CLASSB_CLR_SHADOWED register unless CLASSB_CLR_REGWEN is false.

  • Offset: 0x4e0
  • Reset default: 0x0
  • Reset mask: 0xffff

Fields

{"reg": [{"name": "CLASSB_ACCUM_CNT", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16Reserved
15:0roxCLASSB_ACCUM_CNT

CLASSB_ACCUM_THRESH_SHADOWED

Accumulation threshold value for alert Class B.

  • Offset: 0x4e4
  • Reset default: 0x0
  • Reset mask: 0xffff
  • Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "CLASSB_ACCUM_THRESH_SHADOWED", "bits": 16, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16Reserved
15:0rw0x0CLASSB_ACCUM_THRESH_SHADOWEDOnce the accumulation value register is equal to the threshold escalation will be triggered on the next alert occurrence within this class B begins. Note that this register can not be modified if CLASSB_REGWEN is false.

CLASSB_TIMEOUT_CYC_SHADOWED

Interrupt timeout in cycles.

  • Offset: 0x4e8
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "CLASSB_TIMEOUT_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:0rw0x0CLASSB_TIMEOUT_CYC_SHADOWED

CLASSB_TIMEOUT_CYC_SHADOWED . CLASSB_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class B. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSB_REGWEN is false.

CLASSB_CRASHDUMP_TRIGGER_SHADOWED

Crashdump trigger configuration for Class B.

  • Offset: 0x4ec
  • Reset default: 0x0
  • Reset mask: 0x3
  • Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "CLASSB_CRASHDUMP_TRIGGER_SHADOWED", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 350}}
BitsTypeResetName
31:2Reserved
1:0rw0x0CLASSB_CRASHDUMP_TRIGGER_SHADOWED

CLASSB_CRASHDUMP_TRIGGER_SHADOWED . CLASSB_CRASHDUMP_TRIGGER_SHADOWED

Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation timer states. It is recommended to capture the crashdump upon entering the first escalation phase that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order to prevent spurious alert events from masking the original alert causes. Note that this register can not be modified if CLASSB_REGWEN is false.

CLASSB_PHASE0_CYC_SHADOWED

Duration of escalation phase 0 for Class B.

  • Offset: 0x4f0
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "CLASSB_PHASE0_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSB_PHASE0_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSB_REGWEN is false.

CLASSB_PHASE1_CYC_SHADOWED

Duration of escalation phase 1 for Class B.

  • Offset: 0x4f4
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "CLASSB_PHASE1_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSB_PHASE1_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSB_REGWEN is false.

CLASSB_PHASE2_CYC_SHADOWED

Duration of escalation phase 2 for Class B.

  • Offset: 0x4f8
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "CLASSB_PHASE2_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSB_PHASE2_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSB_REGWEN is false.

CLASSB_PHASE3_CYC_SHADOWED

Duration of escalation phase 3 for Class B.

  • Offset: 0x4fc
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSB_REGWEN

Fields

{"reg": [{"name": "CLASSB_PHASE3_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSB_PHASE3_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSB_REGWEN is false.

CLASSB_ESC_CNT

Escalation counter in cycles for Class B.

  • Offset: 0x500
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "CLASSB_ESC_CNT", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:0roxCLASSB_ESC_CNT

CLASSB_ESC_CNT . CLASSB_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSB_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSB_CLR_SHADOWED. Note however that has no effect if CLASSB_REGWEN is set to false (either by SW or by HW via the CLASSB_CTRL_SHADOWED.LOCK feature).

CLASSB_STATE

Current escalation state of Class B. See also CLASSB_ESC_CNT.

  • Offset: 0x504
  • Reset default: 0x0
  • Reset mask: 0x7

Fields

{"reg": [{"name": "CLASSB_STATE", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}}
BitsTypeResetName
31:3Reserved
2:0roxCLASSB_STATE

CLASSB_STATE . CLASSB_STATE

ValueNameDescription
0x0IdleNo timeout or escalation triggered.
0x1TimeoutIRQ timeout counter is active.
0x2FsmErrorTerminal error state if FSM has been glitched.
0x3TerminalTerminal state after escalation protocol.
0x4Phase0Escalation Phase0 is active.
0x5Phase1Escalation Phase1 is active.
0x6Phase2Escalation Phase2 is active.
0x7Phase3Escalation Phase3 is active.

CLASSC_REGWEN

Lock bit for Class C configuration.

  • Offset: 0x508
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSC_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1CLASSC_REGWENClass configuration enable bit. If this is cleared to 0, the corresponding class configuration registers cannot be written anymore.

CLASSC_CTRL_SHADOWED

Escalation control register for alert Class C. Can not be modified if CLASSC_REGWEN is false.

  • Offset: 0x50c
  • Reset default: 0x393c
  • Reset mask: 0x3fff
  • Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LOCK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E0", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E1", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E2", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E3", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 18}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:14Reserved
13:12rw0x3MAP_E3Determines in which escalation phase escalation signal 3 shall be asserted.
11:10rw0x2MAP_E2Determines in which escalation phase escalation signal 2 shall be asserted.
9:8rw0x1MAP_E1Determines in which escalation phase escalation signal 1 shall be asserted.
7:6rw0x0MAP_E0Determines in which escalation phase escalation signal 0 shall be asserted.
5rw0x1EN_E3Enable escalation signal 3 for Class C
4rw0x1EN_E2Enable escalation signal 2 for Class C
3rw0x1EN_E1Enable escalation signal 1 for Class C
2rw0x1EN_E0Enable escalation signal 0 for Class C
1rw0x0LOCKEnable automatic locking of escalation counter for class C. If true, there is no way to stop the escalation protocol for class C once it has been triggered.
0rw0x0ENEnable escalation mechanisms (accumulation and interrupt timeout) for Class C. Note that interrupts can fire regardless of whether the escalation mechanisms are enabled for this class or not.

CLASSC_CLR_REGWEN

Clear enable for escalation protocol of Class C alerts.

  • Offset: 0x510
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSC_CLR_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1CLASSC_CLR_REGWENRegister defaults to true, can only be cleared. This register is set to false by the hardware if the escalation protocol has been triggered and the bit CLASSC_CTRL_SHADOWED.LOCK is true.

CLASSC_CLR_SHADOWED

Clear for escalation protocol of Class C.

  • Offset: 0x514
  • Reset default: 0x0
  • Reset mask: 0x1
  • Register enable: CLASSC_CLR_REGWEN

Fields

{"reg": [{"name": "CLASSC_CLR_SHADOWED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
BitsTypeResetNameDescription
31:1Reserved
0rw0x0CLASSC_CLR_SHADOWEDWriting 1 to this register clears the accumulator and aborts escalation (if it has been triggered). This clear is disabled if CLASSC_CLR_REGWEN is false.

CLASSC_ACCUM_CNT

Current accumulation value for alert Class C. Software can clear this register with a write to CLASSC_CLR_SHADOWED register unless CLASSC_CLR_REGWEN is false.

  • Offset: 0x518
  • Reset default: 0x0
  • Reset mask: 0xffff

Fields

{"reg": [{"name": "CLASSC_ACCUM_CNT", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16Reserved
15:0roxCLASSC_ACCUM_CNT

CLASSC_ACCUM_THRESH_SHADOWED

Accumulation threshold value for alert Class C.

  • Offset: 0x51c
  • Reset default: 0x0
  • Reset mask: 0xffff
  • Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "CLASSC_ACCUM_THRESH_SHADOWED", "bits": 16, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16Reserved
15:0rw0x0CLASSC_ACCUM_THRESH_SHADOWEDOnce the accumulation value register is equal to the threshold escalation will be triggered on the next alert occurrence within this class C begins. Note that this register can not be modified if CLASSC_REGWEN is false.

CLASSC_TIMEOUT_CYC_SHADOWED

Interrupt timeout in cycles.

  • Offset: 0x520
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "CLASSC_TIMEOUT_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:0rw0x0CLASSC_TIMEOUT_CYC_SHADOWED

CLASSC_TIMEOUT_CYC_SHADOWED . CLASSC_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class C. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSC_REGWEN is false.

CLASSC_CRASHDUMP_TRIGGER_SHADOWED

Crashdump trigger configuration for Class C.

  • Offset: 0x524
  • Reset default: 0x0
  • Reset mask: 0x3
  • Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "CLASSC_CRASHDUMP_TRIGGER_SHADOWED", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 350}}
BitsTypeResetName
31:2Reserved
1:0rw0x0CLASSC_CRASHDUMP_TRIGGER_SHADOWED

CLASSC_CRASHDUMP_TRIGGER_SHADOWED . CLASSC_CRASHDUMP_TRIGGER_SHADOWED

Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation timer states. It is recommended to capture the crashdump upon entering the first escalation phase that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order to prevent spurious alert events from masking the original alert causes. Note that this register can not be modified if CLASSC_REGWEN is false.

CLASSC_PHASE0_CYC_SHADOWED

Duration of escalation phase 0 for Class C.

  • Offset: 0x528
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "CLASSC_PHASE0_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSC_PHASE0_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSC_REGWEN is false.

CLASSC_PHASE1_CYC_SHADOWED

Duration of escalation phase 1 for Class C.

  • Offset: 0x52c
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "CLASSC_PHASE1_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSC_PHASE1_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSC_REGWEN is false.

CLASSC_PHASE2_CYC_SHADOWED

Duration of escalation phase 2 for Class C.

  • Offset: 0x530
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "CLASSC_PHASE2_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSC_PHASE2_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSC_REGWEN is false.

CLASSC_PHASE3_CYC_SHADOWED

Duration of escalation phase 3 for Class C.

  • Offset: 0x534
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSC_REGWEN

Fields

{"reg": [{"name": "CLASSC_PHASE3_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSC_PHASE3_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSC_REGWEN is false.

CLASSC_ESC_CNT

Escalation counter in cycles for Class C.

  • Offset: 0x538
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "CLASSC_ESC_CNT", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:0roxCLASSC_ESC_CNT

CLASSC_ESC_CNT . CLASSC_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSC_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSC_CLR_SHADOWED. Note however that has no effect if CLASSC_REGWEN is set to false (either by SW or by HW via the CLASSC_CTRL_SHADOWED.LOCK feature).

CLASSC_STATE

Current escalation state of Class C. See also CLASSC_ESC_CNT.

  • Offset: 0x53c
  • Reset default: 0x0
  • Reset mask: 0x7

Fields

{"reg": [{"name": "CLASSC_STATE", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}}
BitsTypeResetName
31:3Reserved
2:0roxCLASSC_STATE

CLASSC_STATE . CLASSC_STATE

ValueNameDescription
0x0IdleNo timeout or escalation triggered.
0x1TimeoutIRQ timeout counter is active.
0x2FsmErrorTerminal error state if FSM has been glitched.
0x3TerminalTerminal state after escalation protocol.
0x4Phase0Escalation Phase0 is active.
0x5Phase1Escalation Phase1 is active.
0x6Phase2Escalation Phase2 is active.
0x7Phase3Escalation Phase3 is active.

CLASSD_REGWEN

Lock bit for Class D configuration.

  • Offset: 0x540
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSD_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1CLASSD_REGWENClass configuration enable bit. If this is cleared to 0, the corresponding class configuration registers cannot be written anymore.

CLASSD_CTRL_SHADOWED

Escalation control register for alert Class D. Can not be modified if CLASSD_REGWEN is false.

  • Offset: 0x544
  • Reset default: 0x393c
  • Reset mask: 0x3fff
  • Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LOCK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_E3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E0", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E1", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E2", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "MAP_E3", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 18}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:14Reserved
13:12rw0x3MAP_E3Determines in which escalation phase escalation signal 3 shall be asserted.
11:10rw0x2MAP_E2Determines in which escalation phase escalation signal 2 shall be asserted.
9:8rw0x1MAP_E1Determines in which escalation phase escalation signal 1 shall be asserted.
7:6rw0x0MAP_E0Determines in which escalation phase escalation signal 0 shall be asserted.
5rw0x1EN_E3Enable escalation signal 3 for Class D
4rw0x1EN_E2Enable escalation signal 2 for Class D
3rw0x1EN_E1Enable escalation signal 1 for Class D
2rw0x1EN_E0Enable escalation signal 0 for Class D
1rw0x0LOCKEnable automatic locking of escalation counter for class D. If true, there is no way to stop the escalation protocol for class D once it has been triggered.
0rw0x0ENEnable escalation mechanisms (accumulation and interrupt timeout) for Class D. Note that interrupts can fire regardless of whether the escalation mechanisms are enabled for this class or not.

CLASSD_CLR_REGWEN

Clear enable for escalation protocol of Class D alerts.

  • Offset: 0x548
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

{"reg": [{"name": "CLASSD_CLR_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1CLASSD_CLR_REGWENRegister defaults to true, can only be cleared. This register is set to false by the hardware if the escalation protocol has been triggered and the bit CLASSD_CTRL_SHADOWED.LOCK is true.

CLASSD_CLR_SHADOWED

Clear for escalation protocol of Class D.

  • Offset: 0x54c
  • Reset default: 0x0
  • Reset mask: 0x1
  • Register enable: CLASSD_CLR_REGWEN

Fields

{"reg": [{"name": "CLASSD_CLR_SHADOWED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
BitsTypeResetNameDescription
31:1Reserved
0rw0x0CLASSD_CLR_SHADOWEDWriting 1 to this register clears the accumulator and aborts escalation (if it has been triggered). This clear is disabled if CLASSD_CLR_REGWEN is false.

CLASSD_ACCUM_CNT

Current accumulation value for alert Class D. Software can clear this register with a write to CLASSD_CLR_SHADOWED register unless CLASSD_CLR_REGWEN is false.

  • Offset: 0x550
  • Reset default: 0x0
  • Reset mask: 0xffff

Fields

{"reg": [{"name": "CLASSD_ACCUM_CNT", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16Reserved
15:0roxCLASSD_ACCUM_CNT

CLASSD_ACCUM_THRESH_SHADOWED

Accumulation threshold value for alert Class D.

  • Offset: 0x554
  • Reset default: 0x0
  • Reset mask: 0xffff
  • Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "CLASSD_ACCUM_THRESH_SHADOWED", "bits": 16, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16Reserved
15:0rw0x0CLASSD_ACCUM_THRESH_SHADOWEDOnce the accumulation value register is equal to the threshold escalation will be triggered on the next alert occurrence within this class D begins. Note that this register can not be modified if CLASSD_REGWEN is false.

CLASSD_TIMEOUT_CYC_SHADOWED

Interrupt timeout in cycles.

  • Offset: 0x558
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "CLASSD_TIMEOUT_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:0rw0x0CLASSD_TIMEOUT_CYC_SHADOWED

CLASSD_TIMEOUT_CYC_SHADOWED . CLASSD_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class D. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSD_REGWEN is false.

CLASSD_CRASHDUMP_TRIGGER_SHADOWED

Crashdump trigger configuration for Class D.

  • Offset: 0x55c
  • Reset default: 0x0
  • Reset mask: 0x3
  • Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "CLASSD_CRASHDUMP_TRIGGER_SHADOWED", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 350}}
BitsTypeResetName
31:2Reserved
1:0rw0x0CLASSD_CRASHDUMP_TRIGGER_SHADOWED

CLASSD_CRASHDUMP_TRIGGER_SHADOWED . CLASSD_CRASHDUMP_TRIGGER_SHADOWED

Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation timer states. It is recommended to capture the crashdump upon entering the first escalation phase that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order to prevent spurious alert events from masking the original alert causes. Note that this register can not be modified if CLASSD_REGWEN is false.

CLASSD_PHASE0_CYC_SHADOWED

Duration of escalation phase 0 for Class D.

  • Offset: 0x560
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "CLASSD_PHASE0_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSD_PHASE0_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSD_REGWEN is false.

CLASSD_PHASE1_CYC_SHADOWED

Duration of escalation phase 1 for Class D.

  • Offset: 0x564
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "CLASSD_PHASE1_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSD_PHASE1_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSD_REGWEN is false.

CLASSD_PHASE2_CYC_SHADOWED

Duration of escalation phase 2 for Class D.

  • Offset: 0x568
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "CLASSD_PHASE2_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSD_PHASE2_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSD_REGWEN is false.

CLASSD_PHASE3_CYC_SHADOWED

Duration of escalation phase 3 for Class D.

  • Offset: 0x56c
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CLASSD_REGWEN

Fields

{"reg": [{"name": "CLASSD_PHASE3_CYC_SHADOWED", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:0rw0x0CLASSD_PHASE3_CYC_SHADOWEDEscalation phase duration in cycles. Note that this register can not be modified if CLASSD_REGWEN is false.

CLASSD_ESC_CNT

Escalation counter in cycles for Class D.

  • Offset: 0x570
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "CLASSD_ESC_CNT", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:0roxCLASSD_ESC_CNT

CLASSD_ESC_CNT . CLASSD_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSD_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSD_CLR_SHADOWED. Note however that has no effect if CLASSD_REGWEN is set to false (either by SW or by HW via the CLASSD_CTRL_SHADOWED.LOCK feature).

CLASSD_STATE

Current escalation state of Class D. See also CLASSD_ESC_CNT.

  • Offset: 0x574
  • Reset default: 0x0
  • Reset mask: 0x7

Fields

{"reg": [{"name": "CLASSD_STATE", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}}
BitsTypeResetName
31:3Reserved
2:0roxCLASSD_STATE

CLASSD_STATE . CLASSD_STATE

ValueNameDescription
0x0IdleNo timeout or escalation triggered.
0x1TimeoutIRQ timeout counter is active.
0x2FsmErrorTerminal error state if FSM has been glitched.
0x3TerminalTerminal state after escalation protocol.
0x4Phase0Escalation Phase0 is active.
0x5Phase1Escalation Phase1 is active.
0x6Phase2Escalation Phase2 is active.
0x7Phase3Escalation Phase3 is active.