Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module alert_handler has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_edn_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Inter-Module Signals: Reference

Inter-Module Signals
Port Name	Package::Struct	Type	Act	Width
crashdump	alert_pkg::alert_crashdump	uni	req	1
edn	edn_pkg::edn	req_rsp	req	1
esc_rx	prim_esc_pkg::esc_rx	uni	rcv	4
esc_tx	prim_esc_pkg::esc_tx	uni	req	4
tl	tlul_pkg::tl	req_rsp	rsp	1

Interrupts:

Interrupt Name	Type	Description
classa	Event	Interrupt state bit of Class A. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
classb	Event	Interrupt state bit of Class B. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
classc	Event	Interrupt state bit of Class C. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
classd	Event	Interrupt state bit of Class D. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.

Security Alerts: none

Security Countermeasures:

Countermeasure ID	Description
ALERT_HANDLER.BUS.INTEGRITY	End-to-end bus integrity scheme.
ALERT_HANDLER.CONFIG.SHADOW	Important CSRs are shadowed.
ALERT_HANDLER.PING_TIMER.CONFIG.REGWEN	The ping timer configuration registers are REGWEN protected.
ALERT_HANDLER.ALERT.CONFIG.REGWEN	The individual alert enables are REGWEN protected.
ALERT_HANDLER.ALERT_LOC.CONFIG.REGWEN	The individual local alert enables are REGWEN protected.
ALERT_HANDLER.CLASS.CONFIG.REGWEN	The class configuration registers are REGWEN protected.
ALERT_HANDLER.ALERT.INTERSIG.DIFF	Differentially encoded alert channels.
ALERT_HANDLER.LPG.INTERSIG.MUBI	LPG signals are encoded with MUBI types.
ALERT_HANDLER.ESC.INTERSIG.DIFF	Differentially encoded escalation channels.
ALERT_HANDLER.ALERT_RX.INTERSIG.BKGN_CHK	Periodic background checks on alert channels (ping mechanism).
ALERT_HANDLER.ESC_TX.INTERSIG.BKGN_CHK	Periodic background checks on escalation channels (ping mechanism).
ALERT_HANDLER.ESC_RX.INTERSIG.BKGN_CHK	Escalation receivers can detect absence of periodic ping requests.
ALERT_HANDLER.ESC_TIMER.FSM.SPARSE	Escalation timer FSMs are sparsely encoded.
ALERT_HANDLER.PING_TIMER.FSM.SPARSE	Ping timer FSM is sparsely encoded.
ALERT_HANDLER.ESC_TIMER.FSM.LOCAL_ESC	Escalation timer FSMs move into an invalid state upon local escalation.
ALERT_HANDLER.PING_TIMER.FSM.LOCAL_ESC	Ping timer FSM moves into an invalid state upon local escalation.
ALERT_HANDLER.ESC_TIMER.FSM.GLOBAL_ESC	The escalation timer FSMs are the root of global escalation, hence if any of them moves into an invalid state by virtue of ESC_TIMER.FSM.LOCAL_ESC, this will trigger all escalation actions and thereby global escalation as well.
ALERT_HANDLER.ACCU.CTR.REDUN	Accumulator counters employ a cross-counter implementation.
ALERT_HANDLER.ESC_TIMER.CTR.REDUN	Escalation timer counters employ a duplicated counter implementation.
ALERT_HANDLER.PING_TIMER.CTR.REDUN	Ping timer counters employ a duplicated counter implementation.
ALERT_HANDLER.PING_TIMER.LFSR.REDUN	Ping timer LFSR is redundant.

Registers

Summary
Name	Offset	Length	Description
alert_handler.INTR_STATE	0x0	4	Interrupt State Register
alert_handler.INTR_ENABLE	0x4	4	Interrupt Enable Register
alert_handler.INTR_TEST	0x8	4	Interrupt Test Register
alert_handler.PING_TIMER_REGWEN	0xc	4	Register write enable for `PING_TIMEOUT_CYC_SHADOWED` and `PING_TIMER_EN_SHADOWED`.
alert_handler.PING_TIMEOUT_CYC_SHADOWED	0x10	4	Ping timeout cycle count.
alert_handler.PING_TIMER_EN_SHADOWED	0x14	4	Ping timer enable.
alert_handler.ALERT_REGWEN_0	0x18	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_1	0x1c	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_2	0x20	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_3	0x24	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_4	0x28	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_5	0x2c	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_6	0x30	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_7	0x34	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_8	0x38	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_9	0x3c	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_10	0x40	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_11	0x44	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_12	0x48	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_13	0x4c	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_14	0x50	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_15	0x54	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_16	0x58	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_17	0x5c	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_18	0x60	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_19	0x64	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_20	0x68	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_21	0x6c	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_22	0x70	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_23	0x74	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_24	0x78	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_25	0x7c	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_26	0x80	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_27	0x84	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_28	0x88	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_29	0x8c	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_30	0x90	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_31	0x94	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_32	0x98	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_33	0x9c	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_34	0xa0	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_35	0xa4	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_36	0xa8	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_37	0xac	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_38	0xb0	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_39	0xb4	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_40	0xb8	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_41	0xbc	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_42	0xc0	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_43	0xc4	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_44	0xc8	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_45	0xcc	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_46	0xd0	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_47	0xd4	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_48	0xd8	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_49	0xdc	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_50	0xe0	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_51	0xe4	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_52	0xe8	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_53	0xec	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_54	0xf0	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_55	0xf4	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_56	0xf8	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_57	0xfc	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_58	0x100	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_59	0x104	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_60	0x108	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_61	0x10c	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_62	0x110	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_63	0x114	4	Register write enable for alert enable bits.
alert_handler.ALERT_REGWEN_64	0x118	4	Register write enable for alert enable bits.
alert_handler.ALERT_EN_SHADOWED_0	0x11c	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_1	0x120	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_2	0x124	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_3	0x128	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_4	0x12c	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_5	0x130	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_6	0x134	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_7	0x138	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_8	0x13c	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_9	0x140	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_10	0x144	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_11	0x148	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_12	0x14c	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_13	0x150	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_14	0x154	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_15	0x158	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_16	0x15c	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_17	0x160	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_18	0x164	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_19	0x168	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_20	0x16c	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_21	0x170	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_22	0x174	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_23	0x178	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_24	0x17c	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_25	0x180	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_26	0x184	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_27	0x188	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_28	0x18c	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_29	0x190	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_30	0x194	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_31	0x198	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_32	0x19c	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_33	0x1a0	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_34	0x1a4	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_35	0x1a8	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_36	0x1ac	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_37	0x1b0	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_38	0x1b4	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_39	0x1b8	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_40	0x1bc	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_41	0x1c0	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_42	0x1c4	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_43	0x1c8	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_44	0x1cc	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_45	0x1d0	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_46	0x1d4	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_47	0x1d8	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_48	0x1dc	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_49	0x1e0	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_50	0x1e4	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_51	0x1e8	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_52	0x1ec	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_53	0x1f0	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_54	0x1f4	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_55	0x1f8	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_56	0x1fc	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_57	0x200	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_58	0x204	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_59	0x208	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_60	0x20c	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_61	0x210	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_62	0x214	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_63	0x218	4	Enable register for alerts.
alert_handler.ALERT_EN_SHADOWED_64	0x21c	4	Enable register for alerts.
alert_handler.ALERT_CLASS_SHADOWED_0	0x220	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_1	0x224	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_2	0x228	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_3	0x22c	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_4	0x230	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_5	0x234	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_6	0x238	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_7	0x23c	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_8	0x240	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_9	0x244	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_10	0x248	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_11	0x24c	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_12	0x250	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_13	0x254	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_14	0x258	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_15	0x25c	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_16	0x260	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_17	0x264	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_18	0x268	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_19	0x26c	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_20	0x270	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_21	0x274	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_22	0x278	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_23	0x27c	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_24	0x280	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_25	0x284	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_26	0x288	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_27	0x28c	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_28	0x290	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_29	0x294	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_30	0x298	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_31	0x29c	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_32	0x2a0	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_33	0x2a4	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_34	0x2a8	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_35	0x2ac	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_36	0x2b0	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_37	0x2b4	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_38	0x2b8	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_39	0x2bc	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_40	0x2c0	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_41	0x2c4	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_42	0x2c8	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_43	0x2cc	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_44	0x2d0	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_45	0x2d4	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_46	0x2d8	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_47	0x2dc	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_48	0x2e0	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_49	0x2e4	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_50	0x2e8	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_51	0x2ec	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_52	0x2f0	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_53	0x2f4	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_54	0x2f8	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_55	0x2fc	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_56	0x300	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_57	0x304	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_58	0x308	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_59	0x30c	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_60	0x310	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_61	0x314	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_62	0x318	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_63	0x31c	4	Class assignment of alerts.
alert_handler.ALERT_CLASS_SHADOWED_64	0x320	4	Class assignment of alerts.
alert_handler.ALERT_CAUSE_0	0x324	4	Alert Cause Register
alert_handler.ALERT_CAUSE_1	0x328	4	Alert Cause Register
alert_handler.ALERT_CAUSE_2	0x32c	4	Alert Cause Register
alert_handler.ALERT_CAUSE_3	0x330	4	Alert Cause Register
alert_handler.ALERT_CAUSE_4	0x334	4	Alert Cause Register
alert_handler.ALERT_CAUSE_5	0x338	4	Alert Cause Register
alert_handler.ALERT_CAUSE_6	0x33c	4	Alert Cause Register
alert_handler.ALERT_CAUSE_7	0x340	4	Alert Cause Register
alert_handler.ALERT_CAUSE_8	0x344	4	Alert Cause Register
alert_handler.ALERT_CAUSE_9	0x348	4	Alert Cause Register
alert_handler.ALERT_CAUSE_10	0x34c	4	Alert Cause Register
alert_handler.ALERT_CAUSE_11	0x350	4	Alert Cause Register
alert_handler.ALERT_CAUSE_12	0x354	4	Alert Cause Register
alert_handler.ALERT_CAUSE_13	0x358	4	Alert Cause Register
alert_handler.ALERT_CAUSE_14	0x35c	4	Alert Cause Register
alert_handler.ALERT_CAUSE_15	0x360	4	Alert Cause Register
alert_handler.ALERT_CAUSE_16	0x364	4	Alert Cause Register
alert_handler.ALERT_CAUSE_17	0x368	4	Alert Cause Register
alert_handler.ALERT_CAUSE_18	0x36c	4	Alert Cause Register
alert_handler.ALERT_CAUSE_19	0x370	4	Alert Cause Register
alert_handler.ALERT_CAUSE_20	0x374	4	Alert Cause Register
alert_handler.ALERT_CAUSE_21	0x378	4	Alert Cause Register
alert_handler.ALERT_CAUSE_22	0x37c	4	Alert Cause Register
alert_handler.ALERT_CAUSE_23	0x380	4	Alert Cause Register
alert_handler.ALERT_CAUSE_24	0x384	4	Alert Cause Register
alert_handler.ALERT_CAUSE_25	0x388	4	Alert Cause Register
alert_handler.ALERT_CAUSE_26	0x38c	4	Alert Cause Register
alert_handler.ALERT_CAUSE_27	0x390	4	Alert Cause Register
alert_handler.ALERT_CAUSE_28	0x394	4	Alert Cause Register
alert_handler.ALERT_CAUSE_29	0x398	4	Alert Cause Register
alert_handler.ALERT_CAUSE_30	0x39c	4	Alert Cause Register
alert_handler.ALERT_CAUSE_31	0x3a0	4	Alert Cause Register
alert_handler.ALERT_CAUSE_32	0x3a4	4	Alert Cause Register
alert_handler.ALERT_CAUSE_33	0x3a8	4	Alert Cause Register
alert_handler.ALERT_CAUSE_34	0x3ac	4	Alert Cause Register
alert_handler.ALERT_CAUSE_35	0x3b0	4	Alert Cause Register
alert_handler.ALERT_CAUSE_36	0x3b4	4	Alert Cause Register
alert_handler.ALERT_CAUSE_37	0x3b8	4	Alert Cause Register
alert_handler.ALERT_CAUSE_38	0x3bc	4	Alert Cause Register
alert_handler.ALERT_CAUSE_39	0x3c0	4	Alert Cause Register
alert_handler.ALERT_CAUSE_40	0x3c4	4	Alert Cause Register
alert_handler.ALERT_CAUSE_41	0x3c8	4	Alert Cause Register
alert_handler.ALERT_CAUSE_42	0x3cc	4	Alert Cause Register
alert_handler.ALERT_CAUSE_43	0x3d0	4	Alert Cause Register
alert_handler.ALERT_CAUSE_44	0x3d4	4	Alert Cause Register
alert_handler.ALERT_CAUSE_45	0x3d8	4	Alert Cause Register
alert_handler.ALERT_CAUSE_46	0x3dc	4	Alert Cause Register
alert_handler.ALERT_CAUSE_47	0x3e0	4	Alert Cause Register
alert_handler.ALERT_CAUSE_48	0x3e4	4	Alert Cause Register
alert_handler.ALERT_CAUSE_49	0x3e8	4	Alert Cause Register
alert_handler.ALERT_CAUSE_50	0x3ec	4	Alert Cause Register
alert_handler.ALERT_CAUSE_51	0x3f0	4	Alert Cause Register
alert_handler.ALERT_CAUSE_52	0x3f4	4	Alert Cause Register
alert_handler.ALERT_CAUSE_53	0x3f8	4	Alert Cause Register
alert_handler.ALERT_CAUSE_54	0x3fc	4	Alert Cause Register
alert_handler.ALERT_CAUSE_55	0x400	4	Alert Cause Register
alert_handler.ALERT_CAUSE_56	0x404	4	Alert Cause Register
alert_handler.ALERT_CAUSE_57	0x408	4	Alert Cause Register
alert_handler.ALERT_CAUSE_58	0x40c	4	Alert Cause Register
alert_handler.ALERT_CAUSE_59	0x410	4	Alert Cause Register
alert_handler.ALERT_CAUSE_60	0x414	4	Alert Cause Register
alert_handler.ALERT_CAUSE_61	0x418	4	Alert Cause Register
alert_handler.ALERT_CAUSE_62	0x41c	4	Alert Cause Register
alert_handler.ALERT_CAUSE_63	0x420	4	Alert Cause Register
alert_handler.ALERT_CAUSE_64	0x424	4	Alert Cause Register
alert_handler.LOC_ALERT_REGWEN_0	0x428	4	Register write enable for alert enable bits.
alert_handler.LOC_ALERT_REGWEN_1	0x42c	4	Register write enable for alert enable bits.
alert_handler.LOC_ALERT_REGWEN_2	0x430	4	Register write enable for alert enable bits.
alert_handler.LOC_ALERT_REGWEN_3	0x434	4	Register write enable for alert enable bits.
alert_handler.LOC_ALERT_REGWEN_4	0x438	4	Register write enable for alert enable bits.
alert_handler.LOC_ALERT_REGWEN_5	0x43c	4	Register write enable for alert enable bits.
alert_handler.LOC_ALERT_REGWEN_6	0x440	4	Register write enable for alert enable bits.
alert_handler.LOC_ALERT_EN_SHADOWED_0	0x444	4	Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_EN_SHADOWED_1	0x448	4	Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_EN_SHADOWED_2	0x44c	4	Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_EN_SHADOWED_3	0x450	4	Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_EN_SHADOWED_4	0x454	4	Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_EN_SHADOWED_5	0x458	4	Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_EN_SHADOWED_6	0x45c	4	Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_CLASS_SHADOWED_0	0x460	4	Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_CLASS_SHADOWED_1	0x464	4	Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_CLASS_SHADOWED_2	0x468	4	Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_CLASS_SHADOWED_3	0x46c	4	Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_CLASS_SHADOWED_4	0x470	4	Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_CLASS_SHADOWED_5	0x474	4	Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_CLASS_SHADOWED_6	0x478	4	Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_CAUSE_0	0x47c	4	Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_CAUSE_1	0x480	4	Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_CAUSE_2	0x484	4	Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_CAUSE_3	0x488	4	Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_CAUSE_4	0x48c	4	Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_CAUSE_5	0x490	4	Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.LOC_ALERT_CAUSE_6	0x494	4	Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).
alert_handler.CLASSA_REGWEN	0x498	4	Lock bit for Class A configuration.
alert_handler.CLASSA_CTRL_SHADOWED	0x49c	4	Escalation control register for alert Class A. Can not be modified if `CLASSA_REGWEN` is false.
alert_handler.CLASSA_CLR_REGWEN	0x4a0	4	Clear enable for escalation protocol of Class A alerts.
alert_handler.CLASSA_CLR_SHADOWED	0x4a4	4	Clear for escalation protocol of Class A.
alert_handler.CLASSA_ACCUM_CNT	0x4a8	4	Current accumulation value for alert Class A. Software can clear this register with a write to `CLASSA_CLR_SHADOWED` register unless `CLASSA_CLR_REGWEN` is false.
alert_handler.CLASSA_ACCUM_THRESH_SHADOWED	0x4ac	4	Accumulation threshold value for alert Class A.
alert_handler.CLASSA_TIMEOUT_CYC_SHADOWED	0x4b0	4	Interrupt timeout in cycles.
alert_handler.CLASSA_CRASHDUMP_TRIGGER_SHADOWED	0x4b4	4	Crashdump trigger configuration for Class A.
alert_handler.CLASSA_PHASE0_CYC_SHADOWED	0x4b8	4	Duration of escalation phase 0 for Class A.
alert_handler.CLASSA_PHASE1_CYC_SHADOWED	0x4bc	4	Duration of escalation phase 1 for Class A.
alert_handler.CLASSA_PHASE2_CYC_SHADOWED	0x4c0	4	Duration of escalation phase 2 for Class A.
alert_handler.CLASSA_PHASE3_CYC_SHADOWED	0x4c4	4	Duration of escalation phase 3 for Class A.
alert_handler.CLASSA_ESC_CNT	0x4c8	4	Escalation counter in cycles for Class A.
alert_handler.CLASSA_STATE	0x4cc	4	Current escalation state of Class A. See also `CLASSA_ESC_CNT`.
alert_handler.CLASSB_REGWEN	0x4d0	4	Lock bit for Class B configuration.
alert_handler.CLASSB_CTRL_SHADOWED	0x4d4	4	Escalation control register for alert Class B. Can not be modified if `CLASSB_REGWEN` is false.
alert_handler.CLASSB_CLR_REGWEN	0x4d8	4	Clear enable for escalation protocol of Class B alerts.
alert_handler.CLASSB_CLR_SHADOWED	0x4dc	4	Clear for escalation protocol of Class B.
alert_handler.CLASSB_ACCUM_CNT	0x4e0	4	Current accumulation value for alert Class B. Software can clear this register with a write to `CLASSB_CLR_SHADOWED` register unless `CLASSB_CLR_REGWEN` is false.
alert_handler.CLASSB_ACCUM_THRESH_SHADOWED	0x4e4	4	Accumulation threshold value for alert Class B.
alert_handler.CLASSB_TIMEOUT_CYC_SHADOWED	0x4e8	4	Interrupt timeout in cycles.
alert_handler.CLASSB_CRASHDUMP_TRIGGER_SHADOWED	0x4ec	4	Crashdump trigger configuration for Class B.
alert_handler.CLASSB_PHASE0_CYC_SHADOWED	0x4f0	4	Duration of escalation phase 0 for Class B.
alert_handler.CLASSB_PHASE1_CYC_SHADOWED	0x4f4	4	Duration of escalation phase 1 for Class B.
alert_handler.CLASSB_PHASE2_CYC_SHADOWED	0x4f8	4	Duration of escalation phase 2 for Class B.
alert_handler.CLASSB_PHASE3_CYC_SHADOWED	0x4fc	4	Duration of escalation phase 3 for Class B.
alert_handler.CLASSB_ESC_CNT	0x500	4	Escalation counter in cycles for Class B.
alert_handler.CLASSB_STATE	0x504	4	Current escalation state of Class B. See also `CLASSB_ESC_CNT`.
alert_handler.CLASSC_REGWEN	0x508	4	Lock bit for Class C configuration.
alert_handler.CLASSC_CTRL_SHADOWED	0x50c	4	Escalation control register for alert Class C. Can not be modified if `CLASSC_REGWEN` is false.
alert_handler.CLASSC_CLR_REGWEN	0x510	4	Clear enable for escalation protocol of Class C alerts.
alert_handler.CLASSC_CLR_SHADOWED	0x514	4	Clear for escalation protocol of Class C.
alert_handler.CLASSC_ACCUM_CNT	0x518	4	Current accumulation value for alert Class C. Software can clear this register with a write to `CLASSC_CLR_SHADOWED` register unless `CLASSC_CLR_REGWEN` is false.
alert_handler.CLASSC_ACCUM_THRESH_SHADOWED	0x51c	4	Accumulation threshold value for alert Class C.
alert_handler.CLASSC_TIMEOUT_CYC_SHADOWED	0x520	4	Interrupt timeout in cycles.
alert_handler.CLASSC_CRASHDUMP_TRIGGER_SHADOWED	0x524	4	Crashdump trigger configuration for Class C.
alert_handler.CLASSC_PHASE0_CYC_SHADOWED	0x528	4	Duration of escalation phase 0 for Class C.
alert_handler.CLASSC_PHASE1_CYC_SHADOWED	0x52c	4	Duration of escalation phase 1 for Class C.
alert_handler.CLASSC_PHASE2_CYC_SHADOWED	0x530	4	Duration of escalation phase 2 for Class C.
alert_handler.CLASSC_PHASE3_CYC_SHADOWED	0x534	4	Duration of escalation phase 3 for Class C.
alert_handler.CLASSC_ESC_CNT	0x538	4	Escalation counter in cycles for Class C.
alert_handler.CLASSC_STATE	0x53c	4	Current escalation state of Class C. See also `CLASSC_ESC_CNT`.
alert_handler.CLASSD_REGWEN	0x540	4	Lock bit for Class D configuration.
alert_handler.CLASSD_CTRL_SHADOWED	0x544	4	Escalation control register for alert Class D. Can not be modified if `CLASSD_REGWEN` is false.
alert_handler.CLASSD_CLR_REGWEN	0x548	4	Clear enable for escalation protocol of Class D alerts.
alert_handler.CLASSD_CLR_SHADOWED	0x54c	4	Clear for escalation protocol of Class D.
alert_handler.CLASSD_ACCUM_CNT	0x550	4	Current accumulation value for alert Class D. Software can clear this register with a write to `CLASSD_CLR_SHADOWED` register unless `CLASSD_CLR_REGWEN` is false.
alert_handler.CLASSD_ACCUM_THRESH_SHADOWED	0x554	4	Accumulation threshold value for alert Class D.
alert_handler.CLASSD_TIMEOUT_CYC_SHADOWED	0x558	4	Interrupt timeout in cycles.
alert_handler.CLASSD_CRASHDUMP_TRIGGER_SHADOWED	0x55c	4	Crashdump trigger configuration for Class D.
alert_handler.CLASSD_PHASE0_CYC_SHADOWED	0x560	4	Duration of escalation phase 0 for Class D.
alert_handler.CLASSD_PHASE1_CYC_SHADOWED	0x564	4	Duration of escalation phase 1 for Class D.
alert_handler.CLASSD_PHASE2_CYC_SHADOWED	0x568	4	Duration of escalation phase 2 for Class D.
alert_handler.CLASSD_PHASE3_CYC_SHADOWED	0x56c	4	Duration of escalation phase 3 for Class D.
alert_handler.CLASSD_ESC_CNT	0x570	4	Escalation counter in cycles for Class D.
alert_handler.CLASSD_STATE	0x574	4	Current escalation state of Class D. See also `CLASSD_ESC_CNT`.

alert_handler.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												classd	classc	classb	classa

Bits

Type

Reset

Name

Description

rw1c

0x0

classa

Interrupt state bit of Class A. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.

rw1c

0x0

classb

Interrupt state bit of Class B. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.

rw1c

0x0

classc

Interrupt state bit of Class C. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.

rw1c

0x0

classd

Interrupt state bit of Class D. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.

alert_handler.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												classd	classc	classb	classa

Bits Type Reset Name Description

0x0

classa

Enable interrupt when INTR_STATE.classa is set.

0x0

classb

Enable interrupt when INTR_STATE.classb is set.

0x0

classc

Enable interrupt when INTR_STATE.classc is set.

0x0

classd

Enable interrupt when INTR_STATE.classd is set.

alert_handler.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												classd	classc	classb	classa

Bits Type Reset Name Description

0x0

classa

Write 1 to force INTR_STATE.classa to 1.

0x0

classb

Write 1 to force INTR_STATE.classb to 1.

0x0

classc

Write 1 to force INTR_STATE.classc to 1.

0x0

classd

Write 1 to force INTR_STATE.classd to 1.

alert_handler.PING_TIMER_REGWEN @ 0xc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															PING_TIMER_REGWEN

Bits Type Reset Name Description

rw0c

0x1

PING_TIMER_REGWEN

When true, the PING_TIMEOUT_CYC_SHADOWED and PING_TIMER_EN_SHADOWED registers can be modified. When false, they become read-only. Defaults true, write one to clear. This should be cleared once the alert handler has been configured and the ping timer mechanism has been kicked off.

alert_handler.PING_TIMEOUT_CYC_SHADOWED @ 0x10

Ping timeout cycle count.

Reset default = 0x100, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PING_TIMEOUT_CYC_SHADOWED

Bits

Type

Reset

Name

Description

15:0

0x100

PING_TIMEOUT_CYC_SHADOWED

Timeout value in cycles. If an alert receiver or an escalation sender does not respond to a ping within this timeout window, a pingfail alert will be raised. It is recommended to set this value to the equivalent of 256 cycles of the slowest alert sender clock domain in the system (or greater).

alert_handler.PING_TIMER_EN_SHADOWED @ 0x14

Ping timer enable.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															PING_TIMER_EN_SHADOWED

Bits

Type

Reset

Name

Description

rw1s

0x0

PING_TIMER_EN_SHADOWED

Setting this to 1 enables the ping timer mechanism. This bit cannot be cleared to 0 once it has been set to 1.

Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.

alert_handler.ALERT_REGWEN_0 @ 0x18

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits Type Reset Name Description

rw0c

0x1

EN_0

Alert configuration write enable bit. If this is cleared to 0, the corresponding ALERT_EN_SHADOWED and ALERT_CLASS_SHADOWED bits are not writable anymore.

Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.

alert_handler.ALERT_REGWEN_1 @ 0x1c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For alert1

alert_handler.ALERT_REGWEN_2 @ 0x20

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_2

For alert2

alert_handler.ALERT_REGWEN_3 @ 0x24

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_3

For alert3

alert_handler.ALERT_REGWEN_4 @ 0x28

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_4

For alert4

alert_handler.ALERT_REGWEN_5 @ 0x2c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_5

For alert5

alert_handler.ALERT_REGWEN_6 @ 0x30

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_6

For alert6

alert_handler.ALERT_REGWEN_7 @ 0x34

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_7

For alert7

alert_handler.ALERT_REGWEN_8 @ 0x38

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_8

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_8

For alert8

alert_handler.ALERT_REGWEN_9 @ 0x3c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_9

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_9

For alert9

alert_handler.ALERT_REGWEN_10 @ 0x40

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_10

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_10

For alert10

alert_handler.ALERT_REGWEN_11 @ 0x44

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_11

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_11

For alert11

alert_handler.ALERT_REGWEN_12 @ 0x48

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_12

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_12

For alert12

alert_handler.ALERT_REGWEN_13 @ 0x4c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_13

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_13

For alert13

alert_handler.ALERT_REGWEN_14 @ 0x50

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_14

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_14

For alert14

alert_handler.ALERT_REGWEN_15 @ 0x54

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_15

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_15

For alert15

alert_handler.ALERT_REGWEN_16 @ 0x58

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_16

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_16

For alert16

alert_handler.ALERT_REGWEN_17 @ 0x5c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_17

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_17

For alert17

alert_handler.ALERT_REGWEN_18 @ 0x60

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_18

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_18

For alert18

alert_handler.ALERT_REGWEN_19 @ 0x64

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_19

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_19

For alert19

alert_handler.ALERT_REGWEN_20 @ 0x68

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_20

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_20

For alert20

alert_handler.ALERT_REGWEN_21 @ 0x6c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_21

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_21

For alert21

alert_handler.ALERT_REGWEN_22 @ 0x70

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_22

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_22

For alert22

alert_handler.ALERT_REGWEN_23 @ 0x74

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_23

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_23

For alert23

alert_handler.ALERT_REGWEN_24 @ 0x78

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_24

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_24

For alert24

alert_handler.ALERT_REGWEN_25 @ 0x7c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_25

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_25

For alert25

alert_handler.ALERT_REGWEN_26 @ 0x80

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_26

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_26

For alert26

alert_handler.ALERT_REGWEN_27 @ 0x84

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_27

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_27

For alert27

alert_handler.ALERT_REGWEN_28 @ 0x88

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_28

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_28

For alert28

alert_handler.ALERT_REGWEN_29 @ 0x8c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_29

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_29

For alert29

alert_handler.ALERT_REGWEN_30 @ 0x90

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_30

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_30

For alert30

alert_handler.ALERT_REGWEN_31 @ 0x94

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_31

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_31

For alert31

alert_handler.ALERT_REGWEN_32 @ 0x98

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_32

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_32

For alert32

alert_handler.ALERT_REGWEN_33 @ 0x9c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_33

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_33

For alert33

alert_handler.ALERT_REGWEN_34 @ 0xa0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_34

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_34

For alert34

alert_handler.ALERT_REGWEN_35 @ 0xa4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_35

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_35

For alert35

alert_handler.ALERT_REGWEN_36 @ 0xa8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_36

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_36

For alert36

alert_handler.ALERT_REGWEN_37 @ 0xac

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_37

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_37

For alert37

alert_handler.ALERT_REGWEN_38 @ 0xb0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_38

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_38

For alert38

alert_handler.ALERT_REGWEN_39 @ 0xb4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_39

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_39

For alert39

alert_handler.ALERT_REGWEN_40 @ 0xb8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_40

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_40

For alert40

alert_handler.ALERT_REGWEN_41 @ 0xbc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_41

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_41

For alert41

alert_handler.ALERT_REGWEN_42 @ 0xc0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_42

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_42

For alert42

alert_handler.ALERT_REGWEN_43 @ 0xc4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_43

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_43

For alert43

alert_handler.ALERT_REGWEN_44 @ 0xc8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_44

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_44

For alert44

alert_handler.ALERT_REGWEN_45 @ 0xcc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_45

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_45

For alert45

alert_handler.ALERT_REGWEN_46 @ 0xd0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_46

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_46

For alert46

alert_handler.ALERT_REGWEN_47 @ 0xd4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_47

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_47

For alert47

alert_handler.ALERT_REGWEN_48 @ 0xd8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_48

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_48

For alert48

alert_handler.ALERT_REGWEN_49 @ 0xdc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_49

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_49

For alert49

alert_handler.ALERT_REGWEN_50 @ 0xe0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_50

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_50

For alert50

alert_handler.ALERT_REGWEN_51 @ 0xe4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_51

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_51

For alert51

alert_handler.ALERT_REGWEN_52 @ 0xe8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_52

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_52

For alert52

alert_handler.ALERT_REGWEN_53 @ 0xec

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_53

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_53

For alert53

alert_handler.ALERT_REGWEN_54 @ 0xf0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_54

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_54

For alert54

alert_handler.ALERT_REGWEN_55 @ 0xf4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_55

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_55

For alert55

alert_handler.ALERT_REGWEN_56 @ 0xf8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_56

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_56

For alert56

alert_handler.ALERT_REGWEN_57 @ 0xfc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_57

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_57

For alert57

alert_handler.ALERT_REGWEN_58 @ 0x100

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_58

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_58

For alert58

alert_handler.ALERT_REGWEN_59 @ 0x104

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_59

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_59

For alert59

alert_handler.ALERT_REGWEN_60 @ 0x108

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_60

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_60

For alert60

alert_handler.ALERT_REGWEN_61 @ 0x10c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_61

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_61

For alert61

alert_handler.ALERT_REGWEN_62 @ 0x110

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_62

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_62

For alert62

alert_handler.ALERT_REGWEN_63 @ 0x114

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_63

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_63

For alert63

alert_handler.ALERT_REGWEN_64 @ 0x118

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_64

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_64

For alert64

alert_handler.ALERT_EN_SHADOWED_0 @ 0x11c

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_0

Bits

Type

Reset

Name

Description

0x0

EN_A_0

Alert enable bit.

Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.

alert_handler.ALERT_EN_SHADOWED_1 @ 0x120

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_1

Bits

Type

Reset

Name

Description

0x0

EN_A_1

For alert1

alert_handler.ALERT_EN_SHADOWED_2 @ 0x124

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_2

Bits

Type

Reset

Name

Description

0x0

EN_A_2

For alert2

alert_handler.ALERT_EN_SHADOWED_3 @ 0x128

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_3

Bits

Type

Reset

Name

Description

0x0

EN_A_3

For alert3

alert_handler.ALERT_EN_SHADOWED_4 @ 0x12c

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_4

Bits

Type

Reset

Name

Description

0x0

EN_A_4

For alert4

alert_handler.ALERT_EN_SHADOWED_5 @ 0x130

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_5

Bits

Type

Reset

Name

Description

0x0

EN_A_5

For alert5

alert_handler.ALERT_EN_SHADOWED_6 @ 0x134

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_6

Bits

Type

Reset

Name

Description

0x0

EN_A_6

For alert6

alert_handler.ALERT_EN_SHADOWED_7 @ 0x138

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_7

Bits

Type

Reset

Name

Description

0x0

EN_A_7

For alert7

alert_handler.ALERT_EN_SHADOWED_8 @ 0x13c

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_8

Bits

Type

Reset

Name

Description

0x0

EN_A_8

For alert8

alert_handler.ALERT_EN_SHADOWED_9 @ 0x140

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_9

Bits

Type

Reset

Name

Description

0x0

EN_A_9

For alert9

alert_handler.ALERT_EN_SHADOWED_10 @ 0x144

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_10

Bits

Type

Reset

Name

Description

0x0

EN_A_10

For alert10

alert_handler.ALERT_EN_SHADOWED_11 @ 0x148

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_11

Bits

Type

Reset

Name

Description

0x0

EN_A_11

For alert11

alert_handler.ALERT_EN_SHADOWED_12 @ 0x14c

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_12

Bits

Type

Reset

Name

Description

0x0

EN_A_12

For alert12

alert_handler.ALERT_EN_SHADOWED_13 @ 0x150

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_13

Bits

Type

Reset

Name

Description

0x0

EN_A_13

For alert13

alert_handler.ALERT_EN_SHADOWED_14 @ 0x154

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_14

Bits

Type

Reset

Name

Description

0x0

EN_A_14

For alert14

alert_handler.ALERT_EN_SHADOWED_15 @ 0x158

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_15

Bits

Type

Reset

Name

Description

0x0

EN_A_15

For alert15

alert_handler.ALERT_EN_SHADOWED_16 @ 0x15c

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_16

Bits

Type

Reset

Name

Description

0x0

EN_A_16

For alert16

alert_handler.ALERT_EN_SHADOWED_17 @ 0x160

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_17

Bits

Type

Reset

Name

Description

0x0

EN_A_17

For alert17

alert_handler.ALERT_EN_SHADOWED_18 @ 0x164

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_18

Bits

Type

Reset

Name

Description

0x0

EN_A_18

For alert18

alert_handler.ALERT_EN_SHADOWED_19 @ 0x168

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_19

Bits

Type

Reset

Name

Description

0x0

EN_A_19

For alert19

alert_handler.ALERT_EN_SHADOWED_20 @ 0x16c

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_20

Bits

Type

Reset

Name

Description

0x0

EN_A_20

For alert20

alert_handler.ALERT_EN_SHADOWED_21 @ 0x170

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_21

Bits

Type

Reset

Name

Description

0x0

EN_A_21

For alert21

alert_handler.ALERT_EN_SHADOWED_22 @ 0x174

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_22

Bits

Type

Reset

Name

Description

0x0

EN_A_22

For alert22

alert_handler.ALERT_EN_SHADOWED_23 @ 0x178

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_23

Bits

Type

Reset

Name

Description

0x0

EN_A_23

For alert23

alert_handler.ALERT_EN_SHADOWED_24 @ 0x17c

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_24

Bits

Type

Reset

Name

Description

0x0

EN_A_24

For alert24

alert_handler.ALERT_EN_SHADOWED_25 @ 0x180

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_25

Bits

Type

Reset

Name

Description

0x0

EN_A_25

For alert25

alert_handler.ALERT_EN_SHADOWED_26 @ 0x184

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_26

Bits

Type

Reset

Name

Description

0x0

EN_A_26

For alert26

alert_handler.ALERT_EN_SHADOWED_27 @ 0x188

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_27

Bits

Type

Reset

Name

Description

0x0

EN_A_27

For alert27

alert_handler.ALERT_EN_SHADOWED_28 @ 0x18c

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_28

Bits

Type

Reset

Name

Description

0x0

EN_A_28

For alert28

alert_handler.ALERT_EN_SHADOWED_29 @ 0x190

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_29

Bits

Type

Reset

Name

Description

0x0

EN_A_29

For alert29

alert_handler.ALERT_EN_SHADOWED_30 @ 0x194

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_30

Bits

Type

Reset

Name

Description

0x0

EN_A_30

For alert30

alert_handler.ALERT_EN_SHADOWED_31 @ 0x198

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_31

Bits

Type

Reset

Name

Description

0x0

EN_A_31

For alert31

alert_handler.ALERT_EN_SHADOWED_32 @ 0x19c

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_32

Bits

Type

Reset

Name

Description

0x0

EN_A_32

For alert32

alert_handler.ALERT_EN_SHADOWED_33 @ 0x1a0

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_33

Bits

Type

Reset

Name

Description

0x0

EN_A_33

For alert33

alert_handler.ALERT_EN_SHADOWED_34 @ 0x1a4

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_34

Bits

Type

Reset

Name

Description

0x0

EN_A_34

For alert34

alert_handler.ALERT_EN_SHADOWED_35 @ 0x1a8

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_35

Bits

Type

Reset

Name

Description

0x0

EN_A_35

For alert35

alert_handler.ALERT_EN_SHADOWED_36 @ 0x1ac

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_36

Bits

Type

Reset

Name

Description

0x0

EN_A_36

For alert36

alert_handler.ALERT_EN_SHADOWED_37 @ 0x1b0

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_37

Bits

Type

Reset

Name

Description

0x0

EN_A_37

For alert37

alert_handler.ALERT_EN_SHADOWED_38 @ 0x1b4

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_38

Bits

Type

Reset

Name

Description

0x0

EN_A_38

For alert38

alert_handler.ALERT_EN_SHADOWED_39 @ 0x1b8

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_39

Bits

Type

Reset

Name

Description

0x0

EN_A_39

For alert39

alert_handler.ALERT_EN_SHADOWED_40 @ 0x1bc

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_40

Bits

Type

Reset

Name

Description

0x0

EN_A_40

For alert40

alert_handler.ALERT_EN_SHADOWED_41 @ 0x1c0

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_41

Bits

Type

Reset

Name

Description

0x0

EN_A_41

For alert41

alert_handler.ALERT_EN_SHADOWED_42 @ 0x1c4

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_42

Bits

Type

Reset

Name

Description

0x0

EN_A_42

For alert42

alert_handler.ALERT_EN_SHADOWED_43 @ 0x1c8

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_43

Bits

Type

Reset

Name

Description

0x0

EN_A_43

For alert43

alert_handler.ALERT_EN_SHADOWED_44 @ 0x1cc

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_44

Bits

Type

Reset

Name

Description

0x0

EN_A_44

For alert44

alert_handler.ALERT_EN_SHADOWED_45 @ 0x1d0

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_45

Bits

Type

Reset

Name

Description

0x0

EN_A_45

For alert45

alert_handler.ALERT_EN_SHADOWED_46 @ 0x1d4

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_46

Bits

Type

Reset

Name

Description

0x0

EN_A_46

For alert46

alert_handler.ALERT_EN_SHADOWED_47 @ 0x1d8

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_47

Bits

Type

Reset

Name

Description

0x0

EN_A_47

For alert47

alert_handler.ALERT_EN_SHADOWED_48 @ 0x1dc

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_48

Bits

Type

Reset

Name

Description

0x0

EN_A_48

For alert48

alert_handler.ALERT_EN_SHADOWED_49 @ 0x1e0

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_49

Bits

Type

Reset

Name

Description

0x0

EN_A_49

For alert49

alert_handler.ALERT_EN_SHADOWED_50 @ 0x1e4

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_50

Bits

Type

Reset

Name

Description

0x0

EN_A_50

For alert50

alert_handler.ALERT_EN_SHADOWED_51 @ 0x1e8

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_51

Bits

Type

Reset

Name

Description

0x0

EN_A_51

For alert51

alert_handler.ALERT_EN_SHADOWED_52 @ 0x1ec

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_52

Bits

Type

Reset

Name

Description

0x0

EN_A_52

For alert52

alert_handler.ALERT_EN_SHADOWED_53 @ 0x1f0

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_53

Bits

Type

Reset

Name

Description

0x0

EN_A_53

For alert53

alert_handler.ALERT_EN_SHADOWED_54 @ 0x1f4

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_54

Bits

Type

Reset

Name

Description

0x0

EN_A_54

For alert54

alert_handler.ALERT_EN_SHADOWED_55 @ 0x1f8

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_55

Bits

Type

Reset

Name

Description

0x0

EN_A_55

For alert55

alert_handler.ALERT_EN_SHADOWED_56 @ 0x1fc

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_56

Bits

Type

Reset

Name

Description

0x0

EN_A_56

For alert56

alert_handler.ALERT_EN_SHADOWED_57 @ 0x200

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_57

Bits

Type

Reset

Name

Description

0x0

EN_A_57

For alert57

alert_handler.ALERT_EN_SHADOWED_58 @ 0x204

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_58

Bits

Type

Reset

Name

Description

0x0

EN_A_58

For alert58

alert_handler.ALERT_EN_SHADOWED_59 @ 0x208

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_59

Bits

Type

Reset

Name

Description

0x0

EN_A_59

For alert59

alert_handler.ALERT_EN_SHADOWED_60 @ 0x20c

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_60

Bits

Type

Reset

Name

Description

0x0

EN_A_60

For alert60

alert_handler.ALERT_EN_SHADOWED_61 @ 0x210

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_61

Bits

Type

Reset

Name

Description

0x0

EN_A_61

For alert61

alert_handler.ALERT_EN_SHADOWED_62 @ 0x214

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_62

Bits

Type

Reset

Name

Description

0x0

EN_A_62

For alert62

alert_handler.ALERT_EN_SHADOWED_63 @ 0x218

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_63

Bits

Type

Reset

Name

Description

0x0

EN_A_63

For alert63

alert_handler.ALERT_EN_SHADOWED_64 @ 0x21c

Enable register for alerts.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_A_64

Bits

Type

Reset

Name

Description

0x0

EN_A_64

For alert64

alert_handler.ALERT_CLASS_SHADOWED_0 @ 0x220

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_0

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_0

Classification

0x0	ClassA
0x1	ClassB
0x2	ClassC
0x3	ClassD

alert_handler.ALERT_CLASS_SHADOWED_1 @ 0x224

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_1

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_1

For alert1

alert_handler.ALERT_CLASS_SHADOWED_2 @ 0x228

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_2

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_2

For alert2

alert_handler.ALERT_CLASS_SHADOWED_3 @ 0x22c

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_3

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_3

For alert3

alert_handler.ALERT_CLASS_SHADOWED_4 @ 0x230

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_4

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_4

For alert4

alert_handler.ALERT_CLASS_SHADOWED_5 @ 0x234

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_5

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_5

For alert5

alert_handler.ALERT_CLASS_SHADOWED_6 @ 0x238

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_6

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_6

For alert6

alert_handler.ALERT_CLASS_SHADOWED_7 @ 0x23c

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_7

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_7

For alert7

alert_handler.ALERT_CLASS_SHADOWED_8 @ 0x240

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_8

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_8

For alert8

alert_handler.ALERT_CLASS_SHADOWED_9 @ 0x244

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_9

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_9

For alert9

alert_handler.ALERT_CLASS_SHADOWED_10 @ 0x248

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_10

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_10

For alert10

alert_handler.ALERT_CLASS_SHADOWED_11 @ 0x24c

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_11

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_11

For alert11

alert_handler.ALERT_CLASS_SHADOWED_12 @ 0x250

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_12

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_12

For alert12

alert_handler.ALERT_CLASS_SHADOWED_13 @ 0x254

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_13

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_13

For alert13

alert_handler.ALERT_CLASS_SHADOWED_14 @ 0x258

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_14

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_14

For alert14

alert_handler.ALERT_CLASS_SHADOWED_15 @ 0x25c

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_15

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_15

For alert15

alert_handler.ALERT_CLASS_SHADOWED_16 @ 0x260

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_16

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_16

For alert16

alert_handler.ALERT_CLASS_SHADOWED_17 @ 0x264

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_17

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_17

For alert17

alert_handler.ALERT_CLASS_SHADOWED_18 @ 0x268

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_18

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_18

For alert18

alert_handler.ALERT_CLASS_SHADOWED_19 @ 0x26c

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_19

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_19

For alert19

alert_handler.ALERT_CLASS_SHADOWED_20 @ 0x270

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_20

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_20

For alert20

alert_handler.ALERT_CLASS_SHADOWED_21 @ 0x274

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_21

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_21

For alert21

alert_handler.ALERT_CLASS_SHADOWED_22 @ 0x278

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_22

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_22

For alert22

alert_handler.ALERT_CLASS_SHADOWED_23 @ 0x27c

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_23

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_23

For alert23

alert_handler.ALERT_CLASS_SHADOWED_24 @ 0x280

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_24

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_24

For alert24

alert_handler.ALERT_CLASS_SHADOWED_25 @ 0x284

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_25

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_25

For alert25

alert_handler.ALERT_CLASS_SHADOWED_26 @ 0x288

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_26

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_26

For alert26

alert_handler.ALERT_CLASS_SHADOWED_27 @ 0x28c

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_27

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_27

For alert27

alert_handler.ALERT_CLASS_SHADOWED_28 @ 0x290

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_28

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_28

For alert28

alert_handler.ALERT_CLASS_SHADOWED_29 @ 0x294

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_29

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_29

For alert29

alert_handler.ALERT_CLASS_SHADOWED_30 @ 0x298

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_30

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_30

For alert30

alert_handler.ALERT_CLASS_SHADOWED_31 @ 0x29c

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_31

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_31

For alert31

alert_handler.ALERT_CLASS_SHADOWED_32 @ 0x2a0

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_32

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_32

For alert32

alert_handler.ALERT_CLASS_SHADOWED_33 @ 0x2a4

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_33

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_33

For alert33

alert_handler.ALERT_CLASS_SHADOWED_34 @ 0x2a8

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_34

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_34

For alert34

alert_handler.ALERT_CLASS_SHADOWED_35 @ 0x2ac

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_35

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_35

For alert35

alert_handler.ALERT_CLASS_SHADOWED_36 @ 0x2b0

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_36

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_36

For alert36

alert_handler.ALERT_CLASS_SHADOWED_37 @ 0x2b4

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_37

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_37

For alert37

alert_handler.ALERT_CLASS_SHADOWED_38 @ 0x2b8

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_38

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_38

For alert38

alert_handler.ALERT_CLASS_SHADOWED_39 @ 0x2bc

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_39

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_39

For alert39

alert_handler.ALERT_CLASS_SHADOWED_40 @ 0x2c0

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_40

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_40

For alert40

alert_handler.ALERT_CLASS_SHADOWED_41 @ 0x2c4

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_41

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_41

For alert41

alert_handler.ALERT_CLASS_SHADOWED_42 @ 0x2c8

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_42

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_42

For alert42

alert_handler.ALERT_CLASS_SHADOWED_43 @ 0x2cc

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_43

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_43

For alert43

alert_handler.ALERT_CLASS_SHADOWED_44 @ 0x2d0

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_44

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_44

For alert44

alert_handler.ALERT_CLASS_SHADOWED_45 @ 0x2d4

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_45

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_45

For alert45

alert_handler.ALERT_CLASS_SHADOWED_46 @ 0x2d8

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_46

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_46

For alert46

alert_handler.ALERT_CLASS_SHADOWED_47 @ 0x2dc

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_47

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_47

For alert47

alert_handler.ALERT_CLASS_SHADOWED_48 @ 0x2e0

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_48

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_48

For alert48

alert_handler.ALERT_CLASS_SHADOWED_49 @ 0x2e4

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_49

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_49

For alert49

alert_handler.ALERT_CLASS_SHADOWED_50 @ 0x2e8

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_50

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_50

For alert50

alert_handler.ALERT_CLASS_SHADOWED_51 @ 0x2ec

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_51

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_51

For alert51

alert_handler.ALERT_CLASS_SHADOWED_52 @ 0x2f0

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_52

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_52

For alert52

alert_handler.ALERT_CLASS_SHADOWED_53 @ 0x2f4

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_53

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_53

For alert53

alert_handler.ALERT_CLASS_SHADOWED_54 @ 0x2f8

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_54

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_54

For alert54

alert_handler.ALERT_CLASS_SHADOWED_55 @ 0x2fc

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_55

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_55

For alert55

alert_handler.ALERT_CLASS_SHADOWED_56 @ 0x300

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_56

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_56

For alert56

alert_handler.ALERT_CLASS_SHADOWED_57 @ 0x304

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_57

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_57

For alert57

alert_handler.ALERT_CLASS_SHADOWED_58 @ 0x308

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_58

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_58

For alert58

alert_handler.ALERT_CLASS_SHADOWED_59 @ 0x30c

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_59

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_59

For alert59

alert_handler.ALERT_CLASS_SHADOWED_60 @ 0x310

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_60

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_60

For alert60

alert_handler.ALERT_CLASS_SHADOWED_61 @ 0x314

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_61

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_61

For alert61

alert_handler.ALERT_CLASS_SHADOWED_62 @ 0x318

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_62

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_62

For alert62

alert_handler.ALERT_CLASS_SHADOWED_63 @ 0x31c

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_63

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_63

For alert63

alert_handler.ALERT_CLASS_SHADOWED_64 @ 0x320

Class assignment of alerts.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_A_64

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_A_64

For alert64

alert_handler.ALERT_CAUSE_0 @ 0x324

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_0

Bits

Type

Reset

Name

Description

rw1c

0x0

A_0

Cause bit

alert_handler.ALERT_CAUSE_1 @ 0x328

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_1

Bits

Type

Reset

Name

Description

rw1c

0x0

A_1

For ALERT1

alert_handler.ALERT_CAUSE_2 @ 0x32c

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_2

Bits

Type

Reset

Name

Description

rw1c

0x0

A_2

For ALERT2

alert_handler.ALERT_CAUSE_3 @ 0x330

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_3

Bits

Type

Reset

Name

Description

rw1c

0x0

A_3

For ALERT3

alert_handler.ALERT_CAUSE_4 @ 0x334

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_4

Bits

Type

Reset

Name

Description

rw1c

0x0

A_4

For ALERT4

alert_handler.ALERT_CAUSE_5 @ 0x338

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_5

Bits

Type

Reset

Name

Description

rw1c

0x0

A_5

For ALERT5

alert_handler.ALERT_CAUSE_6 @ 0x33c

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_6

Bits

Type

Reset

Name

Description

rw1c

0x0

A_6

For ALERT6

alert_handler.ALERT_CAUSE_7 @ 0x340

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_7

Bits

Type

Reset

Name

Description

rw1c

0x0

A_7

For ALERT7

alert_handler.ALERT_CAUSE_8 @ 0x344

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_8

Bits

Type

Reset

Name

Description

rw1c

0x0

A_8

For ALERT8

alert_handler.ALERT_CAUSE_9 @ 0x348

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_9

Bits

Type

Reset

Name

Description

rw1c

0x0

A_9

For ALERT9

alert_handler.ALERT_CAUSE_10 @ 0x34c

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_10

Bits

Type

Reset

Name

Description

rw1c

0x0

A_10

For ALERT10

alert_handler.ALERT_CAUSE_11 @ 0x350

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_11

Bits

Type

Reset

Name

Description

rw1c

0x0

A_11

For ALERT11

alert_handler.ALERT_CAUSE_12 @ 0x354

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_12

Bits

Type

Reset

Name

Description

rw1c

0x0

A_12

For ALERT12

alert_handler.ALERT_CAUSE_13 @ 0x358

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_13

Bits

Type

Reset

Name

Description

rw1c

0x0

A_13

For ALERT13

alert_handler.ALERT_CAUSE_14 @ 0x35c

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_14

Bits

Type

Reset

Name

Description

rw1c

0x0

A_14

For ALERT14

alert_handler.ALERT_CAUSE_15 @ 0x360

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_15

Bits

Type

Reset

Name

Description

rw1c

0x0

A_15

For ALERT15

alert_handler.ALERT_CAUSE_16 @ 0x364

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_16

Bits

Type

Reset

Name

Description

rw1c

0x0

A_16

For ALERT16

alert_handler.ALERT_CAUSE_17 @ 0x368

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_17

Bits

Type

Reset

Name

Description

rw1c

0x0

A_17

For ALERT17

alert_handler.ALERT_CAUSE_18 @ 0x36c

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_18

Bits

Type

Reset

Name

Description

rw1c

0x0

A_18

For ALERT18

alert_handler.ALERT_CAUSE_19 @ 0x370

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_19

Bits

Type

Reset

Name

Description

rw1c

0x0

A_19

For ALERT19

alert_handler.ALERT_CAUSE_20 @ 0x374

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_20

Bits

Type

Reset

Name

Description

rw1c

0x0

A_20

For ALERT20

alert_handler.ALERT_CAUSE_21 @ 0x378

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_21

Bits

Type

Reset

Name

Description

rw1c

0x0

A_21

For ALERT21

alert_handler.ALERT_CAUSE_22 @ 0x37c

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_22

Bits

Type

Reset

Name

Description

rw1c

0x0

A_22

For ALERT22

alert_handler.ALERT_CAUSE_23 @ 0x380

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_23

Bits

Type

Reset

Name

Description

rw1c

0x0

A_23

For ALERT23

alert_handler.ALERT_CAUSE_24 @ 0x384

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_24

Bits

Type

Reset

Name

Description

rw1c

0x0

A_24

For ALERT24

alert_handler.ALERT_CAUSE_25 @ 0x388

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_25

Bits

Type

Reset

Name

Description

rw1c

0x0

A_25

For ALERT25

alert_handler.ALERT_CAUSE_26 @ 0x38c

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_26

Bits

Type

Reset

Name

Description

rw1c

0x0

A_26

For ALERT26

alert_handler.ALERT_CAUSE_27 @ 0x390

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_27

Bits

Type

Reset

Name

Description

rw1c

0x0

A_27

For ALERT27

alert_handler.ALERT_CAUSE_28 @ 0x394

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_28

Bits

Type

Reset

Name

Description

rw1c

0x0

A_28

For ALERT28

alert_handler.ALERT_CAUSE_29 @ 0x398

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_29

Bits

Type

Reset

Name

Description

rw1c

0x0

A_29

For ALERT29

alert_handler.ALERT_CAUSE_30 @ 0x39c

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_30

Bits

Type

Reset

Name

Description

rw1c

0x0

A_30

For ALERT30

alert_handler.ALERT_CAUSE_31 @ 0x3a0

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_31

Bits

Type

Reset

Name

Description

rw1c

0x0

A_31

For ALERT31

alert_handler.ALERT_CAUSE_32 @ 0x3a4

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_32

Bits

Type

Reset

Name

Description

rw1c

0x0

A_32

For ALERT32

alert_handler.ALERT_CAUSE_33 @ 0x3a8

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_33

Bits

Type

Reset

Name

Description

rw1c

0x0

A_33

For ALERT33

alert_handler.ALERT_CAUSE_34 @ 0x3ac

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_34

Bits

Type

Reset

Name

Description

rw1c

0x0

A_34

For ALERT34

alert_handler.ALERT_CAUSE_35 @ 0x3b0

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_35

Bits

Type

Reset

Name

Description

rw1c

0x0

A_35

For ALERT35

alert_handler.ALERT_CAUSE_36 @ 0x3b4

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_36

Bits

Type

Reset

Name

Description

rw1c

0x0

A_36

For ALERT36

alert_handler.ALERT_CAUSE_37 @ 0x3b8

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_37

Bits

Type

Reset

Name

Description

rw1c

0x0

A_37

For ALERT37

alert_handler.ALERT_CAUSE_38 @ 0x3bc

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_38

Bits

Type

Reset

Name

Description

rw1c

0x0

A_38

For ALERT38

alert_handler.ALERT_CAUSE_39 @ 0x3c0

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_39

Bits

Type

Reset

Name

Description

rw1c

0x0

A_39

For ALERT39

alert_handler.ALERT_CAUSE_40 @ 0x3c4

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_40

Bits

Type

Reset

Name

Description

rw1c

0x0

A_40

For ALERT40

alert_handler.ALERT_CAUSE_41 @ 0x3c8

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_41

Bits

Type

Reset

Name

Description

rw1c

0x0

A_41

For ALERT41

alert_handler.ALERT_CAUSE_42 @ 0x3cc

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_42

Bits

Type

Reset

Name

Description

rw1c

0x0

A_42

For ALERT42

alert_handler.ALERT_CAUSE_43 @ 0x3d0

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_43

Bits

Type

Reset

Name

Description

rw1c

0x0

A_43

For ALERT43

alert_handler.ALERT_CAUSE_44 @ 0x3d4

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_44

Bits

Type

Reset

Name

Description

rw1c

0x0

A_44

For ALERT44

alert_handler.ALERT_CAUSE_45 @ 0x3d8

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_45

Bits

Type

Reset

Name

Description

rw1c

0x0

A_45

For ALERT45

alert_handler.ALERT_CAUSE_46 @ 0x3dc

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_46

Bits

Type

Reset

Name

Description

rw1c

0x0

A_46

For ALERT46

alert_handler.ALERT_CAUSE_47 @ 0x3e0

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_47

Bits

Type

Reset

Name

Description

rw1c

0x0

A_47

For ALERT47

alert_handler.ALERT_CAUSE_48 @ 0x3e4

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_48

Bits

Type

Reset

Name

Description

rw1c

0x0

A_48

For ALERT48

alert_handler.ALERT_CAUSE_49 @ 0x3e8

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_49

Bits

Type

Reset

Name

Description

rw1c

0x0

A_49

For ALERT49

alert_handler.ALERT_CAUSE_50 @ 0x3ec

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_50

Bits

Type

Reset

Name

Description

rw1c

0x0

A_50

For ALERT50

alert_handler.ALERT_CAUSE_51 @ 0x3f0

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_51

Bits

Type

Reset

Name

Description

rw1c

0x0

A_51

For ALERT51

alert_handler.ALERT_CAUSE_52 @ 0x3f4

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_52

Bits

Type

Reset

Name

Description

rw1c

0x0

A_52

For ALERT52

alert_handler.ALERT_CAUSE_53 @ 0x3f8

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_53

Bits

Type

Reset

Name

Description

rw1c

0x0

A_53

For ALERT53

alert_handler.ALERT_CAUSE_54 @ 0x3fc

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_54

Bits

Type

Reset

Name

Description

rw1c

0x0

A_54

For ALERT54

alert_handler.ALERT_CAUSE_55 @ 0x400

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_55

Bits

Type

Reset

Name

Description

rw1c

0x0

A_55

For ALERT55

alert_handler.ALERT_CAUSE_56 @ 0x404

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_56

Bits

Type

Reset

Name

Description

rw1c

0x0

A_56

For ALERT56

alert_handler.ALERT_CAUSE_57 @ 0x408

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_57

Bits

Type

Reset

Name

Description

rw1c

0x0

A_57

For ALERT57

alert_handler.ALERT_CAUSE_58 @ 0x40c

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_58

Bits

Type

Reset

Name

Description

rw1c

0x0

A_58

For ALERT58

alert_handler.ALERT_CAUSE_59 @ 0x410

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_59

Bits

Type

Reset

Name

Description

rw1c

0x0

A_59

For ALERT59

alert_handler.ALERT_CAUSE_60 @ 0x414

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_60

Bits

Type

Reset

Name

Description

rw1c

0x0

A_60

For ALERT60

alert_handler.ALERT_CAUSE_61 @ 0x418

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_61

Bits

Type

Reset

Name

Description

rw1c

0x0

A_61

For ALERT61

alert_handler.ALERT_CAUSE_62 @ 0x41c

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_62

Bits

Type

Reset

Name

Description

rw1c

0x0

A_62

For ALERT62

alert_handler.ALERT_CAUSE_63 @ 0x420

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_63

Bits

Type

Reset

Name

Description

rw1c

0x0

A_63

For ALERT63

alert_handler.ALERT_CAUSE_64 @ 0x424

Alert Cause Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															A_64

Bits

Type

Reset

Name

Description

rw1c

0x0

A_64

For ALERT64

alert_handler.LOC_ALERT_REGWEN_0 @ 0x428

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits Type Reset Name Description

rw0c

0x1

EN_0

Alert configuration write enable bit. If this is cleared to 0, the corresponding LOC_ALERT_EN_SHADOWED and LOC_ALERT_CLASS_SHADOWED bits are not writable anymore.

Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.

alert_handler.LOC_ALERT_REGWEN_1 @ 0x42c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For LOC_ALERT1

alert_handler.LOC_ALERT_REGWEN_2 @ 0x430

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_2

For LOC_ALERT2

alert_handler.LOC_ALERT_REGWEN_3 @ 0x434

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_3

For LOC_ALERT3

alert_handler.LOC_ALERT_REGWEN_4 @ 0x438

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_4

For LOC_ALERT4

alert_handler.LOC_ALERT_REGWEN_5 @ 0x43c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_5

For LOC_ALERT5

alert_handler.LOC_ALERT_REGWEN_6 @ 0x440

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_6

For LOC_ALERT6

alert_handler.LOC_ALERT_EN_SHADOWED_0 @ 0x444

Enable register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_LA_0

Bits

Type

Reset

Name

Description

0x0

EN_LA_0

Alert enable bit.

Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.

alert_handler.LOC_ALERT_EN_SHADOWED_1 @ 0x448

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_LA_1

Bits

Type

Reset

Name

Description

0x0

EN_LA_1

For LOC_ALERT1

alert_handler.LOC_ALERT_EN_SHADOWED_2 @ 0x44c

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_LA_2

Bits

Type

Reset

Name

Description

0x0

EN_LA_2

For LOC_ALERT2

alert_handler.LOC_ALERT_EN_SHADOWED_3 @ 0x450

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_LA_3

Bits

Type

Reset

Name

Description

0x0

EN_LA_3

For LOC_ALERT3

alert_handler.LOC_ALERT_EN_SHADOWED_4 @ 0x454

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_LA_4

Bits

Type

Reset

Name

Description

0x0

EN_LA_4

For LOC_ALERT4

alert_handler.LOC_ALERT_EN_SHADOWED_5 @ 0x458

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_LA_5

Bits

Type

Reset

Name

Description

0x0

EN_LA_5

For LOC_ALERT5

alert_handler.LOC_ALERT_EN_SHADOWED_6 @ 0x45c

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_LA_6

Bits

Type

Reset

Name

Description

0x0

EN_LA_6

For LOC_ALERT6

alert_handler.LOC_ALERT_CLASS_SHADOWED_0 @ 0x460

Class assignment of the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_LA_0

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_LA_0

Classification

0x0	ClassA
0x1	ClassB
0x2	ClassC
0x3	ClassD

alert_handler.LOC_ALERT_CLASS_SHADOWED_1 @ 0x464

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_LA_1

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_LA_1

For LOC_ALERT1

alert_handler.LOC_ALERT_CLASS_SHADOWED_2 @ 0x468

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_LA_2

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_LA_2

For LOC_ALERT2

alert_handler.LOC_ALERT_CLASS_SHADOWED_3 @ 0x46c

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_LA_3

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_LA_3

For LOC_ALERT3

alert_handler.LOC_ALERT_CLASS_SHADOWED_4 @ 0x470

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_LA_4

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_LA_4

For LOC_ALERT4

alert_handler.LOC_ALERT_CLASS_SHADOWED_5 @ 0x474

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_LA_5

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_LA_5

For LOC_ALERT5

alert_handler.LOC_ALERT_CLASS_SHADOWED_6 @ 0x478

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASS_LA_6

Bits

Type

Reset

Name

Description

1:0

0x0

CLASS_LA_6

For LOC_ALERT6

alert_handler.LOC_ALERT_CAUSE_0 @ 0x47c

Alert Cause Register for the local alerts "alert pingfail" (0), "escalation pingfail" (1), "alert integfail" (2), "escalation integfail" (3), "bus integrity failure" (4), "shadow reg update error" (5) and "shadow reg storage error" (6).

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															LA_0

Bits

Type

Reset

Name

Description

rw1c

0x0

LA_0

Cause bit

alert_handler.LOC_ALERT_CAUSE_1 @ 0x480

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															LA_1

Bits

Type

Reset

Name

Description

rw1c

0x0

LA_1

For LOC_ALERT1

alert_handler.LOC_ALERT_CAUSE_2 @ 0x484

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															LA_2

Bits

Type

Reset

Name

Description

rw1c

0x0

LA_2

For LOC_ALERT2

alert_handler.LOC_ALERT_CAUSE_3 @ 0x488

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															LA_3

Bits

Type

Reset

Name

Description

rw1c

0x0

LA_3

For LOC_ALERT3

alert_handler.LOC_ALERT_CAUSE_4 @ 0x48c

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															LA_4

Bits

Type

Reset

Name

Description

rw1c

0x0

LA_4

For LOC_ALERT4

alert_handler.LOC_ALERT_CAUSE_5 @ 0x490

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															LA_5

Bits

Type

Reset

Name

Description

rw1c

0x0

LA_5

For LOC_ALERT5

alert_handler.LOC_ALERT_CAUSE_6 @ 0x494

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															LA_6

Bits

Type

Reset

Name

Description

rw1c

0x0

LA_6

For LOC_ALERT6

alert_handler.CLASSA_REGWEN @ 0x498

Lock bit for Class A configuration.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															CLASSA_REGWEN

Bits

Type

Reset

Name

Description

rw0c

0x1

CLASSA_REGWEN

Class configuration enable bit. If this is cleared to 0, the corresponding class configuration registers cannot be written anymore.

alert_handler.CLASSA_CTRL_SHADOWED @ 0x49c

Escalation control register for alert Class A. Can not be modified if CLASSA_REGWEN is false.

Reset default = 0x393c, mask 0x3fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		MAP_E3		MAP_E2		MAP_E1		MAP_E0		EN_E3	EN_E2	EN_E1	EN_E0	LOCK	EN

Bits Type Reset Name Description

0x0

Enable escalation mechanisms (accumulation and interrupt timeout) for Class A. Note that interrupts can fire regardless of whether the escalation mechanisms are enabled for this class or not.

0x0

LOCK

Enable automatic locking of escalation counter for class A. If true, there is no way to stop the escalation protocol for class A once it has been triggered.

0x1

EN_E0

Enable escalation signal 0 for Class A

0x1

EN_E1

Enable escalation signal 1 for Class A

0x1

EN_E2

Enable escalation signal 2 for Class A

0x1

EN_E3

Enable escalation signal 3 for Class A

7:6

0x0

MAP_E0

Determines in which escalation phase escalation signal 0 shall be asserted.

9:8

0x1

MAP_E1

Determines in which escalation phase escalation signal 1 shall be asserted.

11:10

0x2

MAP_E2

Determines in which escalation phase escalation signal 2 shall be asserted.

13:12

0x3

MAP_E3

Determines in which escalation phase escalation signal 3 shall be asserted.

alert_handler.CLASSA_CLR_REGWEN @ 0x4a0

Clear enable for escalation protocol of Class A alerts.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															CLASSA_CLR_REGWEN

Bits Type Reset Name Description

rw0c

0x1

CLASSA_CLR_REGWEN

Register defaults to true, can only be cleared. This register is set to false by the hardware if the escalation protocol has been triggered and the bit CLASSA_CTRL_SHADOWED.LOCK is true.

alert_handler.CLASSA_CLR_SHADOWED @ 0x4a4

Clear for escalation protocol of Class A.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															CLASSA_CLR_SHADOWED

Bits Type Reset Name Description

0x0

CLASSA_CLR_SHADOWED

Writing 1 to this register clears the accumulator and aborts escalation (if it has been triggered). This clear is disabled if CLASSA_CLR_REGWEN is false.

alert_handler.CLASSA_ACCUM_CNT @ 0x4a8

Current accumulation value for alert Class A. Software can clear this register with a write to CLASSA_CLR_SHADOWED register unless CLASSA_CLR_REGWEN is false.

Reset default = 0x0, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLASSA_ACCUM_CNT

Bits Type Reset Name Description

15:0 ro x CLASSA_ACCUM_CNT

alert_handler.CLASSA_ACCUM_THRESH_SHADOWED @ 0x4ac

Accumulation threshold value for alert Class A.

Reset default = 0x0, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLASSA_ACCUM_THRESH_SHADOWED

Bits Type Reset Name Description

15:0

0x0

CLASSA_ACCUM_THRESH_SHADOWED

Once the accumulation value register is equal to the threshold escalation will be triggered on the next alert occurrence within this class A begins. Note that this register can not be modified if CLASSA_REGWEN is false.

alert_handler.CLASSA_TIMEOUT_CYC_SHADOWED @ 0x4b0

Interrupt timeout in cycles.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSA_TIMEOUT_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSA_TIMEOUT_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSA_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class A. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSA_REGWEN is false.

alert_handler.CLASSA_CRASHDUMP_TRIGGER_SHADOWED @ 0x4b4

Crashdump trigger configuration for Class A.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASSA_CRASHDUMP_TRIGGER_SHADOWED

Bits Type Reset Name Description

1:0

0x0

CLASSA_CRASHDUMP_TRIGGER_SHADOWED

Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation timer states. It is recommended to capture the crashdump upon entering the first escalation phase that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order to prevent spurious alert events from masking the original alert causes. Note that this register can not be modified if CLASSA_REGWEN is false.

alert_handler.CLASSA_PHASE0_CYC_SHADOWED @ 0x4b8

Duration of escalation phase 0 for Class A.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSA_PHASE0_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSA_PHASE0_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSA_PHASE0_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSA_REGWEN is false.

alert_handler.CLASSA_PHASE1_CYC_SHADOWED @ 0x4bc

Duration of escalation phase 1 for Class A.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSA_PHASE1_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSA_PHASE1_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSA_PHASE1_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSA_REGWEN is false.

alert_handler.CLASSA_PHASE2_CYC_SHADOWED @ 0x4c0

Duration of escalation phase 2 for Class A.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSA_PHASE2_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSA_PHASE2_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSA_PHASE2_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSA_REGWEN is false.

alert_handler.CLASSA_PHASE3_CYC_SHADOWED @ 0x4c4

Duration of escalation phase 3 for Class A.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSA_PHASE3_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSA_PHASE3_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSA_PHASE3_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSA_REGWEN is false.

alert_handler.CLASSA_ESC_CNT @ 0x4c8

Escalation counter in cycles for Class A.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSA_ESC_CNT...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSA_ESC_CNT

Bits Type Reset Name Description

31:0

CLASSA_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSA_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSA_CLR_SHADOWED. Note however that has no effect if CLASSA_REGWEN is set to false (either by SW or by HW via the CLASSA_CTRL_SHADOWED.LOCK feature).

alert_handler.CLASSA_STATE @ 0x4cc

Current escalation state of Class A. See also CLASSA_ESC_CNT.

Reset default = 0x0, mask 0x7

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CLASSA_STATE

Bits Type Reset Name Description

2:0

CLASSA_STATE

0x0	Idle	No timeout or escalation triggered.
0x1	Timeout	IRQ timeout counter is active.
0x2	FsmError	Terminal error state if FSM has been glitched.
0x3	Terminal	Terminal state after escalation protocol.
0x4	Phase0	Escalation Phase0 is active.
0x5	Phase1	Escalation Phase1 is active.
0x6	Phase2	Escalation Phase2 is active.
0x7	Phase3	Escalation Phase3 is active.

alert_handler.CLASSB_REGWEN @ 0x4d0

Lock bit for Class B configuration.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															CLASSB_REGWEN

Bits

Type

Reset

Name

Description

rw0c

0x1

CLASSB_REGWEN

Class configuration enable bit. If this is cleared to 0, the corresponding class configuration registers cannot be written anymore.

alert_handler.CLASSB_CTRL_SHADOWED @ 0x4d4

Escalation control register for alert Class B. Can not be modified if CLASSB_REGWEN is false.

Reset default = 0x393c, mask 0x3fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		MAP_E3		MAP_E2		MAP_E1		MAP_E0		EN_E3	EN_E2	EN_E1	EN_E0	LOCK	EN

Bits Type Reset Name Description

0x0

Enable escalation mechanisms (accumulation and interrupt timeout) for Class B. Note that interrupts can fire regardless of whether the escalation mechanisms are enabled for this class or not.

0x0

LOCK

Enable automatic locking of escalation counter for class B. If true, there is no way to stop the escalation protocol for class B once it has been triggered.

0x1

EN_E0

Enable escalation signal 0 for Class B

0x1

EN_E1

Enable escalation signal 1 for Class B

0x1

EN_E2

Enable escalation signal 2 for Class B

0x1

EN_E3

Enable escalation signal 3 for Class B

7:6

0x0

MAP_E0

Determines in which escalation phase escalation signal 0 shall be asserted.

9:8

0x1

MAP_E1

Determines in which escalation phase escalation signal 1 shall be asserted.

11:10

0x2

MAP_E2

Determines in which escalation phase escalation signal 2 shall be asserted.

13:12

0x3

MAP_E3

Determines in which escalation phase escalation signal 3 shall be asserted.

alert_handler.CLASSB_CLR_REGWEN @ 0x4d8

Clear enable for escalation protocol of Class B alerts.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															CLASSB_CLR_REGWEN

Bits Type Reset Name Description

rw0c

0x1

CLASSB_CLR_REGWEN

Register defaults to true, can only be cleared. This register is set to false by the hardware if the escalation protocol has been triggered and the bit CLASSB_CTRL_SHADOWED.LOCK is true.

alert_handler.CLASSB_CLR_SHADOWED @ 0x4dc

Clear for escalation protocol of Class B.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															CLASSB_CLR_SHADOWED

Bits Type Reset Name Description

0x0

CLASSB_CLR_SHADOWED

Writing 1 to this register clears the accumulator and aborts escalation (if it has been triggered). This clear is disabled if CLASSB_CLR_REGWEN is false.

alert_handler.CLASSB_ACCUM_CNT @ 0x4e0

Current accumulation value for alert Class B. Software can clear this register with a write to CLASSB_CLR_SHADOWED register unless CLASSB_CLR_REGWEN is false.

Reset default = 0x0, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLASSB_ACCUM_CNT

Bits Type Reset Name Description

15:0 ro x CLASSB_ACCUM_CNT

alert_handler.CLASSB_ACCUM_THRESH_SHADOWED @ 0x4e4

Accumulation threshold value for alert Class B.

Reset default = 0x0, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLASSB_ACCUM_THRESH_SHADOWED

Bits Type Reset Name Description

15:0

0x0

CLASSB_ACCUM_THRESH_SHADOWED

Once the accumulation value register is equal to the threshold escalation will be triggered on the next alert occurrence within this class B begins. Note that this register can not be modified if CLASSB_REGWEN is false.

alert_handler.CLASSB_TIMEOUT_CYC_SHADOWED @ 0x4e8

Interrupt timeout in cycles.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSB_TIMEOUT_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSB_TIMEOUT_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSB_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class B. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSB_REGWEN is false.

alert_handler.CLASSB_CRASHDUMP_TRIGGER_SHADOWED @ 0x4ec

Crashdump trigger configuration for Class B.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASSB_CRASHDUMP_TRIGGER_SHADOWED

Bits Type Reset Name Description

1:0

0x0

CLASSB_CRASHDUMP_TRIGGER_SHADOWED

alert_handler.CLASSB_PHASE0_CYC_SHADOWED @ 0x4f0

Duration of escalation phase 0 for Class B.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSB_PHASE0_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSB_PHASE0_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSB_PHASE0_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSB_REGWEN is false.

alert_handler.CLASSB_PHASE1_CYC_SHADOWED @ 0x4f4

Duration of escalation phase 1 for Class B.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSB_PHASE1_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSB_PHASE1_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSB_PHASE1_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSB_REGWEN is false.

alert_handler.CLASSB_PHASE2_CYC_SHADOWED @ 0x4f8

Duration of escalation phase 2 for Class B.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSB_PHASE2_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSB_PHASE2_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSB_PHASE2_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSB_REGWEN is false.

alert_handler.CLASSB_PHASE3_CYC_SHADOWED @ 0x4fc

Duration of escalation phase 3 for Class B.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSB_PHASE3_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSB_PHASE3_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSB_PHASE3_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSB_REGWEN is false.

alert_handler.CLASSB_ESC_CNT @ 0x500

Escalation counter in cycles for Class B.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSB_ESC_CNT...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSB_ESC_CNT

Bits Type Reset Name Description

31:0

CLASSB_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSB_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSB_CLR_SHADOWED. Note however that has no effect if CLASSB_REGWEN is set to false (either by SW or by HW via the CLASSB_CTRL_SHADOWED.LOCK feature).

alert_handler.CLASSB_STATE @ 0x504

Current escalation state of Class B. See also CLASSB_ESC_CNT.

Reset default = 0x0, mask 0x7

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CLASSB_STATE

Bits Type Reset Name Description

2:0

CLASSB_STATE

0x0	Idle	No timeout or escalation triggered.
0x1	Timeout	IRQ timeout counter is active.
0x2	FsmError	Terminal error state if FSM has been glitched.
0x3	Terminal	Terminal state after escalation protocol.
0x4	Phase0	Escalation Phase0 is active.
0x5	Phase1	Escalation Phase1 is active.
0x6	Phase2	Escalation Phase2 is active.
0x7	Phase3	Escalation Phase3 is active.

alert_handler.CLASSC_REGWEN @ 0x508

Lock bit for Class C configuration.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															CLASSC_REGWEN

Bits

Type

Reset

Name

Description

rw0c

0x1

CLASSC_REGWEN

Class configuration enable bit. If this is cleared to 0, the corresponding class configuration registers cannot be written anymore.

alert_handler.CLASSC_CTRL_SHADOWED @ 0x50c

Escalation control register for alert Class C. Can not be modified if CLASSC_REGWEN is false.

Reset default = 0x393c, mask 0x3fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		MAP_E3		MAP_E2		MAP_E1		MAP_E0		EN_E3	EN_E2	EN_E1	EN_E0	LOCK	EN

Bits Type Reset Name Description

0x0

Enable escalation mechanisms (accumulation and interrupt timeout) for Class C. Note that interrupts can fire regardless of whether the escalation mechanisms are enabled for this class or not.

0x0

LOCK

Enable automatic locking of escalation counter for class C. If true, there is no way to stop the escalation protocol for class C once it has been triggered.

0x1

EN_E0

Enable escalation signal 0 for Class C

0x1

EN_E1

Enable escalation signal 1 for Class C

0x1

EN_E2

Enable escalation signal 2 for Class C

0x1

EN_E3

Enable escalation signal 3 for Class C

7:6

0x0

MAP_E0

Determines in which escalation phase escalation signal 0 shall be asserted.

9:8

0x1

MAP_E1

Determines in which escalation phase escalation signal 1 shall be asserted.

11:10

0x2

MAP_E2

Determines in which escalation phase escalation signal 2 shall be asserted.

13:12

0x3

MAP_E3

Determines in which escalation phase escalation signal 3 shall be asserted.

alert_handler.CLASSC_CLR_REGWEN @ 0x510

Clear enable for escalation protocol of Class C alerts.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															CLASSC_CLR_REGWEN

Bits Type Reset Name Description

rw0c

0x1

CLASSC_CLR_REGWEN

Register defaults to true, can only be cleared. This register is set to false by the hardware if the escalation protocol has been triggered and the bit CLASSC_CTRL_SHADOWED.LOCK is true.

alert_handler.CLASSC_CLR_SHADOWED @ 0x514

Clear for escalation protocol of Class C.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															CLASSC_CLR_SHADOWED

Bits Type Reset Name Description

0x0

CLASSC_CLR_SHADOWED

Writing 1 to this register clears the accumulator and aborts escalation (if it has been triggered). This clear is disabled if CLASSC_CLR_REGWEN is false.

alert_handler.CLASSC_ACCUM_CNT @ 0x518

Current accumulation value for alert Class C. Software can clear this register with a write to CLASSC_CLR_SHADOWED register unless CLASSC_CLR_REGWEN is false.

Reset default = 0x0, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLASSC_ACCUM_CNT

Bits Type Reset Name Description

15:0 ro x CLASSC_ACCUM_CNT

alert_handler.CLASSC_ACCUM_THRESH_SHADOWED @ 0x51c

Accumulation threshold value for alert Class C.

Reset default = 0x0, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLASSC_ACCUM_THRESH_SHADOWED

Bits Type Reset Name Description

15:0

0x0

CLASSC_ACCUM_THRESH_SHADOWED

Once the accumulation value register is equal to the threshold escalation will be triggered on the next alert occurrence within this class C begins. Note that this register can not be modified if CLASSC_REGWEN is false.

alert_handler.CLASSC_TIMEOUT_CYC_SHADOWED @ 0x520

Interrupt timeout in cycles.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSC_TIMEOUT_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSC_TIMEOUT_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSC_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class C. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSC_REGWEN is false.

alert_handler.CLASSC_CRASHDUMP_TRIGGER_SHADOWED @ 0x524

Crashdump trigger configuration for Class C.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASSC_CRASHDUMP_TRIGGER_SHADOWED

Bits Type Reset Name Description

1:0

0x0

CLASSC_CRASHDUMP_TRIGGER_SHADOWED

alert_handler.CLASSC_PHASE0_CYC_SHADOWED @ 0x528

Duration of escalation phase 0 for Class C.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSC_PHASE0_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSC_PHASE0_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSC_PHASE0_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSC_REGWEN is false.

alert_handler.CLASSC_PHASE1_CYC_SHADOWED @ 0x52c

Duration of escalation phase 1 for Class C.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSC_PHASE1_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSC_PHASE1_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSC_PHASE1_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSC_REGWEN is false.

alert_handler.CLASSC_PHASE2_CYC_SHADOWED @ 0x530

Duration of escalation phase 2 for Class C.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSC_PHASE2_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSC_PHASE2_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSC_PHASE2_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSC_REGWEN is false.

alert_handler.CLASSC_PHASE3_CYC_SHADOWED @ 0x534

Duration of escalation phase 3 for Class C.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSC_PHASE3_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSC_PHASE3_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSC_PHASE3_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSC_REGWEN is false.

alert_handler.CLASSC_ESC_CNT @ 0x538

Escalation counter in cycles for Class C.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSC_ESC_CNT...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSC_ESC_CNT

Bits Type Reset Name Description

31:0

CLASSC_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSC_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSC_CLR_SHADOWED. Note however that has no effect if CLASSC_REGWEN is set to false (either by SW or by HW via the CLASSC_CTRL_SHADOWED.LOCK feature).

alert_handler.CLASSC_STATE @ 0x53c

Current escalation state of Class C. See also CLASSC_ESC_CNT.

Reset default = 0x0, mask 0x7

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CLASSC_STATE

Bits Type Reset Name Description

2:0

CLASSC_STATE

0x0	Idle	No timeout or escalation triggered.
0x1	Timeout	IRQ timeout counter is active.
0x2	FsmError	Terminal error state if FSM has been glitched.
0x3	Terminal	Terminal state after escalation protocol.
0x4	Phase0	Escalation Phase0 is active.
0x5	Phase1	Escalation Phase1 is active.
0x6	Phase2	Escalation Phase2 is active.
0x7	Phase3	Escalation Phase3 is active.

alert_handler.CLASSD_REGWEN @ 0x540

Lock bit for Class D configuration.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															CLASSD_REGWEN

Bits

Type

Reset

Name

Description

rw0c

0x1

CLASSD_REGWEN

Class configuration enable bit. If this is cleared to 0, the corresponding class configuration registers cannot be written anymore.

alert_handler.CLASSD_CTRL_SHADOWED @ 0x544

Escalation control register for alert Class D. Can not be modified if CLASSD_REGWEN is false.

Reset default = 0x393c, mask 0x3fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		MAP_E3		MAP_E2		MAP_E1		MAP_E0		EN_E3	EN_E2	EN_E1	EN_E0	LOCK	EN

Bits Type Reset Name Description

0x0

Enable escalation mechanisms (accumulation and interrupt timeout) for Class D. Note that interrupts can fire regardless of whether the escalation mechanisms are enabled for this class or not.

0x0

LOCK

Enable automatic locking of escalation counter for class D. If true, there is no way to stop the escalation protocol for class D once it has been triggered.

0x1

EN_E0

Enable escalation signal 0 for Class D

0x1

EN_E1

Enable escalation signal 1 for Class D

0x1

EN_E2

Enable escalation signal 2 for Class D

0x1

EN_E3

Enable escalation signal 3 for Class D

7:6

0x0

MAP_E0

Determines in which escalation phase escalation signal 0 shall be asserted.

9:8

0x1

MAP_E1

Determines in which escalation phase escalation signal 1 shall be asserted.

11:10

0x2

MAP_E2

Determines in which escalation phase escalation signal 2 shall be asserted.

13:12

0x3

MAP_E3

Determines in which escalation phase escalation signal 3 shall be asserted.

alert_handler.CLASSD_CLR_REGWEN @ 0x548

Clear enable for escalation protocol of Class D alerts.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															CLASSD_CLR_REGWEN

Bits Type Reset Name Description

rw0c

0x1

CLASSD_CLR_REGWEN

Register defaults to true, can only be cleared. This register is set to false by the hardware if the escalation protocol has been triggered and the bit CLASSD_CTRL_SHADOWED.LOCK is true.

alert_handler.CLASSD_CLR_SHADOWED @ 0x54c

Clear for escalation protocol of Class D.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															CLASSD_CLR_SHADOWED

Bits Type Reset Name Description

0x0

CLASSD_CLR_SHADOWED

Writing 1 to this register clears the accumulator and aborts escalation (if it has been triggered). This clear is disabled if CLASSD_CLR_REGWEN is false.

alert_handler.CLASSD_ACCUM_CNT @ 0x550

Current accumulation value for alert Class D. Software can clear this register with a write to CLASSD_CLR_SHADOWED register unless CLASSD_CLR_REGWEN is false.

Reset default = 0x0, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLASSD_ACCUM_CNT

Bits Type Reset Name Description

15:0 ro x CLASSD_ACCUM_CNT

alert_handler.CLASSD_ACCUM_THRESH_SHADOWED @ 0x554

Accumulation threshold value for alert Class D.

Reset default = 0x0, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLASSD_ACCUM_THRESH_SHADOWED

Bits Type Reset Name Description

15:0

0x0

CLASSD_ACCUM_THRESH_SHADOWED

Once the accumulation value register is equal to the threshold escalation will be triggered on the next alert occurrence within this class D begins. Note that this register can not be modified if CLASSD_REGWEN is false.

alert_handler.CLASSD_TIMEOUT_CYC_SHADOWED @ 0x558

Interrupt timeout in cycles.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSD_TIMEOUT_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSD_TIMEOUT_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSD_TIMEOUT_CYC_SHADOWED

If the interrupt corresponding to this class is not handled within the specified amount of cycles, escalation will be triggered. Set to a positive value to enable the interrupt timeout for Class D. The timeout is set to zero by default, which disables this feature. Note that this register can not be modified if CLASSD_REGWEN is false.

alert_handler.CLASSD_CRASHDUMP_TRIGGER_SHADOWED @ 0x55c

Crashdump trigger configuration for Class D.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLASSD_CRASHDUMP_TRIGGER_SHADOWED

Bits Type Reset Name Description

1:0

0x0

CLASSD_CRASHDUMP_TRIGGER_SHADOWED

alert_handler.CLASSD_PHASE0_CYC_SHADOWED @ 0x560

Duration of escalation phase 0 for Class D.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSD_PHASE0_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSD_PHASE0_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSD_PHASE0_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSD_REGWEN is false.

alert_handler.CLASSD_PHASE1_CYC_SHADOWED @ 0x564

Duration of escalation phase 1 for Class D.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSD_PHASE1_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSD_PHASE1_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSD_PHASE1_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSD_REGWEN is false.

alert_handler.CLASSD_PHASE2_CYC_SHADOWED @ 0x568

Duration of escalation phase 2 for Class D.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSD_PHASE2_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSD_PHASE2_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSD_PHASE2_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSD_REGWEN is false.

alert_handler.CLASSD_PHASE3_CYC_SHADOWED @ 0x56c

Duration of escalation phase 3 for Class D.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSD_PHASE3_CYC_SHADOWED...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSD_PHASE3_CYC_SHADOWED

Bits Type Reset Name Description

31:0

0x0

CLASSD_PHASE3_CYC_SHADOWED

Escalation phase duration in cycles. Note that this register can not be modified if CLASSD_REGWEN is false.

alert_handler.CLASSD_ESC_CNT @ 0x570

Escalation counter in cycles for Class D.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLASSD_ESC_CNT...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLASSD_ESC_CNT

Bits Type Reset Name Description

31:0

CLASSD_ESC_CNT

Returns the current timeout or escalation count (depending on CLASSD_STATE). This register can not be directly cleared. However, SW can indirectly clear as follows.

If the class is in the Timeout state, the timeout can be aborted by clearing the corresponding interrupt bit.

If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be aborted by writing to CLASSD_CLR_SHADOWED. Note however that has no effect if CLASSD_REGWEN is set to false (either by SW or by HW via the CLASSD_CTRL_SHADOWED.LOCK feature).

alert_handler.CLASSD_STATE @ 0x574

Current escalation state of Class D. See also CLASSD_ESC_CNT.

Reset default = 0x0, mask 0x7

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CLASSD_STATE

Bits Type Reset Name Description

2:0

CLASSD_STATE

0x0	Idle	No timeout or escalation triggered.
0x1	Timeout	IRQ timeout counter is active.
0x2	FsmError	Terminal error state if FSM has been glitched.
0x3	Terminal	Terminal state after escalation protocol.
0x4	Phase0	Escalation Phase0 is active.
0x5	Phase1	Escalation Phase1 is active.
0x6	Phase2	Escalation Phase2 is active.
0x7	Phase3	Escalation Phase3 is active.

OpenTitan Documentation

Hardware Interfaces and Registers

Interfaces

Registers