Testplan

Testpoints

Stage V1 Testpoints

smoke

Test: keymgr_dpe_smoke

Smoke test exercising the major datapath within keymgr_dpe. Tests operations (advance, gen-sw-out, gen-hw-out) at every stage.

Stimulus:

  • Randomly select a destination slot x and issue an advance call (which should latch the root key into slot x).
  • At each stage, issue gen-hw-out and gen-sw-out using the previously loaded key slot.
  • At each stage, advance to the next stage by randomly picking a new destination slot y, and advancing to it from slot x (x = y is also allowed).
  • Use fixed values for max_key_version = 0 and policy.allow_child = 1 during advance calls.
  • Use default/fixed values for HW/SW inputs. Use key_version = 0 during key generation.
  • During some erase and disable operations, hold the decoy data of the KMAC interface at all zeros or all ones.

Checks:

  • Check the STATUS register after each operation.
  • Check that the op_done interrupt is triggered when an operation completes.
  • Check that err and alert recov_operation_err are triggered after an invalid operation.
  • Check that the valid bit is set to 1 in the destination slot.
  • Check that the policy field is correctly updated from the SLOT_POLICY CSR.
  • Check KMAC key, KMAC data, and SW output data for correctness.
  • Check that constant decoy data does not raise the KMAC_OUT fault.

random_sw_input

No Tests Implemented

Extends the smoke test by randomizing all SW input data.

  • Fully randomize SW inputs: rom_ext_desc_, software_binding_, salt_, max__key_ver, *_key_ver_regwen.
  • Randomize key_version to any value less than max_*_key_ver, to avoid triggering the invalid_kmac_input error.
  • Fully randomize HW inputs from flash, OTP, and life cycle.
  • Randomize *sw_binding_regwen. Verify that this gates *_sw_binding writes and that it is cleared after a successful advance operation.

Stimulus and checks are the same as smoke.

csr_hw_reset

Test: keymgr_dpe_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_rw

Test: keymgr_dpe_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_bit_bash

Test: keymgr_dpe_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_aliasing

Test: keymgr_dpe_csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_mem_rw_with_rand_reset

Test: keymgr_dpe_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.

regwen_csr_and_corresponding_lockable_csr

Tests:

  • keymgr_dpe_csr_rw
  • keymgr_dpe_csr_aliasing

Verify regwen CSR and its corresponding lockable CSRs.

  • Randomly access all CSRs
  • Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

  • If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
  • If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

Stage V2 Testpoints

cfgen_during_op

No Tests Implemented

cfg_regwen is a read-only register that gates a number of write accesses to other registers, which is not tested in common CSR tests. When a operation is started, register protected by this EN (e.g. SW Binding registers) are not longer modifiable until the operation completes.

Stimulus and checks: Verify that commands and register accesses gated by cfg_regwen are ignored while an operation is in progress.

sideload

No Tests Implemented

keymgr_dpe exposes hardware sideload interfaces that deliver keys to KMAC, AES, and OTBN. After each exposure clear the key from the sideload interface.

Stimulus:

  • Generate a keymgr_dpe output to each HW sideload interface, exercising all three.
  • After each key generation clear the corresponding interface by writing into the SIDELOAD_CLEAR register.
  • Reset the clear mechanism by writing 0 into the SIDELOAD_CLEAR register.

Checks:

  • Verify that the sideload interfaces deliver the requested keys.
  • Verify the clear operation on the interface port.

invalid_hw_slot_overwrite

No Tests Implemented

Stimulus:

  • Attempt to derive a DPE context into an already-occupied hardware slot

Checks:

  • Verify ‘INVALID_OP’ is raised.
  • Verify the content of the hardware slot is unchanged.

invalid_parent_policy

No Tests Implemented

The parent policy of a DPE context determines whether a derived child context must overwrite the parent hardware slot (retain_parent == 0) or must target a different, empty slot (retain_parent == 1).

Stimulus:

  • Derive a DPE context with retain_parent == 1, then attempt to overwrite the parent slot.
  • Derive a DPE context with retain_parent == 0, then attempt to advance the child into a different (empty) slot.

Checks:

  • Verify that ‘INVALID_OP’ is raised in both cases.
  • Verify the content of the source hardware slot is unchanged.
  • Verify the content of the destination hardware slot is unchanged.
  • Verify the empty slot remains empty and invalid.

invalid_child_policy

No Tests Implemented

Verify that deriving a child context is rejected when the allow_child policy bit is false.

Stimulus:

  • Derive a DPE context with allow_child == 0.
  • Attempt to derive a child context from it.

Checks:

  • Verify that ‘INVALID_OP’ is raised.
  • Verify the content of the hardware slot is unchanged.

erase_dpe_context

No Tests Implemented

Erase a DPE context from a hardware slot using a software command.

Stimulus:

  • Derive a DPE context into a slot, then issue an erase command.

Checks:

  • Verify that the destination slot is no longer marked as valid.
  • Verify the stored key is overwritten with randomness.

erase_empty_dpe_context

No Tests Implemented

Attempt to erase a DPE context from a hardware slot that is not occupied.

Stimulus: Issue an erase command targeting an empty slot.

Checks:

  • Verify that ‘INVALID_OP’ is raised.
  • Verify the content of the hardware slot is unchanged.

load_uds_command

No Tests Implemented

Reload the UDS into an empty hardware slot after keymgr_dpe has already reached the Available state.

Stimulus:

  • Bring keymgr_dpe out of the Reset state and into the Available state by issuing a single advance call.
  • Issue the corresponding software command to load the UDS a second time.

Checks:

  • Verify that the second load successfully populates the hardware slot with the UDS.

load_uds_command_without_default_policy

No Tests Implemented

Reload the UDS into an empty hardware slot after keymgr_dpe has reached the Available state, with SLOT_POLICY programmed to values that differ from the RTL-defined defaults.

Stimulus:

  • Bring keymgr_dpe out of the Reset state and into the Available state by issuing a single advance call.
  • Issue the corresponding software command to load the UDS a second time.

Checks:

  • Verify that the resulting slot policies match the RTL-defined defaults from the keymgr_dpe package, not the values programmed via the SLOT_POLICY register.
  • Verify that max_key_version is correctly copied from the MAX_KEY_VER_SHADOWED register.

load_uds_command_in_occupied_slot

No Tests Implemented

Attempt to reload the UDS into an already-occupied hardware slot.

Stimulus:

  • Bring keymgr_dpe out of the Reset state and into the Available state by issuing a single advance call.
  • Attempt to load the UDS into the exact same hardware slot.

Checks:

  • Verify that ‘INVALID_OP’ is raised.
  • Verify the content of the hardware slot is unchanged.

lock_loading_uds_command

No Tests Implemented

Attempt to load the UDS when the load_key_lock hardware register is set.

Stimulus:

  • Bring keymgr_dpe out of the Reset state and into the Available state by issuing a single advance call.
  • Set the load_key_lock register, then attempt to issue the load UDS command.

Checks:

  • Verify that ‘INVALID_OP’ is raised.
  • Verify the content of the hardware slot is unchanged.

invalid_uds

No Tests Implemented

Verify keymgr_dpe behavior when the valid signal of the uds is false.

Stimulus:

  • Drive the valid signal for the uds low
  • Bring keymgr_dpe out of the Reset state and into the Available state by issuing a single advance call.

Checks:

  • Verify the keymgr_dpe enters the Invalid state.
  • Verify the corresponding INVALID_ROOT_KEY entry inside the debug register is set.

use_excl_sw_binding_option

No Tests Implemented

When deriving from the initial DPE slot, HW binding values from the life cycle state are normally included in the KMAC message for the first, second, and third advance calls. The excl_sw_binding flag suppresses these hw binding values.

Stimulus:

  • Bring keymgr_dpe out of the Reset state and into the Available state by issuing a single advance call.
  • Perform three advance operations with the excl_sw_binding flag set.

Checks:

  • Verify that the corresponding hw binding values on the KMAC interface are driven to zero when the flag is set, and carry their expected non-zero values when it is cleared.
  • Generate a SW readable key from the derived DPE context and compare it against a known golden model.

direct_to_disabled_state

No Tests Implemented

Issue the disable command from each reachable state and verify that keymgr_dpe correctly enters the StDisabled state.

check_lc_reset_state

No Tests Implemented

The life cycle controller can deactivate / activate the keymgr_dpe.

Stimulus:

  • Deactivate the keymgr_dpe by the LC controller
  • Issue a single advance call
  • Activate the keymgr_dpe by the LC controller
  • Issue a single advance call

Checks:

  • Verify that ‘INVALID_OP’ is raised by the first advance call.
  • Verify the keymgr_dpe transition into the Available state with the second advance call.

check_lc_available_state

No Tests Implemented

The life cycle controller can deactivate the keymgr_dpe, causing it to wipe all secret key material immediately.

Stimulus:

  • Bring keymgr_dpe out of the Reset state and into the Available state by issuing a single advance call.
  • Assert LC deactivation

Checks:

  • Verify that all sideload ports are immediately wiped and that SW output is invalid after the operation completes.
  • Verify the keymgr_dpe transition into the Invalid state.

check_lc_disable_state

No Tests Implemented

The life cycle controller can deactivate the keymgr_dpe, causing it to wipe all secret key material immediately.

Stimulus:

  • Bring keymgr_dpe out of the Reset state and into the Available state by issuing a single advance call.
  • Issue a disable operation with the register interface
  • Assert LC deactivation

Checks:

  • Verify the keymgr_dpe transition into the Disabled state.
  • Verify that all sideload ports are immediately wiped and that SW output is invalid after the operation completes.
  • Verify the keymgr_dpe transition into the Invalid state.

kmac_error_response

No Tests Implemented

Verify keymgr_dpe behavior when an error response is received from KMAC after initiating a key derivation transaction.

Stimulus:

  • Assert the KMAC error signal while the KMAC output valid signal is high.
  • Alternatively, drive all-zeros or all-ones as the KMAC digest output to trigger the output validity check.

Checks:

  • Verify that KMAC_OP inside the fault_status is updated correctly.

invalid_sw_input

No Tests Implemented

Verify keymgr_dpe behavior when KEY_VERSION exceeds MAX_KEY_VER for the selected source slot.

Stimulus: Randomize KEY_VERSION and MAX_KEY_VER registers such that KEY_VERSION > MAX_KEY_VER.

Checks:

  • Verify that alert recov_operation_err is triggered and err_code is INVALID_KMAC_INPUT.
  • Verify the content of the destination hardware slot is unchanged.

invalid_hw_input

No Tests Implemented

Verify keymgr_dpe behavior when hardware-supplied inputs contain invalid data patterns (all zeros or all ones).

Stimulus:

  • Drive all-zeros or all-ones on any of the following inputs: flash seeds, otp_key, diversification ID, ROM digest, etc.

Checks:

  • Verify that alert recov_operation_err is triggered and err_code is INVALID_KMAC_INPUT.
  • Verify the content of the destination hardware slot is unchanged.
  • Verify the corresponding invalid entry inside the debug register is set.

sync_async_fault_cross

No Tests Implemented

Verify keymgr_dpe behavior when synchronous and asynchronous faults are triggered in combination.

Stimulus: Create the following two direct tests:

  • A sync (transactional) fault occurs, followed by an async (non-transactional) fault.
  • An async (non-transactional) fault occurs, followed by a sync (transactional) fault.

Checks:

  • Check alert fatal_fault_err is triggered on the first fault.
  • Verify that fault_status register is updated correctly with both faults.

stress_all

No Tests Implemented

  • Combine the sequences above into a single test that runs them sequentially, excluding the CSR sequence and keymgr_dpe_cfg_regwen (which requires zero delays).
  • Randomly insert a hardware reset between sequences.

intr_test

Test: keymgr_dpe_intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly “turn on” interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.

alert_test

Test: keymgr_dpe_alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

  • Enable a random set of alert requests by writing random value to alert_test CSR.
  • Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
  • During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
  • Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
  • Repeat the above steps a bunch of times.

tl_d_oob_addr_access

Test: keymgr_dpe_tl_errors

Access out of bounds address and verify correctness of response / behavior

tl_d_illegal_access

Test: keymgr_dpe_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec

  • TL-UL protocol error cases
    • invalid opcode
    • some mask bits not set when opcode is PutFullData
    • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
    • address and size aren’t aligned, e.g. a_address = 0x01, a_size != 0
    • size is greater than 2
  • OpenTitan defined error cases
    • access unmapped address, expect d_error = 1
    • write a CSR with unaligned address, e.g. a_address[1:0] != 0
    • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • write a memory with a_mask != '1 when it doesn’t support partial accesses
    • read a WO (write-only) memory
    • write a RO (read-only) memory
    • write with instr_type = True

tl_d_outstanding_access

Tests:

  • keymgr_dpe_csr_hw_reset
  • keymgr_dpe_csr_rw
  • keymgr_dpe_csr_aliasing
  • keymgr_dpe_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

tl_d_partial_access

Tests:

  • keymgr_dpe_csr_hw_reset
  • keymgr_dpe_csr_rw
  • keymgr_dpe_csr_aliasing
  • keymgr_dpe_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Stage V2S Testpoints

sec_cm_additional_check

No Tests Implemented

Verify the behavior of keymgr_dpe when faults are injected into its security countermeasures.

Stimulus: Follow the stimulus described in prim_count_check, prim_one_hot_check, and prim_fsm_check.

Checks:

  • In addition to checking the alert and fault_status, issue an operation after fault injection and verify that op_status reports failure and the design enters StInvalid.

tl_intg_err

Tests:

  • keymgr_dpe_tl_intg_err
  • keymgr_dpe_sec_cm

Verify that the data integrity check violation generates an alert.

  • Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
  • Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs

shadow_reg_update_error

Test: keymgr_dpe_shadow_reg_errors

Verify shadowed registers’ update error.

  • Randomly pick a shadowed register in the DUT.
  • Write it twice with different values.
  • Verify that the update error alert is triggered and the register value remains unchanged.
  • Verify the update_error status register field is set to 1.
  • Repeat the above steps a bunch of times.

shadow_reg_read_clear_staged_value

Test: keymgr_dpe_shadow_reg_errors

Verify reading a shadowed register will clear its staged value.

  • Randomly pick a shadowed register in the DUT.
  • Write it once and read it back to clear the staged value.
  • Then write it twice with the same new value (but different from the previous step).
  • Read it back to verify the new value and ensure that the update error alert did not trigger.
  • Verify the update_error status register field remains the same value.
  • Repeat the above steps a bunch of times.

shadow_reg_storage_error

Test: keymgr_dpe_shadow_reg_errors

Verify shadowed registers’ storage error.

  • Randomly pick a shadowed register in the DUT.
  • Backdoor write to shadowed or committed flops to create a storage fatal alert.
  • Check if fatal alert continuously fires until reset.
  • Verify that all other frontdoor write attempts are blocked during the storage error.
  • Verify that storage_error status register field is set to 1.
  • Reset the DUT.
  • Read all CSRs to ensure the DUT is properly reset.
  • Repeat the above steps a bunch of times.

shadowed_reset_glitch

Test: keymgr_dpe_shadow_reg_errors

Verify toggle shadowed_rst_n pin can trigger storage error.

  • Randomly drive shadowed_rst_n pin to low or rst_n pin to low.
  • check if any registers have been written before the reset. If so check if storage error fatal alert is triggered.
  • Check status register.
  • Drive shadowed_rst_n pin or rst_n pin back to high.
  • If fatal alert is triggered, reset the DUT.
  • Read all CSRs to ensure the DUT is properly reset.
  • Repeat the above steps a bunch of times.

shadow_reg_update_error_with_csr_rw

Test: keymgr_dpe_shadow_reg_errors_with_csr_rw

Run shadow_reg_update_error sequence in parallel with csr_rw sequence.

  • Randomly select one of the above sequences.
  • Apply csr_rw sequence in parallel but disable the csr_access_abort to ensure all shadowed registers’ write/read to be executed without aborting.
  • Repeat the above steps a bunch of times.

prim_count_check

Test: keymgr_dpe_sec_cm

Verify that violating prim_count counter properties generate a fatal alert.

Stimulus:

  • At the falling edge (non-active edge), force the counter to a different value than expected.
  • Randomly force the counter back to a normal value to ensure the error is latched and won’t go away until reset.
  • Within the next few cycles, the violation of hardened counter property should generate a fatal alert.
  • Repeat for ALL prim_count instances in the DUT.

Checks:

  • Check that fatal alert is triggered.
  • Check that err_code/fault_status is updated correctly and preserved until reset.
  • Verify any operations that follow fail (as applicable).

prim_fsm_check

Test: keymgr_dpe_sec_cm

Verify that entering to an undefined state generates a fatal alert.

Stimulus:

  • Backdoor force the FSM to any of the undefined values.
  • Randomly force the FSM back to a defined state to ensure the error is latched and won’t go away until reset.
  • Within the next few cycles, the FSM landing in an invalid state should trigger a fatal alert.
  • Repeat for ALL prim_fsm instances in the DUT.

Checks:

  • Check that fatal alert is triggered.
  • Check that err_code/fault_status is updated correctly and preserved until reset.
  • Verify any operations that follow fail (as applicable).

sec_cm_bus_integrity

No Tests Implemented

Verify the countermeasure(s) BUS.INTEGRITY.

sec_cm_config_shadow

No Tests Implemented

Verify the countermeasure(s) CONFIG.SHADOW.

sec_cm_op_config_regwen

No Tests Implemented

Verify the countermeasure(s) OP.CONFIG.REGWEN.

sec_cm_reseed_config_regwen

No Tests Implemented

Verify the countermeasure(s) RESEED.CONFIG.REGWEN.

sec_cm_sw_binding_config_regwen

No Tests Implemented

Verify the countermeasure(s) SW_BINDING.CONFIG.REGWEN.

sec_cm_max_key_ver_config_regwen

No Tests Implemented

Verify the countermeasure(s) MAX_KEY_VER.CONFIG.REGWEN.

sec_cm_enforce_sw_binding_ctrl_consistency

No Tests Implemented

Verify the countermeasure(s) ENFORCE_SW_BINDING.CTRL.CONSISTENCY.

sec_cm_enforce_sw_binding_ctrl_mubi

No Tests Implemented

Verify the countermeasure(s) ENFORCE_SW_BINDING.CTRL.MUBI.

sec_cm_lc_ctrl_intersig_mubi

No Tests Implemented

Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI.

sec_cm_constants_consistency

No Tests Implemented

Verify the countermeasure(s) CONSTANTS.CONSISTENCY.

sec_cm_intersig_consistency

No Tests Implemented

Verify the countermeasure(s) INTERSIG.CONSISTENCY.

sec_cm_hw_key_sw_noaccess

No Tests Implemented

Verify the countermeasure(s) HW.KEY.SW_NOACCESS.

sec_cm_output_keys_ctrl_redun

No Tests Implemented

Verify the countermeasure(s) OUTPUT_KEYS.CTRL.REDUN.

sec_cm_ctrl_fsm_sparse

No Tests Implemented

Verify the countermeasure(s) CTRL.FSM.SPARSE.

sec_cm_data_fsm_sparse

No Tests Implemented

Verify the countermeasure(s) DATA.FSM.SPARSE.

sec_cm_ctrl_fsm_local_esc

No Tests Implemented

Verify the countermeasure(s) CTRL.FSM.LOCAL_ESC.

sec_cm_ctrl_fsm_consistency

No Tests Implemented

Verify the countermeasure(s) CTRL.FSM.CONSISTENCY.

sec_cm_ctrl_fsm_global_esc

No Tests Implemented

Verify the countermeasure(s) CTRL.FSM.GLOBAL_ESC.

sec_cm_ctrl_ctr_redun

No Tests Implemented

Verify the countermeasure(s) CTRL.CTR.REDUN.

sec_cm_kmac_if_fsm_sparse

No Tests Implemented

Verify the countermeasure(s) KMAC_IF.FSM.SPARSE.

sec_cm_kmac_if_ctr_redun

No Tests Implemented

Verify the countermeasure(s) KMAC_IF.CTR.REDUN.

sec_cm_kmac_if_cmd_ctrl_consistency

No Tests Implemented

Verify the countermeasure(s) KMAC_IF_CMD.CTRL.CONSISTENCY.

sec_cm_kmac_if_done_ctrl_consistency

No Tests Implemented

Verify the countermeasure(s) KMAC_IF_DONE.CTRL.CONSISTENCY.

sec_cm_reseed_ctr_redun

No Tests Implemented

Verify the countermeasure(s) RESEED.CTR.REDUN.

sec_cm_side_load_sel_ctrl_consistency

No Tests Implemented

Verify the countermeasure(s) SIDE_LOAD_SEL.CTRL.CONSISTENCY.

sec_cm_sideload_ctrl_fsm_sparse

No Tests Implemented

Verify the countermeasure(s) SIDELOAD_CTRL.FSM.SPARSE.

sec_cm_ctrl_key_integrity

No Tests Implemented

Verify the countermeasure(s) CTRL.KEY.INTEGRITY.

Stage V3 Testpoints

stress_all_with_rand_reset

Test: keymgr_dpe_stress_all_with_rand_reset

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Covergroups

err_code_cg

  • Cover all err_code values except invalid_shadow_update, which is tested in a common direct test.
  • Sampled when err_code is read.

fault_status_cg

  • Cover all fault_status bit values
  • Sampled when fault_status is read.

hw_invalid_input_cg

Cover all HW invalid input scenarios, including:

  • All ones/zeros on the OTP root key.
  • OTP root key valid is low.
  • All ones/zeros on the LC keymgr_dpe health state.
  • All ones/zeros on ROM digest.
  • ROM digest valid is low.
  • All ones/zeros on flash creator seeds.
  • All ones/zeros on flash owner seeds.

key_version_compare_cg

  • Cover all comparison outcomes (equal, less than, greater than) between key_version and the current max_key_version.
  • Crossed with the working state and operation type (gen-sw-out or gen-hw-out).

keymgr_dpe_sw_input_cg

  • Cover toggle of all bits across SW input registers.
  • SW inputs include: sw_binding, salt, key_version and max_key_ver*.
  • Cross with the corresponding regwen value, confirm writes are attempted while the regwen allows the write (unlocked) and while it blocks it (locked).

lc_disable_cg

  • Cover LC disable events occurring in each working state and during each operation type.
  • Sampled when LC disables keymgr_dpe.

regwen_val_when_new_value_written_cg

Cover each lockable reg field with these 2 cases:

  • When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
  • When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

reseed_interval_cg

  • Cover small RESEED_INTERVAL values so that the testbench can verify that EDN requests are issued at the correct frequency.
  • Also cover large values to ensure all register bits are toggled.

shadow_field_errs_cg

Cover all shadow register errors for each register field.

For all register fields within the shadowed register, this coverpoint covers the following errors:

  • Update error
  • Storage error

sideload_clear_cg

  • Cover all SIDELOAD_CLEAR values used after each operation type and in each working state.
  • Cross with every combination of sideload interface availability across the three interfaces.
  • Sampled when SIDELOAD_CLEAR is programmed after an operation.

state_and_op_cg

  • Cover all operations crossed with cdi_sel, dest_sel, and op_status (success or failure) across all working states.
  • Sampled once each operation completes.

sync_async_fault_cross_cg

  • Cover both orderings of a sync/async fault cross: sync fault occurring first, and async fault occurring first.
  • Sampled after fault_status is read in the cross-fault sequence.

tl_errors_cg

Cover the following error cases on TL-UL bus:

  • TL-UL protocol error cases.
  • OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.