Testplan

Testpoints

Stage V1 Testpoints

host_smoke

Test: i2c_host_smoke

Smoke test in which random (rx/tx) transactions are sent to the DUT and received asynchronously with scoreboard checks.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Enable DUT host
  • Clear and enable interrupt (if needed)
  • Program OVRD and FDATA registers
  • Randomize I2C timing in TIMING[0-4] registers and other parameters such as TL agent delays
  • Randomize address and data for read/write transactions sent to the agent by the DUT

Checking:

  • Check the timing behavior of START, STOP, ACK, NACK, and “repeated” START
  • Read and write transfer matching
  • Command complete interrupt (cmd_complete) raised

target_smoke

Test: i2c_target_smoke

Smoke test in which random (rx/tx) transactions are sent to the DUT and received asynchronously with scoreboard checks.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Enable DUT target
  • Clear/Enable interrupt (if needed)
  • Randomize I2C timing in TIMING 0-4 registers and other parameters such as TL agent delays
  • Generate random addresses which are programmed to the DUT (target) and used for transaction sent by the agent (host)

Checking:

  • Check the timing behavior of START, STOP, ACK, NACK, and “repeated” START
  • Read and write transfer matching

csr_hw_reset

Test: i2c_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_rw

Test: i2c_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_bit_bash

Test: i2c_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_aliasing

Test: i2c_csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_mem_rw_with_rand_reset

Test: i2c_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.

regwen_csr_and_corresponding_lockable_csr

Tests:

  • i2c_csr_rw
  • i2c_csr_aliasing

Verify regwen CSR and its corresponding lockable CSRs.

  • Randomly access all CSRs
  • Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

  • If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
  • If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

Stage V2 Testpoints

host_error_intr

Test: i2c_host_error_intr

Test error interrupts are asserted by the Host DUT due to interference and unstable signals on bus.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • In host transmit mode, device (target/host) forces SDA or SCL signal low within the clock pulse of host SCL that asserts sda_interference or scl_interference interrupts
  • In host receiving mode (data or ack bits), SDA signal is changed with the clock pulse of host SCL that asserts intr_sda_unstable interrupts
  • When error interrupt assertions are detected, dut, agent, and scoreboard will be reset on-the-fly then new transaction can be continue programming

Checking:

  • Ensure all intr_scl_interference, intr_sda_interference, and intr_sda_unstable interrupts are asserted and stay asserted until cleared
  • Ensure IP operation get back normal after on-the-fly reset finished

host_stress_all

Test: i2c_host_stress_all

Support vseq (context) switching with random reset in between.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Combine above sequences in one test to run sequentially except CSR sequence and i2c_host_rx_oversample_vseq (requires zero_delays)
  • Randomly add reset between each sequence

Checking:

  • Ensure transactions are transmitted/received correctly,
  • Ensure reset is handled correctly

host_perf

Test: i2c_host_perf

The Host DUT sends and receives transactions at max bandwidth.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Program TIMINGx registers based on I2C specification
  • Reduce access latency for all FIFOs
  • Issue long read/write back-to-back transactions
  • Read rx_fifo as soon as read data valid
  • Clear interrupt quickly

Checking:

  • Ensure transactions are transmitted/received correctly

host_override

Test: i2c_host_override

Test SCL/SDA override.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Program OVRD register

Checking:

  • Ensure scl_o, sda_o are overridden

host_fifo_watermark

Test: i2c_host_fifo_watermark

Test the watermark interrupt of fmt_fifo and rx_fifo.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Program random fmt_fifo and rx_fifo watermark level
  • Write data quickly to fmt_fifo and rx_fifo for triggering watermark interrupts

Checking:

  • Ensure the fmt_fifo and rx_fifo watermark interrupts are asserted (fmt_threshold and rx_threshold)
  • Ensure the fmt_fifo and rx_fifo watermark interrupts stay asserted until cleared
  • Ensure receving correct number of fmt_fifo and rx_fifo watermark interrupts

host_fifo_overflow

Test: i2c_host_fifo_overflow

Test the overflow interrupt for fmt_fifo and rx_fifo.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • DUT keeps sending a number of format byte higher than the size of fmt_fifo and rx_fifo depth

Checking:

  • Ensure excess format bytes are dropped
  • Ensure fmt_overflow and rx_overflow interrupt are asserted

host_fifo_reset

Tests:

  • i2c_host_fifo_reset_fmt
  • i2c_host_fifo_reset_rx
  • i2c_host_fifo_fmt_empty

Test fmt_fifo and rx_fifo reset.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Fill up the fmt_fifo with data to be sent out
  • Reset the FIFO randomly after a number of bytes shows up on fmt_fifo

Checking:

  • Ensure the remaining entries are not show up after fmt_fifo is reset

host_fifo_full

Test: i2c_host_fifo_full

Test fmt_fifo and rx_fifo in full states.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Send enough read and write requests to fmt_fifo
  • Hold reading data from rx_fifo until FIFO is full

Checking:

  • Check FIFO full states by reading status register

host_timeout

Test: i2c_host_stretch_timeout

Test stretch_timeout interrupts.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Set timeout enable bit of TIMEOUT_CTRL register
  • Program timeout values (higher than host SCL clock pulse) into TIMEOUT_CTRL register
  • Configure agent to pull down target (device) SCL after the bit 9 (ACK) is transmitted

Checking:

  • Ensure stretch_timeout is asserted and a correct number is received

host_rx_oversample

Test: i2c_host_rx_oversample

Host mode: test oversampling on received channel.

Stimulus:

  • Use input clock to sample the target SDA (sample with baud rate equal to 1)
  • Drive scl_rx using input clock

Checking:

  • Read rx data oversampled value and ensure it is same as driven value

i2c_host_mode_toggle

Test: i2c_host_mode_toggle

Host mode: disable host mode during host mode sequence

Stimulus:

  • Host sends an address and data but receives NACK response since agent is reset before transaction is complete and host mode is disabled Checking:
  • Check if DUT goes to Idle state after Host mode is disabled
  • Check that transactions process normally after recovery by running a smoketest vseq.
  • Interrupt nak is raised

target_error_intr

Test: i2c_target_unexp_stop

Test unexp_stop interrupt is asserted by the Target DUT,

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Host agent send STOP after ACK

Checking:

  • Ensure all acq_stop is asserted and stay asserted until cleared
  • Ensure IP operation get back normal after on-the-fly reset finished

target_glitch

Test: i2c_target_glitch

Test I2C FSM state transitions in target mode of operation.

Stimulus:

  • Configure DUT/Agent in Target/Host mode respectively
  • Program timing parameters
  • Assert start_det and stop_det variables in i2c_fsm.sv to trigger transition to AcquireStart and Idle states Checking:
  • Ensure DUT captures ACQ FIFO data as expected
  • After every glitch, issue a simple transaction to check if DUT is behaving as expected

target_stress_all

Test: i2c_target_stress_all

Support vseq (context) switching with random reset in between.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Combine above sequences in one test to run sequentiall except CSR sequence
  • Randomly add reset between each sequence

Checking:

  • Ensure transactions are transmitted/received correctly
  • Ensure reset is handled correctly

target_perf

Test: i2c_target_perf

The Host Agent sends and receives transactions at max bandwidth.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Reduce access latency for all FIFOs
  • Issue long read/write back-to-back transactions
  • Make all FIFOs accessible without any delay
  • Clear interrupt quickly

Checking:

  • Ensure transactions are transmitted/received correctly

target_fifo_overflow

Test: i2c_target_tx_ovf

Test the overflow interrupt for tx_fifo overflow.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Agent keeps sending a number of format byte higher than the size of tx_fifo Checking:
  • Ensure excess format bytes are dropped
  • Ensure tx_overflow interrupt are asserted

target_fifo_empty

Tests:

  • i2c_target_stress_rd
  • i2c_target_intr_smoke

Test tx_empty and tx_nonempty interrupt.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Agent sends transaction to the DUT

Checking:

  • During read transaction, ensure tx_empty interrupt is asserted when no data left in tx_fifo otherwise tx_empty interrupt must be de-asserted

target_fifo_reset

Tests:

  • i2c_target_fifo_reset_acq
  • i2c_target_fifo_reset_tx

Test tx_fifo and acq_fifo reset.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Run read write mixed traffic
  • Assert reset any period between stop and the next start

Checking:

  • Ensure the remaining entries are not show up after each fifio is reset

target_fifo_full

Tests:

  • i2c_target_stress_wr
  • i2c_target_stress_rd
  • i2c_target_intr_stress_wr

Test acq_fifo and tx_fifo in full states.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Send enough read and write requests to acq_fifo
  • Slow down acq FIFO read process to trigger acq_full interrupt

Checking:

  • Check FIFO full states by reading status register
  • Whether acq_full interrupt raised

target_timeout

Test: i2c_target_timeout

Test host_timeout interrupts.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Set timeout enable bit of HOST_TIMEOUT_CTRL register
  • Agent stops sending clock during an ongoing transaction

Checking:

  • Ensure host_timeout is asserted and a correct number is received

target_clock_stretch

Test: i2c_target_stretch

Test clock stretch feature of DUT Target mode. For the write and address transaction, when acq_fifo is full, DUT starts to stretch clock. For the read transaction, when dut receives read command, the tx_fifo is empty, DUT starts to stretch clock. Using read / write mixed traffic, trigger stretch condition by slowing down acq / tx FIFO process.

Checking: Ensure all read /write data received correct on the other side without dropping any data.

bad_address

Test: i2c_target_bad_addr

Test sends transactions with a randomized address including two legal (programmed) addresses. Run this test with dut target mode.

Checking: All transactions with illegal addresses should be dropped silently and should not disturb transactions with legal address

target_mode_glitch

Test: i2c_target_hrst

Test handling of RStart ot Stop glitches in Target mode

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Issue a new request(RStart) to DUT during an active transfer
  • Stop current request(Stop) to DUT during an active transfer
  • Continue issuing requests to check if DUT FSM handles the transaction correctly

Checking: Ensure all transactions including glitches are observed in i2c.ACQDATA FIFO

alert_test

Test: i2c_alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

  • Enable a random set of alert requests by writing random value to alert_test CSR.
  • Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
  • During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
  • Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
  • Repeat the above steps a bunch of times.

intr_test

Test: i2c_intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly “turn on” interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.

tl_d_oob_addr_access

Test: i2c_tl_errors

Access out of bounds address and verify correctness of response / behavior

tl_d_illegal_access

Test: i2c_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec

  • TL-UL protocol error cases
    • invalid opcode
    • some mask bits not set when opcode is PutFullData
    • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
    • address and size aren’t aligned, e.g. a_address = 0x01, a_size != 0
    • size is greater than 2
  • OpenTitan defined error cases
    • access unmapped address, expect d_error = 1 when devmode_i == 1
    • write a CSR with unaligned address, e.g. a_address[1:0] != 0
    • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • write a memory with a_mask != '1 when it doesn’t support partial accesses
    • read a WO (write-only) memory
    • write a RO (read-only) memory
    • write with instr_type = True

tl_d_outstanding_access

Tests:

  • i2c_csr_hw_reset
  • i2c_csr_rw
  • i2c_csr_aliasing
  • i2c_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

tl_d_partial_access

Tests:

  • i2c_csr_hw_reset
  • i2c_csr_rw
  • i2c_csr_aliasing
  • i2c_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Stage V2S Testpoints

tl_intg_err

Tests:

  • i2c_tl_intg_err
  • i2c_sec_cm

Verify that the data integrity check violation generates an alert.

  • Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
  • Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs

sec_cm_bus_integrity

Test: i2c_tl_intg_err

Verify the countermeasure(s) BUS.INTEGRITY.

Stage V3 Testpoints

host_stress_all_with_rand_reset

Test: i2c_host_stress_all_with_rand_reset

Support random reset in parallel with stress_all and tl_errors sequences.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Combine above sequences in one test to run sequentially except CSR sequence and i2c_host_rx_oversample_vseq (requires zero_delays)
  • Randomly add reset within the sequences then switch to another one

Checking:

  • Ensure transactions are transmitted/received correctly
  • Ensure reset is handled correctly

target_stress_all_with_rand_reset

Test: i2c_target_stress_all_with_rand_reset

Support random reset in parallel with stress_all and tl_errors sequences.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Combine above sequences in one test to run sequentially except CSR sequence
  • Randomly add reset within the sequences then switch to another one

Checking:

  • Ensure transactions are transmitted/received correctly
  • Ensure reset is handled correctly

target_loopback

Test: ``

Test loopback mode, which is enabled by i2c.CTRL.LLPBK.

Covergroups

i2c_acq_fifo_cg

Cover the values supported by ACQDATA

  • Write address byte
  • Read address byte
  • Data byte
  • ACK before STOP
  • NACK before STOP
  • RSTART with previous ACK for READ
  • RSTART with previous NACK for READ

i2c_b2b_txn_cg

Cover combination of back to back read and write transfers covered in test suite Instantiate a separate covergroup for host and target mode of operation

i2c_cmd_complete_cg

Cover cmd_complete interrupt Cross cmd_complete with Host mode Read and Write operation Cross cmd_complete with Target mode Read and Write operation

i2c_fifo_level_cg

Cover the trigger level for FMT_FIFO and RX_FIFO interupts

  • Cross fmt_threshold interrupt with FMT_FIFO trigger level
  • Cross rx_threshold interrupt with RX_FIFO trigger level Cover the FIFO levels in FIFO_STATUS

i2c_fifo_reset_cg

Cover the FIFO reset bits in FIFO_CTL register Cross fmt_threshold with FMTRST Cross rx_threshold with RXRST Cross fmt_overflow with FMTRST Cross rx_overflow with RXRST Cross acq_overflow with ACQRST Cross tx_overflow with TXRST

i2c_fmt_fifo_cg

Cover the values supported by FDATA register

  • Data byte (all flags set to zero)
  • Write address byte
  • Read address byte
  • Read a number of bytes from Target with NACK
  • Cover values ranging from 1-128 Bytes
  • Read number of bytes from Target with ACK
  • Cover values ranging from 1-128 Bytes
  • Stop byte
  • Stop after Start (invalid transmission)
  • Write address transmission with NAKOK
  • Data transmission with NAKOK
  • Stop data with NAKOK Cross bytes with NACK from Target
  • Cross data byte with NAKOK and NACK from Target
  • Cross address byte with NAKOK and NACK from Target
  • Cross data byte with NAKOK and NACK from Target

i2c_interrupts_cg

Cover all the interrupts raised during I2C operation in both host and target mode Cross interrupt with INTERRUPT_TEST register

i2c_operating_mode_cg

  • Cover the operating mode (Host/Target) of DUT
  • Cover the operating mode (Host/Target) of TB
  • Cross the operating modes of DUT and TB
  • Cover the SCL frequency
  • Cross the SCL frequency with operating mode of DUT

i2c_protocol_cov_cg

Cover protocol transitions supported by I2C with single host

  • Cross protocol transitions with mode of operation of DUT (Host or Target) Cover host mode and target mode enable bits Cover mistimed Start or Stop glitches in target mode Cover the number of bytes read from Target Cover the number of bytes written to Target
  • Cover number of bytes as buckets instead of covering every value of number of bytes
  • Cross the number of bytes read in Target and Host mode of DUT
  • Cross the number of bytes written in Target and Host mode of DUT

i2c_rd_wr_cg

Cover the address match feature of IP

  • Cross the address match with Host and Target mode of DUT Cover values in Read bytes
  • Cross with operating mode of I2C Cover values in Write bytes
  • Cross with operating mode of I2C

i2c_scl_sca_override_cg

Cover TX override enable bit TXOVRDEN Cover override value of SCL Cover override value of SDA Cover oversampled value of SCL Cover oversampled value of SDA Cross override value of SCL with override enable Cross override value of SDA with override enable

i2c_scl_stretch_cg

Cover SCL stretch in Host mode

  • Cover clock stretch after address byte Cover SCL stretch in Target mode Cover Target mode SCL stretch in the following scenario
  • Read command received in ACQ FIFo and more than one entry in ACQ FIFO

i2c_status_cg

Cover the fields in i2c.STATUS register

i2c_timing_parameters_cg

Cover different values of Timing parameters supported by I2C IP

regwen_val_when_new_value_written_cg

Cover each lockable reg field with these 2 cases:

  • When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
  • When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

tl_errors_cg

Cover the following error cases on TL-UL bus:

  • TL-UL protocol error cases.
  • OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.