Registers

Summary

INTR_STATE

Interrupt State Register

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0x3ffff

Fields

{"reg": [{"name": "pkt_received", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "pkt_sent", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "disconnected", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "host_lost", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "link_reset", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "link_suspend", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "link_resume", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "av_out_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_full", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "av_overflow", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "link_in_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_crc_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_pid_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_bitstuff_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "frame", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "powered", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "link_out_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "av_setup_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 14}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}

INTR_STATE . av_setup_empty

Raised when the Available SETUP Buffer FIFO is empty and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the Available SETUP Buffer FIFO must be provided with a free buffer before the interrupt can be cleared.

INTR_STATE . link_out_err

Raised if a packet to an OUT endpoint started to be received but was then dropped due to an error. This error is raised if the data toggle, token, packet and/or CRC are invalid, or if the appropriate Available OUT Buffer FIFO is empty and/or the Received Buffer FIFO is full when a packet should have been received.

INTR_STATE . powered

Raised if VBUS is applied.

INTR_STATE . frame

Raised when the USB frame number is updated with a valid SOF.

INTR_STATE . rx_bitstuff_err

Raised if an invalid bitstuffing was received.

INTR_STATE . rx_pid_err

Raised if an invalid Packet IDentifier (PID) was received.

INTR_STATE . rx_crc_err

Raised if a CRC error occurred on a received packet.

INTR_STATE . link_in_err

Raised if a packet to an IN endpoint started to be received but was then dropped due to an error. After transmitting the IN payload, the USB device expects a valid ACK handshake packet. This error is raised if either the packet or CRC is invalid, leading to a NAK instead, or if a different token was received.

INTR_STATE . av_overflow

Raised if a write was done to either the Available OUT Buffer FIFO or the Available SETUP Buffer FIFO when the FIFO was full.

INTR_STATE . rx_full

Raised when the RX FIFO is full and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the RX FIFO must have an entry removed before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert.

INTR_STATE . av_out_empty

Raised when the Available OUT Buffer FIFO is empty and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the Available OUT Buffer FIFO must be provided with a free buffer before the interrupt can be cleared.

INTR_STATE . link_resume

Raised when the link becomes active again after being suspended.

INTR_STATE . link_suspend

Raised if the line has signaled J for longer than 3ms and is therefore in suspend state.

INTR_STATE . link_reset

Raised if the link is at SE0 longer than 3 us indicating a link reset (host asserts for min 10 ms, device can react after 2.5 us).

INTR_STATE . host_lost

Raised if link is active but SOF was not received from host for 4.096 ms. The SOF should be every 1 ms.

INTR_STATE . disconnected

Raised if VBUS is lost, thus the link is disconnected.

INTR_STATE . pkt_sent

Raised if a packet was sent as part of an IN transaction. This interrupt is directly tied to whether a sent packet has not been acknowledged in the in_sent register. It should be cleared only after clearing all bits in the in_sent register.

INTR_STATE . pkt_received

Raised if a packet was received using an OUT or SETUP transaction. This interrupt is directly tied to whether the RX FIFO is empty, so it should be cleared only after handling the FIFO entry.

INTR_ENABLE

Interrupt Enable Register

• Offset: 0x4
• Reset default: 0x0
• Reset mask: 0x3ffff

Fields

{"reg": [{"name": "pkt_received", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pkt_sent", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "disconnected", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "host_lost", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "link_reset", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "link_suspend", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "link_resume", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "av_out_empty", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_full", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "av_overflow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "link_in_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_crc_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_pid_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_bitstuff_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "frame", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "powered", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "link_out_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "av_setup_empty", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 14}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}

INTR_TEST

Interrupt Test Register

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0x3ffff

Fields

{"reg": [{"name": "pkt_received", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "pkt_sent", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "disconnected", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "host_lost", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "link_reset", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "link_suspend", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "link_resume", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "av_out_empty", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_full", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "av_overflow", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "link_in_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_crc_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_pid_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_bitstuff_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "frame", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "powered", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "link_out_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "av_setup_empty", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 14}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}

ALERT_TEST

Alert Test Register

• Offset: 0xc
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

usbctrl

USB Control

• Offset: 0x10
• Reset default: 0x0
• Reset mask: 0x7f0003

Fields

{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "resume_link_active", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 14}, {"name": "device_address", "bits": 7, "attr": ["rw"], "rotate": -90}, {"bits": 9}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

ep_out_enable

Enable an endpoint to respond to transactions in the downstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.

• Offset: 0x14
• Reset default: 0x0
• Reset mask: 0xfff

Fields

{"reg": [{"name": "enable_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

ep_in_enable

Enable an endpoint to respond to transactions in the upstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.

• Offset: 0x18
• Reset default: 0x0
• Reset mask: 0xfff

Fields

{"reg": [{"name": "enable_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

usbstat

USB Status

• Offset: 0x1c
• Reset default: 0x80000000
• Reset mask: 0xcfffffff

Fields

{"reg": [{"name": "frame", "bits": 11, "attr": ["ro"], "rotate": 0}, {"name": "host_lost", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "link_state", "bits": 3, "attr": ["ro"], "rotate": -90}, {"name": "sense", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "av_out_depth", "bits": 4, "attr": ["ro"], "rotate": -90}, {"name": "av_setup_depth", "bits": 3, "attr": ["ro"], "rotate": -90}, {"name": "av_out_full", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_depth", "bits": 4, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "av_setup_full", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_empty", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}

usbstat . rx_empty

Received Buffer FIFO is empty.

usbstat . av_setup_full

Available SETUP Buffer FIFO is full.

usbstat . rx_depth

Number of buffers in the Received Buffer FIFO.

These buffers have packets that have been received and should be popped from the FIFO and processed.

usbstat . av_out_full

Available OUT Buffer FIFO is full.

usbstat . av_setup_depth

Number of buffers in the Available SETUP Buffer FIFO.

These buffers are available for receiving SETUP DATA packets.

usbstat . av_out_depth

Number of buffers in the Available OUT Buffer FIFO.

These buffers are available for receiving OUT DATA packets.

usbstat . sense

Reflects the state of the sense pin. 1 indicates that the host is providing VBUS. Note that this bit always shows the state of the actual pin and does not take account of the override control.

usbstat . link_state

State of USB link, decoded from line.

Other values are reserved.

usbstat . host_lost

Start of frame not received from host for 4.096 ms and the line is active.

usbstat . frame

Frame index received from host. On an active link, this will increment every milisecond.

avoutbuffer

Available OUT Buffer FIFO

• Offset: 0x20
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "buffer", "bits": 5, "attr": ["wo"], "rotate": 0}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

avsetupbuffer

Available SETUP Buffer FIFO

• Offset: 0x24
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "buffer", "bits": 5, "attr": ["wo"], "rotate": 0}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

rxfifo

Received Buffer FIFO

• Offset: 0x28
• Reset default: 0x0
• Reset mask: 0xf87f1f

Fields

{"reg": [{"name": "buffer", "bits": 5, "attr": ["ro"], "rotate": 0}, {"bits": 3}, {"name": "size", "bits": 7, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "setup", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ep", "bits": 4, "attr": ["ro"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

rxenable_setup

Receive SETUP transaction enable

• Offset: 0x2c
• Reset default: 0x0
• Reset mask: 0xfff

Fields

{"reg": [{"name": "setup_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}

rxenable_out

Receive OUT transaction enable

• Offset: 0x30
• Reset default: 0x0
• Reset mask: 0xfff

Fields

{"reg": [{"name": "out_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "out_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "out_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "out_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "out_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "out_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "out_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "out_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "out_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "out_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "out_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "out_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

rxenable_out . out_11

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_10

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_9

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_8

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_7

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_6

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_5

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_4

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_3

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_2

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_1

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_0

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

set_nak_out

Set NAK after OUT transactions

• Offset: 0x34
• Reset default: 0x0
• Reset mask: 0xfff

Fields

{"reg": [{"name": "enable_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "enable_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

in_sent

IN Transaction Sent

• Offset: 0x38
• Reset default: 0x0
• Reset mask: 0xfff

Fields

{"reg": [{"name": "sent_0", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sent_1", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sent_2", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sent_3", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sent_4", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sent_5", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sent_6", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sent_7", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sent_8", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sent_9", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sent_10", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sent_11", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}

out_stall

OUT Endpoint STALL control

• Offset: 0x3c
• Reset default: 0x0
• Reset mask: 0xfff

Fields

{"reg": [{"name": "endpoint_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

out_stall . endpoint_11

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_10

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_9

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_8

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_7

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_6

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_5

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_4

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_3

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_2

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_1

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_0

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall

IN Endpoint STALL control

• Offset: 0x40
• Reset default: 0x0
• Reset mask: 0xfff

Fields

{"reg": [{"name": "endpoint_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoint_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

in_stall . endpoint_11

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_10

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_9

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_8

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_7

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_6

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_5

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_4

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_3

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_2

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_1

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_0

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

configin

Configure IN Transaction

• Reset default: 0x0
• Reset mask: 0xe0007f1f

Instances

Fields

{"reg": [{"name": "buffer", "bits": 5, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "size", "bits": 7, "attr": ["rw"], "rotate": 0}, {"bits": 14}, {"name": "sending", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "pend", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rdy", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}

configin . rdy

This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data.

This bit will also be cleared if an enabled SETUP transaction is received on the endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit.

configin . pend

This bit indicates a pending transaction was canceled by the hardware.

The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected.

The bit remains set until cleared by being written with a 1.

configin . sending

This bit indicates that the buffer is in the process of being collected by the host. It becomes set upon the first attempt by the host to collect a buffer from this endpoint when the rdy bit was set.

It is cleared when the packet has been collected successfully or the pending transaction has been canceled by the hardware through detection of a link reset or receipt of a SETUP packet.

configin . size

The number of bytes to send from the buffer.

If this is 0 then a CRC only packet is sent.

If this is greater than 64 then 64 bytes are sent.

configin . buffer

The buffer ID containing the data to send when an IN transaction is received on the endpoint.

out_iso

OUT Endpoint isochronous setting

• Offset: 0x74
• Reset default: 0x0
• Reset mask: 0xfff

Fields

{"reg": [{"name": "iso_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

out_iso . iso_11

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_10

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_9

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_8

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_7

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_6

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_5

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_4

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_3

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_2

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_1

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_0

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso

IN Endpoint isochronous setting

• Offset: 0x78
• Reset default: 0x0
• Reset mask: 0xfff

Fields

{"reg": [{"name": "iso_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "iso_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

in_iso . iso_11

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_10

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_9

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_8

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_7

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_6

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_5

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_4

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_3

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_2

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_1

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_0

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_data_toggle

OUT Endpoints Data Toggles

• Offset: 0x7c
• Reset default: 0x0
• Reset mask: 0xfff0fff

Fields

{"reg": [{"name": "status", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}, {"name": "mask", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

in_data_toggle

IN Endpoints Data Toggles

• Offset: 0x80
• Reset default: 0x0
• Reset mask: 0xfff0fff

Fields

{"reg": [{"name": "status", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}, {"name": "mask", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

phy_pins_sense

USB PHY pins sense. This register can be used to read out the state of the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing.

• Offset: 0x84
• Reset default: 0x0
• Reset mask: 0x11f07

Fields

{"reg": [{"name": "rx_dp_i", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_dn_i", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_d_i", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 5}, {"name": "tx_dp_o", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "tx_dn_o", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "tx_d_o", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "tx_se0_o", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "tx_oe_o", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 3}, {"name": "pwr_sense", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 15}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

phy_pins_drive

USB PHY pins drive. This register can be used to control the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing.

• Offset: 0x88
• Reset default: 0x0
• Reset mask: 0x100ff

Fields

{"reg": [{"name": "dp_o", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "dn_o", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "d_o", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "se0_o", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "oe_o", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_enable_o", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "dp_pullup_en_o", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "dn_pullup_en_o", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 8}, {"name": "en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 15}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}

phy_config

USB PHY Configuration

• Offset: 0x8c
• Reset default: 0x4
• Reset mask: 0xe7

Fields

{"reg": [{"name": "use_diff_rcvr", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_use_d_se0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "eop_single_bit", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 2}, {"name": "pinflip", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "usb_ref_disable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_osc_test_mode", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}

phy_config . tx_osc_test_mode

Disable (0) or enable (1) oscillator test mode. If enabled, the device constantly transmits a J/K pattern, which is useful for testing the USB clock. Note that while in oscillator test mode, the device no longer receives SOFs and consequently does not generate the reference signal for clock synchronization. The clock might drift off.

phy_config . usb_ref_disable

0: Enable reference signal generation for clock synchronization, 1: disable it by forcing the associated signals to zero.

phy_config . pinflip

Flip the D+/D- pins. Particularly useful if D+/D- are mapped to SBU1/SBU2 pins of USB-C.

phy_config . eop_single_bit

Recognize a single SE0 bit as an end of packet, otherwise two successive bits are required.

phy_config . tx_use_d_se0

If 1, select the d and se0 TX interface. If 0, select the dp and dn TX interface. This directly controls the output pin of the same name. It is intended to be used to enable the use of a variety of external transceivers, to select an encoding that matches the transceiver.

phy_config . use_diff_rcvr

Detect received K and J symbols from the usb_rx_d signal, which must be driven from an external differential receiver. If 1, make use of the usb_rx_d input. If 0, the usb_rx_d input is ignored and the usb_rx_dp and usb_rx_dn pair are used to detect K and J (useful for some environments, but will be unlikely to pass full USB compliance). Regardless of the state of this field usb_rx_dp and usb_rx_dn are always used to detect SE0. This bit also feeds the rx_enable pin, activating the receiver when the device is not suspended.

wake_control

USB wake module control for suspend / resume

• Offset: 0x90
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "suspend_req", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "wake_ack", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

wake_control . wake_ack

Wake acknowledgement.

Signal to the wake detection module that it may release control of the pull-ups back to the main block and return to an inactive state. The release back to normal state may not happen immediately. The status can be confirmed via wake_events.module_active.

Note that this bit can also be used without powering down, such as when usbdev detects resume signaling before transitions to low power states have begun.

wake_control . suspend_req

Suspend request to the wake detection module.

Trigger the wake detection module to begin monitoring for wake-from-suspend events. When written with a 1, the wake detection module will activate. Activation may not happen immediately, and its status can be verified by checking wake_events.module_active.

wake_events

USB wake module events and debug

• Offset: 0x94
• Reset default: 0x0
• Reset mask: 0x701

Fields

{"reg": [{"name": "module_active", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 7}, {"name": "disconnected", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bus_reset", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bus_not_idle", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

fifo_ctrl

FIFO control register

• Offset: 0x98
• Reset default: 0x0
• Reset mask: 0x7

Fields

{"reg": [{"name": "avout_rst", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "avsetup_rst", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_rst", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

count_out

Counter for OUT side USB events.

• Offset: 0x9c
• Reset default: 0x0
• Reset mask: 0x8ffff0ff

Fields

{"reg": [{"name": "count", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "datatog_out", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "drop_rx", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "drop_avout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ign_avsetup", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoints", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "rst", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

count_out . rst

Write 1 to reset the counter.

count_out . endpoints

Set of OUT endpoints for which this counter is enabled.

count_out . ign_avsetup

Count the SETUP packets that were ignored because there was no buffer in the Av SETUP FIFO.

count_out . drop_avout

Count the OUT packets that could not be accepted because there was no buffer in the Av OUT FIFO. Non-Isochronous OUT packets have been NAKed. Isochronous OUT packets were ignored.

count_out . drop_rx

Count the SETUP/OUT packets ignored, dropped or NAKed because the RX FIFO was full. SETUP packets have been ignored, Isochronous OUT packets have been dropped, and non-Isochronous OUT packets have been NAKed.

count_out . datatog_out

Count the OUT transactions for which the USB device acknowledged the OUT packet and dropped it internally, which is the correct response to a packet transmitted with an incorrect Data Toggle.

The expectation is that this packet is a retry of the previous packet transmission and that the handshake response was not received intact by the USB host, indicating unreliable communications.

Other causes of Data Toggle synchronization failure may result in data loss.

count_out . count

Number of events counted.

count_in

Counter for IN side USB events.

• Offset: 0xa0
• Reset default: 0x0
• Reset mask: 0x8fffe0ff

Fields

{"reg": [{"name": "count", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 5}, {"name": "nodata", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "nak", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "timeout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "endpoints", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "rst", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}

count_in . rst

Write 1 to reset the counter.

count_in . endpoints

Set of endpoints for which this counter is enabled.

count_in . timeout

Count the IN transactions for which the USB host did not respond with a handshake, and the transactions timed out. This indicates that the host did not receive it and decode it as a valid packet, suggesting that communication is unreliable.

Isochronous IN transactions are excluded from this count because there is no handshake response to Isochronous packet transfers.

count_in . nak

Count the IN transactions rejected by the host responding with a NAK handshake.

count_in . nodata

Count the IN transactions that were attempted when there was no packet available in the corresponding ‘configin’ register(s). This is not necessarily an error condition, and the counter primarily offers some visibility into when the IN traffic is underusing the available bus bandwidth. It is of particular utility to Isochronous IN endpoints.

count_in . count

Number of events counted.

count_nodata_in

Count of IN transactions for which no packet data was available.

This secondary register allows some partitioning of endpoints among the two counters, for more targeted measurement, eg. endpoints may be grouped according to the expected bandwidth usage, or Isochronous vs. non-Isochronous transfers.

• Offset: 0xa4
• Reset default: 0x0
• Reset mask: 0x8fff00ff

Fields

{"reg": [{"name": "count", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 8}, {"name": "endpoints", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "rst", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

count_errors

Count of error conditions detected on token packets from the host.

• Offset: 0xa8
• Reset default: 0x0
• Reset mask: 0xf80000ff

Fields

{"reg": [{"name": "count", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 19}, {"name": "pid_invalid", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "bitstuff", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "crc16", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "crc5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rst", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

buffer

2 KiB packet buffer. Divided into thirty two 64-byte buffers.

The packet buffer is used for sending and receiving packets.

• Word Aligned Offset Range: 0x800to0xffc
• Size (words): 512
• Access: rw
• Byte writes are not supported.