Registers

Summary

NameOffsetLengthDescription
usbdev.INTR_STATE0x04Interrupt State Register
usbdev.INTR_ENABLE0x44Interrupt Enable Register
usbdev.INTR_TEST0x84Interrupt Test Register
usbdev.ALERT_TEST0xc4Alert Test Register
usbdev.usbctrl0x104USB Control
usbdev.ep_out_enable0x144Enable an endpoint to respond to transactions in the downstream direction.
usbdev.ep_in_enable0x184Enable an endpoint to respond to transactions in the upstream direction.
usbdev.usbstat0x1c4USB Status
usbdev.avoutbuffer0x204Available OUT Buffer FIFO
usbdev.avsetupbuffer0x244Available SETUP Buffer FIFO
usbdev.rxfifo0x284Received Buffer FIFO
usbdev.rxenable_setup0x2c4Receive SETUP transaction enable
usbdev.rxenable_out0x304Receive OUT transaction enable
usbdev.set_nak_out0x344Set NAK after OUT transactions
usbdev.in_sent0x384IN Transaction Sent
usbdev.out_stall0x3c4OUT Endpoint STALL control
usbdev.in_stall0x404IN Endpoint STALL control
usbdev.configin_00x444Configure IN Transaction
usbdev.configin_10x484Configure IN Transaction
usbdev.configin_20x4c4Configure IN Transaction
usbdev.configin_30x504Configure IN Transaction
usbdev.configin_40x544Configure IN Transaction
usbdev.configin_50x584Configure IN Transaction
usbdev.configin_60x5c4Configure IN Transaction
usbdev.configin_70x604Configure IN Transaction
usbdev.configin_80x644Configure IN Transaction
usbdev.configin_90x684Configure IN Transaction
usbdev.configin_100x6c4Configure IN Transaction
usbdev.configin_110x704Configure IN Transaction
usbdev.out_iso0x744OUT Endpoint isochronous setting
usbdev.in_iso0x784IN Endpoint isochronous setting
usbdev.out_data_toggle0x7c4OUT Endpoints Data Toggles
usbdev.in_data_toggle0x804IN Endpoints Data Toggles
usbdev.phy_pins_sense0x844USB PHY pins sense.
usbdev.phy_pins_drive0x884USB PHY pins drive.
usbdev.phy_config0x8c4USB PHY Configuration
usbdev.wake_control0x904USB wake module control for suspend / resume
usbdev.wake_events0x944USB wake module events and debug
usbdev.fifo_ctrl0x984FIFO control register
usbdev.buffer0x80020482 kB packet buffer. Divided into 32 64-byte buffers.

INTR_STATE

Interrupt State Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x3ffff

Fields

BitsTypeResetName
31:18Reserved
17ro0x0av_setup_empty
16rw1c0x0link_out_err
15rw1c0x0powered
14rw1c0x0frame
13rw1c0x0rx_bitstuff_err
12rw1c0x0rx_pid_err
11rw1c0x0rx_crc_err
10rw1c0x0link_in_err
9rw1c0x0av_overflow
8ro0x0rx_full
7ro0x0av_out_empty
6rw1c0x0link_resume
5rw1c0x0link_suspend
4rw1c0x0link_reset
3rw1c0x0host_lost
2rw1c0x0disconnected
1ro0x0pkt_sent
0ro0x0pkt_received

INTR_STATE . av_setup_empty

Raised when the Available SETUP Buffer FIFO is empty and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the Available SETUP Buffer FIFO must be provided a free buffer before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert.

Raised if a packet to an OUT endpoint started to be received but was then dropped due to an error. This error is raised if the data toggle, token, packet and/or CRC are invalid, or if the appropriate Available OUT Buffer FIFO is empty and/or the Received Buffer FIFO is full when a packet should have been received.

INTR_STATE . powered

Raised if VBUS is applied.

INTR_STATE . frame

Raised when the USB frame number is updated with a valid SOF.

INTR_STATE . rx_bitstuff_err

Raised if an invalid bitstuffing was received.

INTR_STATE . rx_pid_err

Raised if an invalid Packet IDentifier (PID) was received.

INTR_STATE . rx_crc_err

Raised if a CRC error occurred on a received packet.

Raised if a packet to an IN endpoint started to be received but was then dropped due to an error. After transmitting the IN payload, the USB device expects a valid ACK handshake packet. This error is raised if either the packet or CRC is invalid, leading to a NAK instead, or if a different token was received.

INTR_STATE . av_overflow

Raised if a write was done to either the Available OUT Buffer FIFO or the Available SETUP Buffer FIFO when the FIFO was full.

INTR_STATE . rx_full

Raised when the RX FIFO is full and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the RX FIFO must have an entry removed before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert.

INTR_STATE . av_out_empty

Raised when the Available OUT Buffer FIFO is empty and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the Available OUT Buffer FIFO must be provided a free buffer before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert.

Raised when the link becomes active again after being suspended.

Raised if the line has signaled J for longer than 3ms and is therefore in suspend state.

Raised if the link is at SE0 longer than 3 us indicating a link reset (host asserts for min 10 ms, device can react after 2.5 us).

INTR_STATE . host_lost

Raised if link is active but SOF was not received from host for 4.096 ms. The SOF should be every 1 ms.

INTR_STATE . disconnected

Raised if VBUS is lost, thus the link is disconnected.

INTR_STATE . pkt_sent

Raised if a packet was sent as part of an IN transaction. This interrupt is directly tied to whether a sent packet has not been acknowledged in the in_sent register. It should be cleared only after clearing all bits in the in_sent register.

INTR_STATE . pkt_received

Raised if a packet was received using an OUT or SETUP transaction. This interrupt is directly tied to whether the RX FIFO is empty, so it should be cleared only after handling the FIFO entry.

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x3ffff

Fields

BitsTypeResetNameDescription
31:18Reserved
17rw0x0av_setup_emptyEnable interrupt when INTR_STATE.av_setup_empty is set.
16rw0x0link_out_errEnable interrupt when INTR_STATE.link_out_err is set.
15rw0x0poweredEnable interrupt when INTR_STATE.powered is set.
14rw0x0frameEnable interrupt when INTR_STATE.frame is set.
13rw0x0rx_bitstuff_errEnable interrupt when INTR_STATE.rx_bitstuff_err is set.
12rw0x0rx_pid_errEnable interrupt when INTR_STATE.rx_pid_err is set.
11rw0x0rx_crc_errEnable interrupt when INTR_STATE.rx_crc_err is set.
10rw0x0link_in_errEnable interrupt when INTR_STATE.link_in_err is set.
9rw0x0av_overflowEnable interrupt when INTR_STATE.av_overflow is set.
8rw0x0rx_fullEnable interrupt when INTR_STATE.rx_full is set.
7rw0x0av_out_emptyEnable interrupt when INTR_STATE.av_out_empty is set.
6rw0x0link_resumeEnable interrupt when INTR_STATE.link_resume is set.
5rw0x0link_suspendEnable interrupt when INTR_STATE.link_suspend is set.
4rw0x0link_resetEnable interrupt when INTR_STATE.link_reset is set.
3rw0x0host_lostEnable interrupt when INTR_STATE.host_lost is set.
2rw0x0disconnectedEnable interrupt when INTR_STATE.disconnected is set.
1rw0x0pkt_sentEnable interrupt when INTR_STATE.pkt_sent is set.
0rw0x0pkt_receivedEnable interrupt when INTR_STATE.pkt_received is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0x3ffff

Fields

BitsTypeResetNameDescription
31:18Reserved
17wo0x0av_setup_emptyWrite 1 to force INTR_STATE.av_setup_empty to 1.
16wo0x0link_out_errWrite 1 to force INTR_STATE.link_out_err to 1.
15wo0x0poweredWrite 1 to force INTR_STATE.powered to 1.
14wo0x0frameWrite 1 to force INTR_STATE.frame to 1.
13wo0x0rx_bitstuff_errWrite 1 to force INTR_STATE.rx_bitstuff_err to 1.
12wo0x0rx_pid_errWrite 1 to force INTR_STATE.rx_pid_err to 1.
11wo0x0rx_crc_errWrite 1 to force INTR_STATE.rx_crc_err to 1.
10wo0x0link_in_errWrite 1 to force INTR_STATE.link_in_err to 1.
9wo0x0av_overflowWrite 1 to force INTR_STATE.av_overflow to 1.
8wo0x0rx_fullWrite 1 to force INTR_STATE.rx_full to 1.
7wo0x0av_out_emptyWrite 1 to force INTR_STATE.av_out_empty to 1.
6wo0x0link_resumeWrite 1 to force INTR_STATE.link_resume to 1.
5wo0x0link_suspendWrite 1 to force INTR_STATE.link_suspend to 1.
4wo0x0link_resetWrite 1 to force INTR_STATE.link_reset to 1.
3wo0x0host_lostWrite 1 to force INTR_STATE.host_lost to 1.
2wo0x0disconnectedWrite 1 to force INTR_STATE.disconnected to 1.
1wo0x0pkt_sentWrite 1 to force INTR_STATE.pkt_sent to 1.
0wo0x0pkt_receivedWrite 1 to force INTR_STATE.pkt_received to 1.

ALERT_TEST

Alert Test Register

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.

usbctrl

USB Control

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0x7f0003

Fields

BitsTypeResetNameDescription
31:23Reserved
22:16rw0x0device_addressDevice address set by host (this should be copied from the Set Device ID SETUP packet). This will be zeroed by the hardware when the link resets.
15:2Reserved
1wo0x0resume_link_activeWrite a 1 to this bit to instruct usbdev to jump to the LinkResuming state. The write will only have an effect when the device is in the LinkPowered state. Its intention is to handle a resume-from-suspend event after the IP has been powered down.
0rw0x0enableSet to connect the USB interface (i.e. assert the pullup).

ep_out_enable

Enable an endpoint to respond to transactions in the downstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.

  • Offset: 0x14
  • Reset default: 0x0
  • Reset mask: 0xfff

Fields

BitsTypeResetNameDescription
31:12Reserved
11rw0x0enable_11This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.
10rw0x0enable_10This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.
9rw0x0enable_9This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.
8rw0x0enable_8This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.
7rw0x0enable_7This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.
6rw0x0enable_6This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.
5rw0x0enable_5This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.
4rw0x0enable_4This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.
3rw0x0enable_3This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.
2rw0x0enable_2This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.
1rw0x0enable_1This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.
0rw0x0enable_0This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

ep_in_enable

Enable an endpoint to respond to transactions in the upstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.

  • Offset: 0x18
  • Reset default: 0x0
  • Reset mask: 0xfff

Fields

BitsTypeResetNameDescription
31:12Reserved
11rw0x0enable_11This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.
10rw0x0enable_10This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.
9rw0x0enable_9This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.
8rw0x0enable_8This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.
7rw0x0enable_7This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.
6rw0x0enable_6This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.
5rw0x0enable_5This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.
4rw0x0enable_4This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.
3rw0x0enable_3This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.
2rw0x0enable_2This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.
1rw0x0enable_1This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.
0rw0x0enable_0This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

usbstat

USB Status

  • Offset: 0x1c
  • Reset default: 0x80000000
  • Reset mask: 0xcfffffff

Fields

BitsTypeResetName
31ro0x1rx_empty
30roxav_setup_full
29:28Reserved
27:24roxrx_depth
23roxav_out_full
22:20roxav_setup_depth
19:16roxav_out_depth
15roxsense
14:12roxlink_state
11roxhost_lost
10:0roxframe

usbstat . rx_empty

Received Buffer FIFO is empty.

usbstat . av_setup_full

Available SETUP Buffer FIFO is full.

usbstat . rx_depth

Number of buffers in the Received Buffer FIFO.

These buffers have packets that have been received and should be popped from the FIFO and processed.

usbstat . av_out_full

Available OUT Buffer FIFO is full.

usbstat . av_setup_depth

Number of buffers in the Available SETUP Buffer FIFO.

These buffers are available for receiving SETUP DATA packets.

usbstat . av_out_depth

Number of buffers in the Available OUT Buffer FIFO.

These buffers are available for receiving OUT DATA packets.

usbstat . sense

Reflects the state of the sense pin. 1 indicates that the host is providing VBUS. Note that this bit always shows the state of the actual pin and does not take account of the override control.

State of USB link, decoded from line.

ValueNameDescription
0x0disconnectedLink disconnected (no VBUS or no pull-up connected)
0x1poweredLink powered and connected, but not reset yet
0x2powered_suspendedLink suspended (constant idle/J for > 3 ms), but not reset yet
0x3activeLink active
0x4suspendedLink suspended (constant idle for > 3 ms), was active before becoming suspended
0x5active_nosofLink active but no SOF has been received since the last reset.
0x6resumingLink resuming to an active state, pending the end of resume signaling

Other values are reserved.

usbstat . host_lost

Start of frame not received from host for 4.096 ms and the line is active.

usbstat . frame

Frame index received from host. On an active link, this will increment every milisecond.

avoutbuffer

Available OUT Buffer FIFO

  • Offset: 0x20
  • Reset default: 0x0
  • Reset mask: 0x1f

Fields

BitsTypeResetNameDescription
31:5Reserved
4:0wo0x0bufferThis field contains the buffer ID being passed to the USB receive engine. If the Available OUT Buffer FIFO is full, any write operations are discarded.

avsetupbuffer

Available SETUP Buffer FIFO

  • Offset: 0x24
  • Reset default: 0x0
  • Reset mask: 0x1f

Fields

BitsTypeResetNameDescription
31:5Reserved
4:0wo0x0bufferThis field contains the buffer ID being passed to the USB receive engine. If the Available SETUP Buffer FIFO is full, any write operations are discarded.

rxfifo

Received Buffer FIFO

  • Offset: 0x28
  • Reset default: 0x0
  • Reset mask: 0xf87f1f

Fields

BitsTypeResetNameDescription
31:24Reserved
23:20roxepThis field contains the endpoint ID to which the packet was directed.
19roxsetupThis bit indicates if the received transaction is of type SETUP (1) or OUT (0).
18:15Reserved
14:8roxsizeThis field contains the data length in bytes of the packet written to the buffer.
7:5Reserved
4:0roxbufferThis field contains the buffer ID that data was received into. On read the buffer ID is popped from the Received Buffer FIFO and returned to software.

rxenable_setup

Receive SETUP transaction enable

  • Offset: 0x2c
  • Reset default: 0x0
  • Reset mask: 0xfff

Fields

BitsTypeResetNameDescription
31:12Reserved
11rw0x0setup_11This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
10rw0x0setup_10This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
9rw0x0setup_9This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
8rw0x0setup_8This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
7rw0x0setup_7This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
6rw0x0setup_6This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
5rw0x0setup_5This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
4rw0x0setup_4This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
3rw0x0setup_3This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
2rw0x0setup_2This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
1rw0x0setup_1This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
0rw0x0setup_0This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

rxenable_out

Receive OUT transaction enable

  • Offset: 0x30
  • Reset default: 0x0
  • Reset mask: 0xfff

Fields

BitsTypeResetName
31:12Reserved
11rw0x0out_11
10rw0x0out_10
9rw0x0out_9
8rw0x0out_8
7rw0x0out_7
6rw0x0out_6
5rw0x0out_5
4rw0x0out_4
3rw0x0out_3
2rw0x0out_2
1rw0x0out_1
0rw0x0out_0

rxenable_out . out_11

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_10

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_9

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_8

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_7

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_6

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_5

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_4

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_3

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_2

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_1

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

rxenable_out . out_0

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

set_nak_out

Set NAK after OUT transactions

  • Offset: 0x34
  • Reset default: 0x0
  • Reset mask: 0xfff

Fields

BitsTypeResetNameDescription
31:12Reserved
11rw0x0enable_11When this bit is set, hardware will clear this endpoint’s rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.
10rw0x0enable_10When this bit is set, hardware will clear this endpoint’s rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.
9rw0x0enable_9When this bit is set, hardware will clear this endpoint’s rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.
8rw0x0enable_8When this bit is set, hardware will clear this endpoint’s rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.
7rw0x0enable_7When this bit is set, hardware will clear this endpoint’s rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.
6rw0x0enable_6When this bit is set, hardware will clear this endpoint’s rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.
5rw0x0enable_5When this bit is set, hardware will clear this endpoint’s rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.
4rw0x0enable_4When this bit is set, hardware will clear this endpoint’s rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.
3rw0x0enable_3When this bit is set, hardware will clear this endpoint’s rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.
2rw0x0enable_2When this bit is set, hardware will clear this endpoint’s rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.
1rw0x0enable_1When this bit is set, hardware will clear this endpoint’s rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.
0rw0x0enable_0When this bit is set, hardware will clear this endpoint’s rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

in_sent

IN Transaction Sent

  • Offset: 0x38
  • Reset default: 0x0
  • Reset mask: 0xfff

Fields

BitsTypeResetNameDescription
31:12Reserved
11rw1c0x0sent_11This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.
10rw1c0x0sent_10This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.
9rw1c0x0sent_9This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.
8rw1c0x0sent_8This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.
7rw1c0x0sent_7This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.
6rw1c0x0sent_6This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.
5rw1c0x0sent_5This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.
4rw1c0x0sent_4This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.
3rw1c0x0sent_3This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.
2rw1c0x0sent_2This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.
1rw1c0x0sent_1This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.
0rw1c0x0sent_0This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

out_stall

OUT Endpoint STALL control

  • Offset: 0x3c
  • Reset default: 0x0
  • Reset mask: 0xfff

Fields

BitsTypeResetName
31:12Reserved
11rw0x0endpoint_11
10rw0x0endpoint_10
9rw0x0endpoint_9
8rw0x0endpoint_8
7rw0x0endpoint_7
6rw0x0endpoint_6
5rw0x0endpoint_5
4rw0x0endpoint_4
3rw0x0endpoint_3
2rw0x0endpoint_2
1rw0x0endpoint_1
0rw0x0endpoint_0

out_stall . endpoint_11

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_10

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_9

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_8

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_7

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_6

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_5

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_4

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_3

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_2

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_1

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

out_stall . endpoint_0

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall

IN Endpoint STALL control

  • Offset: 0x40
  • Reset default: 0x0
  • Reset mask: 0xfff

Fields

BitsTypeResetName
31:12Reserved
11rw0x0endpoint_11
10rw0x0endpoint_10
9rw0x0endpoint_9
8rw0x0endpoint_8
7rw0x0endpoint_7
6rw0x0endpoint_6
5rw0x0endpoint_5
4rw0x0endpoint_4
3rw0x0endpoint_3
2rw0x0endpoint_2
1rw0x0endpoint_1
0rw0x0endpoint_0

in_stall . endpoint_11

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_10

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_9

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_8

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_7

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_6

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_5

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_4

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_3

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_2

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_1

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

in_stall . endpoint_0

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

configin

Configure IN Transaction

  • Reset default: 0x0
  • Reset mask: 0xc0007f1f

Instances

NameOffset
configin_00x44
configin_10x48
configin_20x4c
configin_30x50
configin_40x54
configin_50x58
configin_60x5c
configin_70x60
configin_80x64
configin_90x68
configin_100x6c
configin_110x70

Fields

BitsTypeResetName
31rw0x0rdy
30rw1c0x0pend
29:15Reserved
14:8rw0x0size
7:5Reserved
4:0rw0x0buffer

configin . rdy

This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data.

This bit will also be cleared if an enabled SETUP transaction is received on the endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit.

configin . pend

This bit indicates a pending transaction was canceled by the hardware.

The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected.

The bit remains set until cleared by being written with a 1.

configin . size

The number of bytes to send from the buffer.

If this is 0 then a CRC only packet is sent.

If this is greater than 64 then 64 bytes are sent.

configin . buffer

The buffer ID containing the data to send when an IN transaction is received on the endpoint.

out_iso

OUT Endpoint isochronous setting

  • Offset: 0x74
  • Reset default: 0x0
  • Reset mask: 0xfff

Fields

BitsTypeResetName
31:12Reserved
11rw0x0iso_11
10rw0x0iso_10
9rw0x0iso_9
8rw0x0iso_8
7rw0x0iso_7
6rw0x0iso_6
5rw0x0iso_5
4rw0x0iso_4
3rw0x0iso_3
2rw0x0iso_2
1rw0x0iso_1
0rw0x0iso_0

out_iso . iso_11

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_10

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_9

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_8

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_7

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_6

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_5

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_4

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_3

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_2

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_1

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_iso . iso_0

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso

IN Endpoint isochronous setting

  • Offset: 0x78
  • Reset default: 0x0
  • Reset mask: 0xfff

Fields

BitsTypeResetName
31:12Reserved
11rw0x0iso_11
10rw0x0iso_10
9rw0x0iso_9
8rw0x0iso_8
7rw0x0iso_7
6rw0x0iso_6
5rw0x0iso_5
4rw0x0iso_4
3rw0x0iso_3
2rw0x0iso_2
1rw0x0iso_1
0rw0x0iso_0

in_iso . iso_11

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_10

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_9

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_8

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_7

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_6

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_5

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_4

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_3

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_2

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_1

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

in_iso . iso_0

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint’s number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

out_data_toggle

OUT Endpoints Data Toggles

  • Offset: 0x7c
  • Reset default: 0x0
  • Reset mask: 0xfff0fff

Fields

BitsTypeResetNameDescription
31:28Reserved
27:16rwxmaskReads as zero. When writing, a set bit will cause the Data Toggle flag of the corresponding OUT endpoint to be updated. A clear bit will leave the flag for the corresponding endpoint unchanged.
15:12Reserved
11:0rwxstatusReading returns the current state of the OUT endpoint Data Toggle flags. Writing sets the Data Toggle flag for each endpoint if the corresponding mask bit in the upper half of this register is set.

in_data_toggle

IN Endpoints Data Toggles

  • Offset: 0x80
  • Reset default: 0x0
  • Reset mask: 0xfff0fff

Fields

BitsTypeResetNameDescription
31:28Reserved
27:16rwxmaskReads as zero. When writing, a set bit will cause the Data Toggle flag of the corresponding IN endpoint to be updated. A clear bit will leave the flag for the corresponding endpoint unchanged.
15:12Reserved
11:0rwxstatusReading returns the current state of the IN endpoint Data Toggle flags. Writing sets the Data Toggle flag for each endpoint if the corresponding mask bit in the upper half of this register is set.

phy_pins_sense

USB PHY pins sense. This register can be used to read out the state of the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing.

  • Offset: 0x84
  • Reset default: 0x0
  • Reset mask: 0x11f07

Fields

BitsTypeResetNameDescription
31:17Reserved
16roxpwr_senseUSB power sense signal.
15:13Reserved
12roxtx_oe_oUSB OE output (readback).
11roxtx_se0_oUSB single-ended zero output (readback).
10roxtx_d_oUSB transmit data value (readback).
9roxtx_dn_oUSB transmit D- output (readback).
8roxtx_dp_oUSB transmit D+ output (readback).
7:3Reserved
2roxrx_d_iUSB data input from an external differential receiver, if available.
1roxrx_dn_iUSB D- input.
0roxrx_dp_iUSB D+ input.

phy_pins_drive

USB PHY pins drive. This register can be used to control the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing.

  • Offset: 0x88
  • Reset default: 0x0
  • Reset mask: 0x100ff

Fields

BitsTypeResetNameDescription
31:17Reserved
16rw0x0en0: Outputs are controlled by the hardware block. 1: Outputs are controlled with this register.
15:8Reserved
7rw0x0dn_pullup_en_oUSB D- pullup enable output.
6rw0x0dp_pullup_en_oUSB D+ pullup enable output.
5rw0x0rx_enable_oEnable differential receiver.
4rw0x0oe_oUSB OE output.
3rw0x0se0_oUSB single-ended zero output.
2rw0x0d_oUSB transmit data output, encoding K and J when se0_o is 0.
1rw0x0dn_oUSB transmit D- output, used with dp_o.
0rw0x0dp_oUSB transmit D+ output, used with dn_o.

phy_config

USB PHY Configuration

  • Offset: 0x8c
  • Reset default: 0x4
  • Reset mask: 0xe7

Fields

BitsTypeResetName
31:8Reserved
7rw0x0tx_osc_test_mode
6rw0x0usb_ref_disable
5rw0x0pinflip
4:3Reserved
2rw0x1eop_single_bit
1rw0x0tx_use_d_se0
0rw0x0use_diff_rcvr

phy_config . tx_osc_test_mode

Disable (0) or enable (1) oscillator test mode. If enabled, the device constantly transmits a J/K pattern, which is useful for testing the USB clock. Note that while in oscillator test mode, the device no longer receives SOFs and consequently does not generate the reference signal for clock synchronization. The clock might drift off.

phy_config . usb_ref_disable

0: Enable reference signal generation for clock synchronization, 1: disable it by forcing the associated signals to zero.

phy_config . pinflip

Flip the D+/D- pins. Particularly useful if D+/D- are mapped to SBU1/SBU2 pins of USB-C.

phy_config . eop_single_bit

Recognize a single SE0 bit as an end of packet, otherwise two successive bits are required.

phy_config . tx_use_d_se0

If 1, select the d and se0 TX interface. If 0, select the dp and dn TX interface. This directly controls the output pin of the same name. It is intended to be used to enable the use of a variety of external transceivers, to select an encoding that matches the transceiver.

phy_config . use_diff_rcvr

Detect received K and J symbols from the usb_rx_d signal, which must be driven from an external differential receiver. If 1, make use of the usb_rx_d input. If 0, the usb_rx_d input is ignored and the usb_rx_dp and usb_rx_dn pair are used to detect K and J (useful for some environments, but will be unlikely to pass full USB compliance). Regardless of the state of this field usb_rx_dp and usb_rx_dn are always used to detect SE0. This bit also feeds the rx_enable pin, activating the receiver when the device is not suspended.

wake_control

USB wake module control for suspend / resume

  • Offset: 0x90
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetName
31:2Reserved
1wo0x0wake_ack
0wo0x0suspend_req

wake_control . wake_ack

Wake acknowledgement.

Signal to the wake detection module that it may release control of the pull-ups back to the main block and return to an inactive state. The release back to normal state may not happen immediately. The status can be confirmed via wake_events.module_active.

Note that this bit can also be used without powering down, such as when usbdev detects resume signaling before transitions to low power states have begun.

wake_control . suspend_req

Suspend request to the wake detection module.

Trigger the wake detection module to begin monitoring for wake-from-suspend events. When written with a 1, the wake detection module will activate. Activation may not happen immediately, and its status can be verified by checking wake_events.module_active.

wake_events

USB wake module events and debug

  • Offset: 0x94
  • Reset default: 0x0
  • Reset mask: 0x301

Fields

BitsTypeResetNameDescription
31:10Reserved
9ro0x0bus_resetUSB aon wake module detected a bus reset while monitoring events.
8ro0x0disconnectedUSB aon wake module detected VBUS was interrupted while monitoring events.
7:1Reserved
0ro0x0module_activeUSB aon wake module is active, monitoring events and controlling the pull-ups.

fifo_ctrl

FIFO control register

  • Offset: 0x98
  • Reset default: 0x0
  • Reset mask: 0x7

Fields

BitsTypeResetNameDescription
31:3Reserved
2wo0x0rx_rstSoftware reset the of Rx Buffer FIFO. This must be used only when the USB device is not connected to the USB.
1wo0x0avsetup_rstSoftware reset of the Available SETUP Buffer FIFO. This must be used only when the USB device is not connected to the USB.
0wo0x0avout_rstSoftware reset of the Available OUT Buffer FIFO. This must be used only when the USB device is not connected to the USB.

buffer

2 kB packet buffer. Divided into 32 64-byte buffers.

The packet buffer is used for sending and receiveing packets.

  • Word Aligned Offset Range: 0x800to0xffc
  • Size (words): 512
  • Access: rw
  • Byte writes are not supported.