Summary

NameOffsetLengthDescription
edn.INTR_STATE0x04Interrupt State Register
edn.INTR_ENABLE0x44Interrupt Enable Register
edn.INTR_TEST0x84Interrupt Test Register
edn.ALERT_TEST0xc4Alert Test Register
edn.REGWEN0x104Register write enable for all control registers
edn.CTRL0x144EDN control register
edn.BOOT_INS_CMD0x184EDN boot instantiate command register
edn.BOOT_GEN_CMD0x1c4EDN boot generate command register
edn.SW_CMD_REQ0x204EDN csrng app command request register
edn.SW_CMD_STS0x244EDN software command status register
edn.HW_CMD_STS0x284EDN hardware command status register
edn.RESEED_CMD0x2c4EDN csrng reseed command register
edn.GENERATE_CMD0x304EDN csrng generate command register
edn.MAX_NUM_REQS_BETWEEN_RESEEDS0x344EDN maximum number of requests between reseeds register
edn.RECOV_ALERT_STS0x384Recoverable alert status register
edn.ERR_CODE0x3c4Hardware detection of fatal error conditions status register
edn.ERR_CODE_TEST0x404Test error conditions register
edn.MAIN_SM_STATE0x444Main state machine state observation register

INTR_STATE

Interrupt State Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw1c0x0edn_fatal_errAsserted when a FIFO error occurs.
0rw1c0x0edn_cmd_req_doneAsserted when a software CSRNG request has completed.

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw0x0edn_fatal_errEnable interrupt when INTR_STATE.edn_fatal_err is set.
0rw0x0edn_cmd_req_doneEnable interrupt when INTR_STATE.edn_cmd_req_done is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1wo0x0edn_fatal_errWrite 1 to force INTR_STATE.edn_fatal_err to 1.
0wo0x0edn_cmd_req_doneWrite 1 to force INTR_STATE.edn_cmd_req_done to 1.

ALERT_TEST

Alert Test Register

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1wo0x0fatal_alertWrite 1 to trigger one alert event of this kind.
0wo0x0recov_alertWrite 1 to trigger one alert event of this kind.

REGWEN

Register write enable for all control registers

  • Offset: 0x10
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1REGWENWhen true, the CTRL can be written by software. When false, this field read-only. Defaults true, write zero to clear. Note that this needs to be cleared after initial configuration at boot in order to lock in the listed register settings.

CTRL

EDN control register

  • Offset: 0x14
  • Reset default: 0x9999
  • Reset mask: 0xffff
  • Register enable: REGWEN

Fields

BitsTypeResetName
31:16Reserved
15:12rw0x9CMD_FIFO_RST
11:8rw0x9AUTO_REQ_MODE
7:4rw0x9BOOT_REQ_MODE
3:0rw0x9EDN_ENABLE

CTRL . CMD_FIFO_RST

Setting this field to kMultiBitBool4True clears the two command FIFOs: the RESEED_CMD FIFO and the GENERATE_CMD FIFO. This field must be set to the reset state by software before any further commands can be issued to these FIFOs.

CTRL . AUTO_REQ_MODE

Setting this field to kMultiBitBool4True will enable the EDN block to automatically send another request to CSRNG application interface. It is assumed that a CSRNG instantiate command will be issued using the SW_CMD_REQ register interface. When this command has an command ack returned from CSRNG, a new generate command will be send out again without software intervention. It is expected that the generate command will be sent repeatedly so that a continuous supply of entropy can be delivered to the endpoints. Reseed commands will be sent on a programmable basic between generate commands. The GENERATE_CMD, RESEED_CMD, and MAX_NUM_REQS_BETWEEN_RESEEDS registers must set up before the SW_CMD_REQ register command is issued.

CTRL . BOOT_REQ_MODE

Setting this field to kMultiBitBool4True will enable the feature where the EDN block will automatically send a boot-time request to the CSRNG application interface. The purpose of this feature is to request entropy as fast as possible after reset, and during chip boot-time.

CTRL . EDN_ENABLE

Setting this field to kMultiBitBool4True enables the EDN module. The modules of the entropy complex may only be enabled and disabled in a specific order, see Programmers Guide for details.

BOOT_INS_CMD

EDN boot instantiate command register

  • Offset: 0x18
  • Reset default: 0x901
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x901BOOT_INS_CMDThis field is used as the value for Instantiate command at boot time.

BOOT_GEN_CMD

EDN boot generate command register

  • Offset: 0x1c
  • Reset default: 0xfff003
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0xfff003BOOT_GEN_CMDThis field is used as the value for generate command at boot time.

SW_CMD_REQ

EDN csrng app command request register

  • Offset: 0x20
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetName
31:0woxSW_CMD_REQ

SW_CMD_REQ . SW_CMD_REQ

Any CSRNG action can be initiated by writing a CSRNG command to this register. The application interface must wait for the “ack” to return before issuing new commands. This interface is intended to be controlled solely by software.

If CTRL.AUTO_REQ_MODE is set, only the first instantiate command has any effect. After that command has been processed, writes to this register register will have no effect on operation. Note that CSRNG command format details can be found in the CSRNG documentation.

SW_CMD_STS

EDN software command status register

  • Offset: 0x24
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

BitsTypeResetName
31:4Reserved
3ro0x0CMD_ACK
2ro0x0CMD_STS
1ro0x0CMD_RDY
0ro0x0CMD_REG_RDY

SW_CMD_STS . CMD_ACK

This one bit field indicates when a SW command has been acknowledged by the CSRNG. It is set to low each time a new command is written to SW_CMD_REQ. The field is set to high once a SW command request has been acknowledged by the CSRNG. 0b0: The last SW command has not been acknowledged yet. 0b1: The last SW command has been acknowledged.

SW_CMD_STS . CMD_STS

This one bit field represents the status code returned with the CSRNG application command ack. It is updated each time a SW command is acknowledged by CSRNG. To check whether a command was succesful, wait for INTR_STATE.EDN_CMD_REQ_DONE or SW_CMD_STS.CMD_ACK to be high and then check the value of this field. 0b0: Request completed successfully. 0b1: Request completed with an error.

SW_CMD_STS . CMD_RDY

This bit indicates when the EDN is ready to accept the next command. Before starting to write a new command to SW_CMD_REQ, this field needs to be polled. 0b0: The EDN is not ready to accept commands or the last command hasn’t been acked yet. 0b1: The EDN is ready to accept the next command.

SW_CMD_STS . CMD_REG_RDY

This bit indicates when SW_CMD_REQ is ready to accept the next word. This bit has to be polled before each word of a command is written to SW_CMD_REQ. 0b0: The EDN is not ready to accept the next word yet. 0b1: The EDN is ready to accept the next word.

HW_CMD_STS

EDN hardware command status register

  • Offset: 0x28
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetName
31:8Reserved
7:4ro0x0CMD_TYPE
3ro0x0CMD_ACK
2ro0x0CMD_STS
1ro0x0AUTO_MODE
0ro0x0BOOT_MODE

HW_CMD_STS . CMD_TYPE

This field contains the application command type of the hardware controlled command issued last. The application command selects one of five operations to perform. A description of the application command types can be found here.

HW_CMD_STS . CMD_ACK

This one bit field indicates when a HW command has been acknowledged by the CSRNG. It is set to low each time a new command is sent to the CSRNG. The field is set to high once a HW command request has been acknowledged by the CSRNG. 0b0: The last HW command has not been acknowledged yet. 0b1: The last HW command has been acknowledged.

HW_CMD_STS . CMD_STS

This one bit field represents the status code returned with the CSRNG application command ack. It is updated each time a HW command is acknowledged by CSRNG. 0b0: Request completed successfully. 0b1: Request completed with an error.

HW_CMD_STS . AUTO_MODE

This one bit field indicates whether the EDN is in the hardware controlled part of auto mode. The instantiate command is issued via SW interface and is thus not part of the hardware controlled part of auto mode. 0b0: The EDN is not in the hardware controlled part of auto mode. 0b1: The EDN is in the hardware controlled part of auto mode.

HW_CMD_STS . BOOT_MODE

This one bit field indicates whether the EDN is in the hardware controlled boot mode. 0b0: The EDN is not in boot mode. 0b1: The EDN is in boot mode.

RESEED_CMD

EDN csrng reseed command register

  • Offset: 0x2c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetName
31:0woxRESEED_CMD

RESEED_CMD . RESEED_CMD

Writing this register will fill a FIFO with up to 13 command words (32b words). This FIFO will be used to automatically send out a reseed command to the CSRNG application interface when in CTRL.AUTO_REQ_MODE. This command will be sent only after the MAX_NUM_REQS_BETWEEN_RESEEDS counter value has reached zero.

If more than 13 entires are written to the FIFO, the design will automatically generate a fatal alert.

Note that CSRNG command format details can be found in the CSRNG documentation.

GENERATE_CMD

EDN csrng generate command register

  • Offset: 0x30
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetName
31:0woxGENERATE_CMD

GENERATE_CMD . GENERATE_CMD

Writing this register will fill a FIFO with up to 13 command words (32b words). This FIFO will be used to automatically send out a generate command to the CSRNG appl interface when in CTRL.AUTO_REQ_MODE. This command will be sent only after receiving a command ack from the previous command.

If more than 13 entires are written to the FIFO, the design will automatically generate a fatal alert.

Note that CSRNG command format details can be found in the CSRNG documentation.

MAX_NUM_REQS_BETWEEN_RESEEDS

EDN maximum number of requests between reseeds register

  • Offset: 0x34
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetName
31:0rw0x0MAX_NUM_REQS_BETWEEN_RESEEDS

MAX_NUM_REQS_BETWEEN_RESEEDS . MAX_NUM_REQS_BETWEEN_RESEEDS

Setting this field will set the number of generate requests that can be made to CSRNG before a reseed request is made. This value only has meaning when in CTRL.AUTO_REQ_MODE. This register supports a maximum of 2^32 requests between reseeds. This register will be used by a counter that counts down, triggering an automatic reseed when it reaches zero.

RECOV_ALERT_STS

Recoverable alert status register

  • Offset: 0x38
  • Reset default: 0x0
  • Reset mask: 0x300f

Fields

BitsTypeResetNameDescription
31:14Reserved
13rw0c0x0CSRNG_ACK_ERRThis bit is set when the CSRNG returns an acknowledgement where the status signal is high. Writing a zero resets this status bit.
12rw0c0x0EDN_BUS_CMP_ALERTThis bit is set when the interal entropy bus value is equal to the prior valid value on the bus, indicating a possible attack. Writing a zero resets this status bit.
11:4Reserved
3rw0c0x0CMD_FIFO_RST_FIELD_ALERTThis bit is set when the CMD_FIFO_RST field is set to an illegal value, something other than kMultiBitBool4True or kMultiBitBool4False. Writing a zero resets this status bit.
2rw0c0x0AUTO_REQ_MODE_FIELD_ALERTThis bit is set when the CTRL.AUTO_REQ_MODE field is set to an illegal value, something other than kMultiBitBool4True or kMultiBitBool4False. Writing a zero resets this status bit.
1rw0c0x0BOOT_REQ_MODE_FIELD_ALERTThis bit is set when the BOOT_REQ_MODE field is set to an illegal value, something other than kMultiBitBool4True or kMultiBitBool4False. Writing a zero resets this status bit.
0rw0c0x0EDN_ENABLE_FIELD_ALERTThis bit is set when the EDN_ENABLE field is set to an illegal value, something other than kMultiBitBool4True or kMultiBitBool4False. Writing a zero resets this status bit.

ERR_CODE

Hardware detection of fatal error conditions status register

  • Offset: 0x3c
  • Reset default: 0x0
  • Reset mask: 0x70700003

Fields

BitsTypeResetName
31Reserved
30ro0x0FIFO_STATE_ERR
29ro0x0FIFO_READ_ERR
28ro0x0FIFO_WRITE_ERR
27:23Reserved
22ro0x0EDN_CNTR_ERR
21ro0x0EDN_MAIN_SM_ERR
20ro0x0EDN_ACK_SM_ERR
19:2Reserved
1ro0x0SFIFO_GENCMD_ERR
0ro0x0SFIFO_RESCMD_ERR

ERR_CODE . FIFO_STATE_ERR

This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any FIFO where both the empty and full status bits are set. This bit will stay set until the next reset.

ERR_CODE . FIFO_READ_ERR

This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any empty FIFO that has recieved a read pulse. This bit will stay set until the next reset.

ERR_CODE . FIFO_WRITE_ERR

This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any full FIFO that has been recieved a write pulse. This bit will stay set until the next reset.

ERR_CODE . EDN_CNTR_ERR

This bit will be set to one when a hardened counter has detected an error condition. This error will signal a fatal alert. This bit will stay set until the next reset.

ERR_CODE . EDN_MAIN_SM_ERR

This bit will be set to one when an illegal state has been detected for the EDN main stage state machine. This error will signal a fatal alert. This bit will stay set until the next reset.

ERR_CODE . EDN_ACK_SM_ERR

This bit will be set to one when an illegal state has been detected for the EDN ack stage state machine. This error will signal a fatal alert. This bit will stay set until the next reset.

ERR_CODE . SFIFO_GENCMD_ERR

This bit will be set to one when an error has been detected for the generate command FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). When this bit is set, a fatal error condition will result. This bit will stay set until the next reset.

ERR_CODE . SFIFO_RESCMD_ERR

This bit will be set to one when an error has been detected for the reseed command FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). When this bit is set, a fatal error condition will result.

ERR_CODE_TEST

Test error conditions register

  • Offset: 0x40
  • Reset default: 0x0
  • Reset mask: 0x1f

Fields

BitsTypeResetName
31:5Reserved
4:0rw0x0ERR_CODE_TEST

ERR_CODE_TEST . ERR_CODE_TEST

Setting this field will set the bit number for which an error will be forced in the hardware. This bit number is that same one found in the ERR_CODE register. The action of writing this register will force an error pulse. The sole purpose of this register is to test that any error properly propagates to either an interrupt or an alert.

MAIN_SM_STATE

Main state machine state observation register

  • Offset: 0x44
  • Reset default: 0xc1
  • Reset mask: 0x1ff

Fields

BitsTypeResetNameDescription
31:9Reserved
8:0ro0xc1MAIN_SM_STATEThis is the state of the EDN main state machine. See the RTL file edn_main_sm for the meaning of the values.