Testplan - OpenTitan Documentation

Testpoints

Stage	Name	Tests	Description
V1	smoke	spi_device_smoke	Use default SRAM fifo setting. Seq: Write a word data to TX memory and update wptr Send a word SPI transfer Read a word data from RX memory and update rptr Compare the data and check no pending data in SRAM FIFO Repeat above steps
V1	csr_hw_reset	spi_device_csr_hw_reset	Verify the reset values as indicated in the RAL specification. Write all CSRs with a random value. Apply reset to the DUT as well as the RAL model. Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_rw	spi_device_csr_rw	Verify accessibility of CSRs as indicated in the RAL specification. Loop through each CSR to write it with a random value. Read the CSR back and check for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_bit_bash	spi_device_csr_bit_bash	Verify no aliasing within individual bits of a CSR. Walk a 1 through each CSR by flipping 1 bit at a time. Read the CSR back and check for correctness while adhering to its access policies. This verify that writing a specific bit within the CSR did not affect any of the other bits. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_aliasing	spi_device_csr_aliasing	Verify no aliasing within the CSR address space. Loop through each CSR to write it with a random value Shuffle and read ALL CSRs back. All CSRs except for the one that was written in this iteration should read back the previous value. The CSR that was written in this iteration is checked for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	Verify random reset during CSR/memory access. Run csr_rw sequence to randomly access CSRs If memory exists, run mem_partial_access in parallel with csr_rw Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw spi_device_csr_aliasing	Verify regwen CSR and its corresponding lockable CSRs. Randomly access all CSRs Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers Note: If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing. If regwen CSR is HW updated, a separate test should be created to test it. This is only applicable if the block contains regwen and locakable CSRs.
V1	mem_walk	spi_device_mem_walk	Verify accessibility of all memories in the design. Run the standard UVM mem walk sequence on all memories in the RAL model. It is mandatory to run this test from all available interfaces the memories are accessible from.
V1	mem_partial_access	spi_device_mem_partial_access	Verify partial-accessibility of all memories in the design. Do partial reads and writes into the memories and verify the outcome for correctness. Also test outstanding access on memories
V2	base_random_seq	spi_device_txrx	Create 3 parallel threads Write random data to TX memory unless fifo is full Send SPI transfer unless TX is empty or RX is full Read RX memory unless RX is empty
V2	fifo_full	spi_device_fifo_full	Increase the chance to have fifo full by following Reduce delay to write TX memory Increase delay to read RX memory
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	Override spi_device_txrx_vseq to send SPI transfer without checking TX/RX fifo, note: When TX is underflow, SW shouldn't update wptr if spi isn't idle, otherwise, spi may send mis-aligned data When RX is overflow, data will be lost and if SW update rptr, received data may be mis-aligned Ensure underflow/overflow is triggered correctly
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	Drive dummy sck without csb or drive dummy csb without sck, and test no impact on the design
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	Add extra delay between spi clock edge or extra delay between 2 words data This is to test host pause transfer for a while without turning off csb and then stream in data again
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	Reset TX async fifo when SPI interface is idle Fill TX SRAM FIFO with some data, which will be transfered to TX async FIFO Write 0 into read and write point of TX SRAM FIFO Program `rst_txfifo` to reset the async FIFO Check `async_fifo_level.txlvl` is 0 Fill TX SRAM FIFO with some other data and enable SPI transfer Check SPI device sends and receives the correct data
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	Reset RX async fifo when SPI interface is idle Configure RX SRAM FIFO with a small size, so that it's easy to fill up Start SPI transfers to fill up the RX SRAM FIFO and at least part of the RX async FIFO Program `rst_rxfifo` to reset the async FIFO Check `async_fifo_level.rxlvl` is 0 Write 0 into read and write point of RX SRAM FIFO Fill TX SRAM FIFO with some other data and start another SPI transfers Check SPI device sends and receives the correct data
V2	interrupts	spi_device_intr	Test all supported interrupts: tx/rx lvl rx full rx error overflow/underflow
V2	abort	spi_device_abort	Fill TX FIFO without host traffic Issue Abort to control register Poll until abort_done in status register TBD additional checking
V2	byte_transfer_on_spi	spi_device_byte_transfer	send spi transfer on byte granularity, and make sure the timer never expires
V2	rx_timeout	spi_device_rx_timeout	Send spi transfer on byte granularity, and timer may expires Only check data in sequence level when timer expires. Monitor and scoreboard don't model the timer feature Note: Timeout only for RX
V2	bit_transfer_on_spi	spi_device_bit_transfer	Send spi transfer on bit granularity If TX drives < 7 bits, this byte will be sent in next CSB. If TX drives 7 bits and set CSB to high, this byte won't be sent in next CSB
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	Set fifo size to 4 bytes(minimum), 2k-4bytes(maximum) and others
V2	perf	spi_device_perf	Run spi_device_fifi_full_vseq with very small delays
V2	csb_read	spi_device_csb_read	Read CSB value from CSR and check the correctness This feature is for debug only, so it's sufficient to verify with this direct sequence: Assign both CSB pins with random values and read the CSB CSRs to check the values
V2	mem_parity	spi_device_mem_parity	Test memory parity error pick a random mem address to inject parity errors and read it back, then check it returns d_error with all 1s data.
V2	mem_cfg	spi_device_ram_cfg	Test cfg_i connectivity between spi_device and prim_ram_2p. Randomly set dut.ram_cfg_i and check this value is propagated to prim_mem_2p.
V2	tpm_read	spi_device_tpm_rw	Set TPM_CFG.TPM_MODE to CRB mode and set TPM_CFG.EN. Randomise other fields in TPM_CFG. Assert the tpm_csb. Send TPM read command over the SPI bus with a randomised address. Check TPM_CMD_ADDR. Confirm FIFO behaviour dictated by TPM_CFG.tpm_mode. Check TPM_STATUS.cmdaddr_notempty and INTR_STATE.tpm_header_notempty, they should be asserted if hw_reg_dis == 0. If hw_reg_dis == 0, the data is returned to the host via return-by-HW register, else the data is returned via read FIFO. Confirm that the TPM submodule sends WAIT until the read FIFO is available. Check the read FIFO. When available, confirm that the TPM submodule sends START followed by the register value. Compare this value with the expected value.
V2	tpm_write	spi_device_tpm_rw	Set TPM_CFG.TPM_MODE to CRB mode and set TPM_CFG.EN. Randomise other fields in TPM_CFG. Assert the tpm_csb. Send TPM write command with a randomised address. Check TPM_CMD_ADDR and write FIFO. Check TPM_STATUS.cmdaddr_notempty and INTR_STATE.tpm_header_notempty. Based on FIFO status, check SPI bus to confirm WAIT or START sent. Check that the TPM submodule accepts write data without the WAIT state if the write FIFO is empty. Otherwise, check WAIT until the write FIFO becomes available (empty).
V2	tpm_hw_reg	spi_device_tpm_sts_read spi_device_tpm_read_hw_reg	Configure `TPM_CFG` as follows to have DUT directly respond for the access to the HW registers. Set `tpm_mode` to fifo mode. Set `hw_reg_dis` to 0. Set `tpm_reg_chk_dis` to 0. Set `invalid_locality` to 1. Send SPI transactions of varying HW registers. In the meanwhile, SW updates the HW registers. Ensure that the data returned is correct for the given address and active locality.
V2	tpm_fully_random_case	spi_device_tpm_all	Configure `TPM_CFG.EN` to On and fully randomize other TPM configuration. Run these 3 threads to randomly access TPM HW registers and other addresses. Host issues random TPM reads/writes to spi_device. SW polls the TPM interrupt `tpm_header_not_empty`, then read command/address and the corresponding FIFO. SW randomly updates TPM HW registers. Ensure all the data is correct in the scoreboard.
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering spi_device_flash_all	Randomize command opcode. Configure unused CMD_INFO reg with new opcode and set it to valid. Check opcode, address and payload are passing through. Configure filter bit corresponding to opcode to 1. Check the entire command is filtered. Set filter bit back to 0. Check opcode and address are passing through again. Invalid opcode is also filtered
V2	pass_addr_translation	spi_device_pass_addr_payload_swap spi_device_flash_all	Randomize command opcode. Configure unused CMD_INFO reg with new opcode and set it to valid. Enable address translation for given command. Configure address translation bits. Check proper address translation is applied. Disable address translation for given command. Check address is now passing unchanged.
V2	pass_payload_translation	spi_device_pass_addr_payload_swap spi_device_flash_all	Configure program or write_status command. Enable payload translation for given command. Configure payload translation bits. Check proper payload translation is applied. Disable payload translation for given command. Check payload is now passing unchanged.
V2	cmd_info_slots	spi_device_flash_all	Configure first 5 slots according to required configuration. Configure next 6 slots for read commands Randomize configuration of the remaining 13 cmd info slots. Issue commands with various opcodes enabled in info slots. Check proper command propagation. Disable some cmd info slots. Check no propagation of disabled commands.
V2	cmd_read_status	spi_device_intercept spi_device_flash_all	Configure proper read status command info slot. Issue read status command. Check propagation of read status command. Initiate response to the read status. Check proper reception of response.
V2	cmd_read_jedec	spi_device_intercept spi_device_flash_all	Configure proper read jedec command info slot. Issue read jedec command. Check propagation of read jedec command. Initiate response to the read jedec. Check proper reception of response.
V2	cmd_read_sfdp	spi_device_intercept spi_device_flash_all	Configure proper read sfdp command info slot. Issue read sfdp command. Check propagation of read sfdp command. Initiate response to the read sfdp. Check proper reception of response.
V2	cmd_fast_read	spi_device_intercept spi_device_flash_all	Configure proper fast read command info slot. Issue fast read command. Check propagation of fast read command. Initiate response to the fast read. Check proper reception of response.
V2	flash_cmd_upload	spi_device_upload	Configure spi_device on flash or passthrough mode. Configure cmd info slots. Set upload to 1 for some of 13 non fixed cmd info slots. Host should poll busy field status to check if command is done. Issue next command upload and poll busy status again.
V2	mailbox_command	spi_device_mailbox	Configure cmd info slots. Issue one of predefined read command targeting mailbox space. Check response to read command. Check if command is processed internally.
V2	mailbox_cross_outside_command	spi_device_mailbox	Configure spi_device on passthrough mode. Mailbox boundary crossing is not expected to be used on flash mode, so that testing this on flash mode isn't needed. Configure cmd info slots. Issue one of predefined read command targeting mailbox space. Command should start inside mailbox space and cross into read space. When the address falls in the mailbox region, data returns from the mailbox. when the address is outside the mailbox, data returns as follows returns high-z if the read command is filtered. returns from downstream port if read command is passed through.
V2	mailbox_cross_inside_command	spi_device_mailbox	Similar to `mailbox_cross_outside_command`, except that start address is inside the mailbox.
V2	cmd_read_buffer	spi_device_flash_mode spi_device_read_buffer_direct	Configure device in flash mode. Issue read commands. Create another parallel thread that SW updates read buffer contents after a watermark or buffer flip event occurs. Check proper read data. Randomly issue read command that crosses read buffer boundary and switches back to index 0. Check correctness of `last_read_addr`, `readbuf_watermark` and `readbuf_flip`.
V2	cmd_dummy_cycle	spi_device_mailbox spi_device_flash_all	Configure cmd info slots. Configure dummy cycle of read commands to non default value. For single mode allowed dummy cycle is 0 or more. For dual/quad mode allowed dummy cycle is 2 or more. Check return data timing for configured commands. Check proper read data. Issue new read command that crosses read maibox boundary. Check internal buffer index bit.
V2	quad_spi	spi_device_flash_all	Configure passthrough or flash mode. Configure cmd info slots. Configure quad mode. Issue supported command. Check data on all four lines.
V2	dual_spi	spi_device_flash_all	Configure passthrough or flash mode. Configure cmd info slots. Configure dual mode. Issue supported command. Check data on both lines.
V2	4b_3b_feature	spi_device_cfg_cmd	Configure passthrough or flash mode. Configure command info slots. Configure different values for 4B/3B. Randomize configuration of EN4B and EX4B register fields. Issue supported command with required address. Check proper address propagation.
V2	write_enable_disable	spi_device_cfg_cmd	Configure passthrough or flash mode. Randomize WREN and WRDI command info slots. Issue WREN and WRDI commands along with read_status command and others. Read flash status via TL interface. Check WREN/WRDI sets/clears flash status correctly.
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	Enable TPM mode. Configure passthrough or flash mode. Issue TPM read/write interleaving with flash transactions.
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	Issue these transactions with 2 sys_clk inactive time in between. 2 tpm transactions. 2 flash transactions. a tpm transaction and a flash transaction.
V2	stress_all	spi_device_stress_all	Combine above sequences in one test to run sequentially, except csr sequences. Test modes switch among FW, flash, passthrough and tpm. Randomly add reset between each sequence
V2	alert_test	spi_device_alert_test	Verify common `alert_test` CSR that allows SW to mock-inject alert requests. Enable a random set of alert requests by writing random value to alert_test CSR. Check each `alert_tx.alert_p` pin to verify that only the requested alerts are triggered. During alert_handshakes, write `alert_test` CSR again to verify that: If `alert_test` writes to current ongoing alert handshake, the `alert_test` request will be ignored. If `alert_test` writes to current idle alert handshake, a new alert_handshake should be triggered. Wait for the alert handshakes to finish and verify `alert_tx.alert_p` pins all sets back to 0. Repeat the above steps a bunch of times.
V2	intr_test	spi_device_intr_test	Verify common intr_test CSRs that allows SW to mock-inject interrupts. Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s). Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s). Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR. Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set. Clear a random set of interrupts by writing a randomly value to intr_state CSR(s). Repeat the above steps a bunch of times.
V2	tl_d_oob_addr_access	spi_device_tl_errors	Access out of bounds address and verify correctness of response / behavior
V2	tl_d_illegal_access	spi_device_tl_errors	Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec TL-UL protocol error cases invalid opcode some mask bits not set when opcode is `PutFullData` mask does not match the transfer size, e.g. `a_address = 0x00`, `a_size = 0`, `a_mask = 'b0010` mask and address misaligned, e.g. `a_address = 0x01`, `a_mask = 'b0001` address and size aren't aligned, e.g. `a_address = 0x01`, `a_size != 0` size is greater than 2 OpenTitan defined error cases access unmapped address, expect `d_error = 1` when `devmode_i == 1` write a CSR with unaligned address, e.g. `a_address[1:0] != 0` write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte write a memory with `a_mask != '1` when it doesn't support partial accesses read a WO (write-only) memory write a RO (read-only) memory write with `instr_type = True`
V2	tl_d_outstanding_access	spi_device_csr_hw_reset spi_device_csr_rw spi_device_csr_aliasing spi_device_same_csr_outstanding	Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
V2	tl_d_partial_access	spi_device_csr_hw_reset spi_device_csr_rw spi_device_csr_aliasing spi_device_same_csr_outstanding	Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.
V2S	tl_intg_err	spi_device_tl_intg_err spi_device_sec_cm	Verify that the data integrity check violation generates an alert. Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert. Inject a fault at the onehot check in `u_reg.u_prim_reg_we_check` and verify the corresponding fatal alert occurs
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	Verify the countermeasure(s) BUS.INTEGRITY.
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset	This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Covergroups

Name	Description
all_modes_cg	Cover every combination of all possible modes: FW mode, passthrough mode and flash mode. Cover passthrough mode and flash mode with TPM mode enabled.
bit_order_clk_cfg_cg	Cover all configurations of rx/tx order in SPI_DEVICE.CFG for FW mode. Note: Flash or TPM mode always use the fixed bit order. Cover all combinations of SPI_DEVICE.CFG.CPOL and SPI_DEVICE.CFG.CPHA. Cross both bit order and clock configure.
flash_cmd_info_cg	Cover flash/passthrough mode. Cover all opcode enabled in cmd info. Cover all payload direction. Cover all address modes. Cover addr swap enable. Cover payload swap enable. Cover upload enable. Cover busy enable. Cover all dummy sizes. Cover number of payload lanes (single, dual and quad modes or no payload). cross mode, payload directions, address modes, addr/payload swap enable. cross mode, dummy sizes, number of lanes.
flash_command_while_busy_set_cg	Cover host sends flash commands while busy bit is set. Cover above with filter enabled/disabled on that command.
flash_mailbox_cg	Cover read commands targeting inside mailbox space in the flash mode.
flash_read_commands_cg	Cover read status/read JEDEC/read SFDP and all other read commands configurable in the first 10 slots. Cover dummy cycle. Cover filter enabled/disabled. Cover various payload size Cover INTERCEPT_EN. Cross all above items.
flash_status_cg	Cover all status bits toggled. Cross above with host reading status and SW reading status. Cover SW updating flash_status while CSB is active.
flash_upload_payload_size_cg	Cover supported payload sizes for IN transactions. Cover supported payload sizes for OUT transactions. Cover upload transaction payload size. Cover payload size of upload transaction exceeds 256B limit (wrap around).
fw_rx_fifo_size_cg	The same CG as `fw_tx_fifo_size_cg` for RX.
fw_tx_fifo_size_cg	Cover these values are used to configure TX fifo size for FW mode. min(1 word), typical(half of SRAM size), max(SRAM size - 1 word) Sample this when fifo is full.
passthrough_addr_swap_cg	Cover address swap on a transaction with both payload direction (read and program). Cover all bits toggled on the swap address and mask. Cross with filter enabled and disabled.
passthrough_cmd_filter_cg	Cover all possible bits for command filter. Every opcode should be enabled and filtering checked.
passthrough_mailbox_cg	Cover read commands targeting inside mailbox space. Cover command starting outside mailbox and crossing into mailbox space. Cover command starting in mailbox comming outside mailbox space. Cover command starting outside mailbox and crossing the entire mailbox space and coming outside mailbox. Cross above with filter on and off.
passthrough_payload_swap_cg	Cover payload swap on a transaction with both payload direction (read and program). Cover all bits toggled on the swap payload and mask. Cross with filter enabled and disabled.
regwen_val_when_new_value_written_cg	Cover each lockable reg field with these 2 cases: When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that. When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that. This is only applicable if the block contains regwen and locakable CSRs.
spi_device_4B_enter_exit_command_cg	Cover both EN4B and EX4B commands. Cross this with the previous `cfg_addr_4b_en` value.
spi_device_buffer_boundary_cg	Cover all the read commands. Cover buffer boundary crossing (2 buffer flips).
spi_device_write_enable_disable_cg	Cover write enable and write disable commands. Cross this with the previous flash_status.wel value.
sw_update_addr4b_cg	Cover SW updating addr4b to another value.
tl_errors_cg	Cover the following error cases on TL-UL bus: TL-UL protocol error cases. OpenTitan defined error cases, refer to testpoint `tl_d_illegal_access`.
tl_intg_err_cg	Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.
tpm_cfg_cg	Cover all combinations of these configurations in CSR `tpm_cfg`: tpm_mode, hw_reg_dis, tpm_reg_chk_dis, invalid_locality. Cover these address mode: TPM address in both valid and invalid locality. TPM address in/outside TPM address region ('hd4_xxxx). TPM offset matching to any HW return register. Both word aligned and unaligned. Cross above with TPM read and write transactions. This CG is sampled when receiving a TPM request.
tpm_interleave_with_flash_item_cg	Cover TPM transactions interleaving with flash transactions.
tpm_read_hw_reg_cg	Cover TPM read on all HW returned registered.
tpm_sts_cg	Cover `tpm_sts` read and write on an active/inactive tpm access. Cover `tpm_sts` read with HW returned and SW handled. Cross above with all locality.
tpm_transfer_size_cg	Cover both TPM read and write. Cover request HW returned and SW handled. Cross above with various payload size. min (1B), typical (4B), max (64B).