Testpoints
Stage | Name | Tests | Description |
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V1 | smoke | spi_device_smoke | Use default SRAM fifo setting. Seq:
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V1 | csr_hw_reset | spi_device_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
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V1 | csr_rw | spi_device_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
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V1 | csr_bit_bash | spi_device_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
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V1 | csr_aliasing | spi_device_csr_aliasing | Verify no aliasing within the CSR address space.
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V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
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V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw spi_device_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V1 | mem_walk | spi_device_mem_walk | Verify accessibility of all memories in the design.
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V1 | mem_partial_access | spi_device_mem_partial_access | Verify partial-accessibility of all memories in the design.
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V2 | base_random_seq | spi_device_txrx | Create 3 parallel threads
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V2 | fifo_full | spi_device_fifo_full | Increase the chance to have fifo full by following
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V2 | fifo_underflow_overflow | spi_device_fifo_underflow_overflow | Override spi_device_txrx_vseq to send SPI transfer without checking TX/RX fifo, note:
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V2 | dummy_sck_and_dummy_csb | spi_device_dummy_item_extra_dly | Drive dummy sck without csb or drive dummy csb without sck, and test no impact on the design |
V2 | extra_delay_on_spi | spi_device_dummy_item_extra_dly | Add extra delay between spi clock edge or extra delay between 2 words data This is to test host pause transfer for a while without turning off csb and then stream in data again |
V2 | tx_async_fifo_reset | spi_device_tx_async_fifo_reset | Reset TX async fifo when SPI interface is idle
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V2 | rx_async_fifo_reset | spi_device_rx_async_fifo_reset | Reset RX async fifo when SPI interface is idle
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V2 | interrupts | spi_device_intr | Test all supported interrupts:
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V2 | abort | spi_device_abort |
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V2 | byte_transfer_on_spi | spi_device_byte_transfer | send spi transfer on byte granularity, and make sure the timer never expires |
V2 | rx_timeout | spi_device_rx_timeout |
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V2 | bit_transfer_on_spi | spi_device_bit_transfer | Send spi transfer on bit granularity
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V2 | extreme_fifo_setting | spi_device_extreme_fifo_size | Set fifo size to 4 bytes(minimum), 2k-4bytes(maximum) and others |
V2 | perf | spi_device_perf | Run spi_device_fifi_full_vseq with very small delays |
V2 | csb_read | spi_device_csb_read | Read CSB value from CSR and check the correctness This feature is for debug only, so it's sufficient to verify with this direct sequence:
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V2 | mem_parity | spi_device_mem_parity | Test memory parity error pick a random mem address to inject parity errors and read it back, then check it returns d_error with all 1s data. |
V2 | mem_cfg | spi_device_ram_cfg | Test cfg_i connectivity between spi_device and prim_ram_2p. Randomly set dut.ram_cfg_i and check this value is propagated to prim_mem_2p. |
V2 | tpm_read | spi_device_tpm_rw |
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V2 | tpm_write | spi_device_tpm_rw |
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V2 | tpm_hw_reg | spi_device_tpm_sts_read spi_device_tpm_read_hw_reg |
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V2 | tpm_fully_random_case | spi_device_tpm_all |
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V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering spi_device_flash_all |
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V2 | pass_addr_translation | spi_device_pass_addr_payload_swap spi_device_flash_all |
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V2 | pass_payload_translation | spi_device_pass_addr_payload_swap spi_device_flash_all |
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V2 | cmd_info_slots | spi_device_flash_all |
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V2 | cmd_read_status | spi_device_intercept spi_device_flash_all |
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V2 | cmd_read_jedec | spi_device_intercept spi_device_flash_all |
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V2 | cmd_read_sfdp | spi_device_intercept spi_device_flash_all |
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V2 | cmd_fast_read | spi_device_intercept spi_device_flash_all |
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V2 | flash_cmd_upload | spi_device_upload |
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V2 | mailbox_command | spi_device_mailbox |
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V2 | mailbox_cross_outside_command | spi_device_mailbox |
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V2 | mailbox_cross_inside_command | spi_device_mailbox |
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V2 | cmd_read_buffer | spi_device_flash_mode spi_device_read_buffer_direct |
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V2 | cmd_dummy_cycle | spi_device_mailbox spi_device_flash_all |
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V2 | quad_spi | spi_device_flash_all |
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V2 | dual_spi | spi_device_flash_all |
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V2 | 4b_3b_feature | spi_device_cfg_cmd |
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V2 | write_enable_disable | spi_device_cfg_cmd |
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V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm |
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V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | Issue these transactions with 2 sys_clk inactive time in between.
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V2 | stress_all | spi_device_stress_all |
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V2 | alert_test | spi_device_alert_test | Verify common
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V2 | intr_test | spi_device_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
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V2 | tl_d_oob_addr_access | spi_device_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | spi_device_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec
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V2 | tl_d_outstanding_access | spi_device_csr_hw_reset spi_device_csr_rw spi_device_csr_aliasing spi_device_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | spi_device_csr_hw_reset spi_device_csr_rw spi_device_csr_aliasing spi_device_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | spi_device_tl_intg_err spi_device_sec_cm | Verify that the data integrity check violation generates an alert.
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V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | Verify the countermeasure(s) BUS.INTEGRITY. |
V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers. |
Covergroups
Name | Description |
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all_modes_cg | Cover every combination of all possible modes:
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bit_order_clk_cfg_cg | Cover all configurations of rx/tx order in SPI_DEVICE.CFG for FW mode. Note: Flash or TPM mode always use the fixed bit order. Cover all combinations of SPI_DEVICE.CFG.CPOL and SPI_DEVICE.CFG.CPHA. Cross both bit order and clock configure. |
flash_cmd_info_cg | Cover flash/passthrough mode. Cover all opcode enabled in cmd info. Cover all payload direction. Cover all address modes. Cover addr swap enable. Cover payload swap enable. Cover upload enable. Cover busy enable. Cover all dummy sizes. Cover number of payload lanes (single, dual and quad modes or no payload). cross mode, payload directions, address modes, addr/payload swap enable. cross mode, dummy sizes, number of lanes. |
flash_command_while_busy_set_cg | Cover host sends flash commands while busy bit is set. Cover above with filter enabled/disabled on that command. |
flash_mailbox_cg | Cover read commands targeting inside mailbox space in the flash mode. |
flash_read_commands_cg | Cover read status/read JEDEC/read SFDP and all other read commands configurable in the first 10 slots. Cover dummy cycle. Cover filter enabled/disabled. Cover various payload size Cover INTERCEPT_EN. Cross all above items. |
flash_status_cg | Cover all status bits toggled. Cross above with host reading status and SW reading status. Cover SW updating flash_status while CSB is active. |
flash_upload_payload_size_cg | Cover supported payload sizes for IN transactions. Cover supported payload sizes for OUT transactions. Cover upload transaction payload size. Cover payload size of upload transaction exceeds 256B limit (wrap around). |
fw_rx_fifo_size_cg | The same CG as |
fw_tx_fifo_size_cg | Cover these values are used to configure TX fifo size for FW mode.
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passthrough_addr_swap_cg | Cover address swap on a transaction with both payload direction (read and program). Cover all bits toggled on the swap address and mask. Cross with filter enabled and disabled. |
passthrough_cmd_filter_cg | Cover all possible bits for command filter. Every opcode should be enabled and filtering checked. |
passthrough_mailbox_cg | Cover read commands targeting inside mailbox space. Cover command starting outside mailbox and crossing into mailbox space. Cover command starting in mailbox comming outside mailbox space. Cover command starting outside mailbox and crossing the entire mailbox space and coming outside mailbox. Cross above with filter on and off. |
passthrough_payload_swap_cg | Cover payload swap on a transaction with both payload direction (read and program). Cover all bits toggled on the swap payload and mask. Cross with filter enabled and disabled. |
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
spi_device_4B_enter_exit_command_cg | Cover both EN4B and EX4B commands.
Cross this with the previous |
spi_device_buffer_boundary_cg | Cover all the read commands. Cover buffer boundary crossing (2 buffer flips). |
spi_device_write_enable_disable_cg | Cover write enable and write disable commands. Cross this with the previous flash_status.wel value. |
sw_update_addr4b_cg | Cover SW updating addr4b to another value. |
tl_errors_cg | Cover the following error cases on TL-UL bus:
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tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |
tpm_cfg_cg | Cover all combinations of these configurations in CSR
This CG is sampled when receiving a TPM request. |
tpm_interleave_with_flash_item_cg | Cover TPM transactions interleaving with flash transactions. |
tpm_read_hw_reg_cg | Cover TPM read on all HW returned registered. |
tpm_sts_cg | Cover |
tpm_transfer_size_cg | Cover both TPM read and write. Cover request HW returned and SW handled. Cross above with various payload size.
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