Registers

Summary of the core interface’s registers

INTR_STATE

Interrupt State Register

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0x7

Fields

{"reg": [{"name": "mbx_ready", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "mbx_abort", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "mbx_error", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

INTR_ENABLE

Interrupt Enable Register

• Offset: 0x4
• Reset default: 0x0
• Reset mask: 0x7

Fields

{"reg": [{"name": "mbx_ready", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "mbx_abort", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "mbx_error", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

INTR_TEST

Interrupt Test Register

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0x7

Fields

{"reg": [{"name": "mbx_ready", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "mbx_abort", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "mbx_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

ALERT_TEST

Alert Test Register

• Offset: 0xc
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "recov_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

CONTROL

DOE mailbox control register visible to OpenTitan

• Offset: 0x10
• Reset default: 0x0
• Reset mask: 0xb

Fields

{"reg": [{"name": "abort", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "error", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "sys_async_msg", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

STATUS

DOE mailbox status register visible to OpenTitan

• Offset: 0x14
• Reset default: 0x1
• Reset mask: 0xf

Fields

{"reg": [{"name": "busy", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "sys_intr_state", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "sys_intr_enable", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "sys_async_enable", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}

ADDRESS_RANGE_REGWEN

Used to lock the inbound/outbound base/limit configuration registers.

• Offset: 0x18
• Reset default: 0x6
• Reset mask: 0xf

Fields

{"reg": [{"name": "regwen", "bits": 4, "attr": ["rw0c"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ADDRESS_RANGE_VALID

Used to mark the inbound/outbound base/limit configuration registers to have a valid configuration.

• Offset: 0x1c
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "range_valid", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

INBOUND_BASE_ADDRESS

Base address of SRAM region, which is used to back up the inbound mailbox data. This address is 4-byte aligned, the lower 2 bits are ignored.

• Offset: 0x20
• Reset default: 0x0
• Reset mask: 0xfffffffc
• Register enable: ADDRESS_RANGE_REGWEN

Fields

{"reg": [{"bits": 2}, {"name": "base_address", "bits": 30, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INBOUND_LIMIT_ADDRESS

Inclusive end address of the inbound mailbox memory range in the private SRAM. This address is 4-byte aligned and it specifies the start address of the final valid DWORD location. The lower 2 bits are ignored.

• Offset: 0x24
• Reset default: 0x0
• Reset mask: 0xfffffffc
• Register enable: ADDRESS_RANGE_REGWEN

Fields

{"reg": [{"bits": 2}, {"name": "limit", "bits": 30, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INBOUND_WRITE_PTR

Write pointer for the next inbound data write. This pointer is 4-byte aligned, the lower 2 bits are always zero.

• Offset: 0x28
• Reset default: 0x0
• Reset mask: 0xfffffffc

Fields

{"reg": [{"bits": 2}, {"name": "inbound_read_ptr", "bits": 30, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

OUTBOUND_BASE_ADDRESS

Base address of SRAM region, which is used to buffer the outbound mailbox data. This address is 4-byte aligned, the lower 2 bits are ignored.

• Offset: 0x2c
• Reset default: 0x0
• Reset mask: 0xfffffffc
• Register enable: ADDRESS_RANGE_REGWEN

Fields

{"reg": [{"bits": 2}, {"name": "base_address", "bits": 30, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

OUTBOUND_LIMIT_ADDRESS

Inclusive end address of the outbound mailbox memory range in the private SRAM. This address is 4-byte aligned and it specifies the start address of the final valid DWORD location. The lower 2 bits are ignored.

• Offset: 0x30
• Reset default: 0x0
• Reset mask: 0xfffffffc
• Register enable: ADDRESS_RANGE_REGWEN

Fields

{"reg": [{"bits": 2}, {"name": "limit", "bits": 30, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

OUTBOUND_READ_PTR

Read pointer for the next outbound data read. This pointer is 4-byte aligned, the lower 2 bits are always zero.

• Offset: 0x34
• Reset default: 0x0
• Reset mask: 0xfffffffc

Fields

{"reg": [{"bits": 2}, {"name": "outbound_write_ptr", "bits": 30, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

OUTBOUND_OBJECT_SIZE

Indicates the size of the data object to be transferred out. Note that this size specifies the number of 4-byte words (DWORD). Maximum size supported by any OT DOE instance is 1K DWORDS.

• Offset: 0x38
• Reset default: 0x0
• Reset mask: 0x7ff

Fields

{"reg": [{"name": "cnt", "bits": 11, "attr": ["rw"], "rotate": 0}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DOE_INTR_MSG_ADDR

Software read-only alias of the DOE_INTR_MSG_ADDR register of the SoC interface for convenient access of the OT firmware. Defined only for FW-to-FW mailboxes.

• Offset: 0x3c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "doe_intr_msg_addr", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DOE_INTR_MSG_DATA

Software read-only alias of the DOE_INTR_MSG_DATA register of the SoC interface for convenient access of the OT firmware. Defined only for FW-to-FW mailboxes.

• Offset: 0x40
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "doe_intr_msg_data", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

Summary of the soc interface’s registers

SOC_CONTROL

DOE mailbox control register.

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0x8000000b

Fields

{"reg": [{"name": "abort", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "doe_intr_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "doe_async_msg_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}, {"name": "go", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}

SOC_STATUS

DOE mailbox status register

• Offset: 0xc
• Reset default: 0x1
• Reset mask: 0x8000000f

Fields

{"reg": [{"name": "busy", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "doe_intr_status", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "error", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "doe_async_msg_status", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 27}, {"name": "ready", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

SOC_STATUS . ready

When Set, this bit indicates the DOE instance has a data object available to be read by SoC firmware/software. The transition of this bit from Clear to Set is an interrupt triggering event.

SOC_STATUS . doe_async_msg_status

This bit, when Set, indicates the DOE instance has one or more asynchronous messages to transfer. The transition of this bit from Clear to Set is an interrupt triggering event.This bit is set when an interrupt event occurs.

SOC_STATUS . error

When Set, this bit indicates that there has been an internal error associated with data object received, or that a data object has been received for which the DOE instance is unable to provide a response. The transition of this bit from Clear to Set is an interrupt triggering event.

SOC_STATUS . doe_intr_status

This bit is set when an interrupt event occurs.

SOC_STATUS . busy

When Set, this bit indicates the DOE instance is temporarily unable to receive a new data object through the DOE Write Data Mailbox register.

WDATA

DOE mailbox write data register. The DOE instance receives data objects via writes to this register. A successful write adds one DWORD to the data object being assembled in the DOE instance. A write of 1 to the DOE Go bit in the DOE Control Register marks the completion of the data transfer, i.e, final DWORD for the object has been written.

• Word Aligned Offset Range: 0x10to0x10
• Size (words): 1
• Access: wo
• Byte writes are not supported.

RDATA

DOE mailbox read data register If the Data Object Ready bit is Set, a read of this register returns the current DW of the data object. A write of any value to this register indicates a successful read of the current DWORD. The next read to this register shall return to the next DW from the data object being read

• Word Aligned Offset Range: 0x14to0x14
• Size (words): 1
• Access: rw
• Byte writes are not supported.

SOC_DOE_INTR_MSG_ADDR

Utilized by the mailbox responder to send an interrupt message to the requester via a write to the configured address. Defined only for FW-to-FW mailboxes.

• Offset: 0x18
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "doe_intr_msg_addr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

SOC_DOE_INTR_MSG_DATA

Interrupt message data to be sent to the address configured in the DOE_INTR_MSG_ADDR register. Defined only for FW-to-FW mailboxes.

• Offset: 0x1c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "doe_intr_msg_data", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}