RV_DM Checklist

This checklist is for Hardware Stage transitions for the RV_DM peripheral. All checklist items refer to the content in the Checklist.

Design Checklist

D1

TypeItemResolutionNote/Collaterals
DocumentationSPEC_COMPLETEDoneRV_DM Design Spec
DocumentationCSR_DEFINEDDone
RTLCLKRST_CONNECTEDDone
RTLIP_TOPDone
RTLIP_INSTANTIABLEDone
RTLPHYSICAL_MACROS_DEFINED_80N/ADebug ROM implemented using sea of gates
RTLFUNC_IMPLEMENTEDDone
RTLASSERT_KNOWN_ADDEDDone
Code QualityLINT_SETUPDone

D2

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURESDone
DocumentationBLOCK_DIAGRAMDoneAvailable in external PULP RISC-V Debug System Documentation
DocumentationDOC_INTERFACEDone
DocumentationDOC_INTERFACEDone
DocumentationDOC_INTEGRATION_GUIDEWaivedThis checklist item has been added retrospectively.
DocumentationMISSING_FUNCDone
DocumentationFEATURE_FROZENDone
RTLFEATURE_COMPLETEDone
RTLPORT_FROZENDone
RTLARCHITECTURE_FROZENDone
RTLREVIEW_TODODone
RTLSTYLE_XWaivedWaiving as RTL is from a third-party
RTLCDC_SYNCMACRODone
Code QualityLINT_PASSDone
Code QualityCDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityRDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityAREA_CHECKDone
Code QualityTIMING_CHECKDone
SecuritySEC_CM_DOCUMENTEDN/A

D2S

TypeItemResolutionNote/Collaterals
SecuritySEC_CM_ASSETS_LISTEDDone
SecuritySEC_CM_IMPLEMENTEDDone
SecuritySEC_CM_RND_CNSTN/A
SecuritySEC_CM_NON_RESET_FLOPSDone
SecuritySEC_CM_SHADOW_REGSDone
SecuritySEC_CM_RTL_REVIEWEDDone
SecuritySEC_CM_COUNCIL_REVIEWEDDone

D3

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURES_D3Not Started
RTLTODO_COMPLETENot Started
Code QualityLINT_COMPLETENot Started
Code QualityCDC_COMPLETENot Started
Code QualityRDC_COMPLETENot Started
ReviewREVIEW_RTLNot Started
ReviewREVIEW_DELETED_FFNot Started
ReviewREVIEW_SW_CHANGENot Started
ReviewREVIEW_SW_ERRATANot Started
ReviewReviewer(s)Not Started
ReviewSignoff dateNot Started

Verification Checklist

V1

TypeItemResolutionNote/Collaterals
DocumentationDV_DOC_DRAFT_COMPLETEDDoneRV_DM DV document
DocumentationTESTPLAN_COMPLETEDDoneRV_DM Testplan
TestbenchTB_TOP_CREATEDDone
TestbenchPRELIMINARY_ASSERTION_CHECKS_ADDEDDone
TestbenchSIM_TB_ENV_CREATEDDone
TestbenchSIM_RAL_MODEL_GEN_AUTOMATEDDoneDone for both, regs and debug mem RAL. JTAG DTM and DMI RAL models are hand-written.
TestbenchCSR_CHECK_GEN_AUTOMATEDDoneDone for both, regs and debug mem RAL.
TestbenchTB_GEN_AUTOMATEDN.A.Design is not parameterized into multiple variants.
TestsSIM_SMOKE_TEST_PASSINGDone
TestsSIM_CSR_MEM_TEST_SUITE_PASSINGDoneCSR tests run on all 4 RAL models.
TestsFPV_MAIN_ASSERTIONS_PROVENN.A.
Tool SetupSIM_ALT_TOOL_SETUPDonePrimary: VCS, Alt: Xcelium
RegressionSIM_SMOKE_REGRESSION_SETUPDone
RegressionSIM_NIGHTLY_REGRESSION_SETUPDone
RegressionFPV_REGRESSION_SETUPN.A.
CoverageSIM_COVERAGE_MODEL_ADDEDDone
Code QualityTB_LINT_SETUPDone
IntegrationPRE_VERIFIED_SUB_MODULES_V1DoneStandard pre-verified sub-modules. Third party PULP DM modules will be fully coverage-closed.
ReviewDESIGN_SPEC_REVIEWEDDone
ReviewTESTPLAN_REVIEWEDDone
ReviewSTD_TEST_CATEGORIES_PLANNEDDoneSecurity, debug, stress, error test cases planned.
ReviewV2_CHECKLIST_SCOPEDDone

V2

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V2Not Started
DocumentationDV_DOC_COMPLETEDNot Started
TestbenchFUNCTIONAL_COVERAGE_IMPLEMENTEDNot Started
TestbenchALL_INTERFACES_EXERCISEDNot Started
TestbenchALL_ASSERTION_CHECKS_ADDEDNot Started
TestbenchSIM_TB_ENV_COMPLETEDNot Started
TestsSIM_ALL_TESTS_PASSINGNot Started
TestsFPV_ALL_ASSERTIONS_WRITTENNot Started
TestsFPV_ALL_ASSUMPTIONS_REVIEWEDNot Started
TestsSIM_FW_SIMULATEDNot Started
RegressionSIM_NIGHTLY_REGRESSION_V2Not Started
CoverageSIM_CODE_COVERAGE_V2Not Started
CoverageSIM_FUNCTIONAL_COVERAGE_V2Not Started
CoverageFPV_CODE_COVERAGE_V2Not Started
CoverageFPV_COI_COVERAGE_V2Not Started
IntegrationPRE_VERIFIED_SUB_MODULES_V2Not Started
IssuesNO_HIGH_PRIORITY_ISSUES_PENDINGNot Started
IssuesALL_LOW_PRIORITY_ISSUES_ROOT_CAUSEDNot Started
ReviewDV_DOC_TESTPLAN_REVIEWEDNot Started
ReviewV3_CHECKLIST_SCOPEDNot Started

V2S

TypeItemResolutionNote/Collaterals
DocumentationSEC_CM_TESTPLAN_COMPLETEDNot Started
TestsFPV_SEC_CM_VERIFIEDNot Started
TestsSIM_SEC_CM_VERIFIEDNot Started
CoverageSIM_COVERAGE_REVIEWEDNot Started
ReviewSEC_CM_DV_REVIEWEDNot Started

V3

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V3Not Started
TestsX_PROP_ANALYSIS_COMPLETEDNot Started
TestsFPV_ASSERTIONS_PROVEN_AT_V3Not Started
RegressionSIM_NIGHTLY_REGRESSION_AT_V3Not Started
CoverageSIM_CODE_COVERAGE_AT_100Not Started
CoverageSIM_FUNCTIONAL_COVERAGE_AT_100Not Started
CoverageFPV_CODE_COVERAGE_AT_100Not Started
CoverageFPV_COI_COVERAGE_AT_100Not Started
Code QualityALL_TODOS_RESOLVEDNot Started
Code QualityNO_TOOL_WARNINGS_THROWNNot Started
Code QualityTB_LINT_COMPLETENot Started
IntegrationPRE_VERIFIED_SUB_MODULES_V3Not Started
IssuesNO_ISSUES_PENDINGNot Started
ReviewReviewer(s)Not Started
ReviewSignoff dateNot Started