V1 | random | rv_timer_random | RV_TIMER random test performs following steps for number of iterations
- Program zero to CTRL.active* Register(deactivate timer)
- Program random legal values in CFG*, TIMER_V_, COMPARE_, INTR_ENABLE*
- Program one to CTRL.active* (activate timer)
- Wait for number of cycles to have mTime>= mTimeCmp
- Check Interrupt state register and Interrupt signal (scoreboard logic)
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V1 | csr_hw_reset | rv_timer_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
- Write all CSRs with a random value.
- Apply reset to the DUT as well as the RAL model.
- Read each CSR and compare it against the reset value.
it is mandatory to replicate this test for each reset that affects
all or a subset of the CSRs.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
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V1 | csr_rw | rv_timer_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
- Loop through each CSR to write it with a random value.
- Read the CSR back and check for correctness while adhering to its
access policies.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
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V1 | csr_bit_bash | rv_timer_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
- Walk a 1 through each CSR by flipping 1 bit at a time.
- Read the CSR back and check for correctness while adhering to its
access policies.
- This verify that writing a specific bit within the CSR did not affect
any of the other bits.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
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V1 | csr_aliasing | rv_timer_csr_aliasing | Verify no aliasing within the CSR address space.
- Loop through each CSR to write it with a random value
- Shuffle and read ALL CSRs back.
- All CSRs except for the one that was written in this iteration should
read back the previous value.
- The CSR that was written in this iteration is checked for correctness
while adhering to its access policies.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
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V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
- Run csr_rw sequence to randomly access CSRs
- If memory exists, run mem_partial_access in parallel with csr_rw
- Randomly issue reset and then use hw_reset sequence to check all CSRs
are reset to default value
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
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V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw
rv_timer_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
- Randomly access all CSRs
- Test when regwen CSR is set, its corresponding lockable CSRs become
read-only registers
Note:
- If regwen CSR is HW read-only, this feature can be fully tested by common
CSR tests - csr_rw and csr_aliasing.
- If regwen CSR is HW updated, a separate test should be created to test it.
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | random_reset | rv_timer_random_reset | This test is to exercise on the fly reset(timer is active)
- Assert reset randomly in the middle of random test steps
- Scoreboard check for all register go back to reset value
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V2 | disabled | rv_timer_disabled | This test to verify no activity in mTime, Interrupt Status, Interrupt signal,
When all timers are deactive (ctrl.active = 0).
- Program 1 in interrupt enable and 0 in control register and random value for
rest of the registers
- Scoreboard check for no activity and no interrupt whatever is setting
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V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | This test will verify update timer configuration on running timer.
- Program timer.Active to zero
- Program random values in interrrupt enable, prescaler, step, mtime and mtime cmp
- After some clocks update timer config values
- Check for interrupt as per new config set
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V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | This test will update timer value and compare value just before timer is going to
expire (multiple times) and verify no interrupt is asserted
- Program timer.Active to zero
- Program random values in interrrupt enable, prescaler, step, mtime and mtime cmp
- Update timer config values just before timer is about to expire
- Check for no interrupt set
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V2 | stress | rv_timer_stress_all | Do combinations of multiple of above scenarios to get multiple interrupts
asserted at the same time. Scoreboard should be robust enough to deal with all
scenarios. |
V2 | intr_test | rv_timer_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
- Enable a random set of interrupts by writing random value(s) to
intr_enable CSR(s).
- Randomly "turn on" interrupts by writing random value(s) to intr_test
CSR(s).
- Read all intr_state CSR(s) back to verify that it reflects the same value
as what was written to the corresponding intr_test CSR.
- Check the cfg.intr_vif pins to verify that only the interrupts that were
enabled and turned on are set.
- Clear a random set of interrupts by writing a randomly value to intr_state
CSR(s).
- Repeat the above steps a bunch of times.
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V2 | tl_d_oob_addr_access | rv_timer_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | rv_timer_tl_errors | Drive unsupported requests via TL interface and verify correctness of response
/ behavior. Below error cases are tested bases on the
TLUL spec
- TL-UL protocol error cases
- invalid opcode
- some mask bits not set when opcode is
PutFullData
- mask does not match the transfer size, e.g.
a_address = 0x00 , a_size = 0 ,
a_mask = 'b0010
- mask and address misaligned, e.g.
a_address = 0x01 , a_mask = 'b0001
- address and size aren't aligned, e.g.
a_address = 0x01 , a_size != 0
- size is greater than 2
- OpenTitan defined error cases
- access unmapped address, expect
d_error = 1 when devmode_i == 1
- write a CSR with unaligned address, e.g.
a_address[1:0] != 0
- write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
- write a memory with
a_mask != '1 when it doesn't support partial accesses
- read a WO (write-only) memory
- write a RO (read-only) memory
- write with
instr_type = True
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V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset
rv_timer_csr_rw
rv_timer_csr_aliasing
rv_timer_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one
transaction outstanding within the TL device. Also, verify one outstanding when back-
to-back accesses are made to the same address. |
V2 | tl_d_partial_access | rv_timer_csr_hw_reset
rv_timer_csr_rw
rv_timer_csr_aliasing
rv_timer_same_csr_outstanding | Access CSR with one or more bytes of data.
For read, expect to return all word value of the CSR.
For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | rv_timer_tl_intg_err
rv_timer_sec_cm | Verify that the data integrity check violation generates an alert.
- Randomly inject errors on the control, data, or the ECC bits during CSR accesses.
Verify that triggers the correct fatal alert.
- Inject a fault at the onehot check in
u_reg.u_prim_reg_we_check and verify the
corresponding fatal alert occurs
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V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | Verify the countermeasure(s) BUS.INTEGRITY. |
V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset.
After reset is asserted, the test will read and check all valid CSR registers. |