// Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 { name: “rv_timer” import_testplans: [“hw/dv/tools/dvsim/testplans/csr_testplan.hjson”, “hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson”, “hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson”, “hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson”, “hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson”, “rv_timer_sec_cm_testplan.hjson”] testpoints: [ { name: random desc: ‘’‘RV_TIMER random test performs following steps for number of iterations - Program zero to CTRL.active* Register(deactivate timer) - Program random legal values in CFG*, TIMER_V_, COMPARE_, INTR_ENABLE* - Program one to CTRL.active* (activate timer) - Wait for number of cycles to have mTime>= mTimeCmp - Check Interrupt state register and Interrupt signal (scoreboard logic)’‘’ stage: V1 tests: [“rv_timer_random”] } { name: random_reset desc: ‘’‘This test is to exercise on the fly reset(timer is active) - Assert reset randomly in the middle of random test steps - Scoreboard check for all register go back to reset value’‘’ stage: V2 tests: [“rv_timer_random_reset”] } { name: disabled desc: ‘’‘This test to verify no activity in mTime, Interrupt Status, Interrupt signal, When all timers are deactivated (ctrl.active = 0). - Program 1 in interrupt enable and 0 in control register and random value for rest of the registers - Scoreboard check for no activity and no interrupt whatever is setting’‘’ stage: V2 tests: [“rv_timer_disabled”] } { name: cfg_update_on_fly desc: ‘’‘This test will verify update timer configuration on running timer. - Program timer.Active to zero - Program random values in interrupt enable, prescaler, step, mtime and mtime cmp - After some clocks update timer config values - Check for interrupt as per new config set’‘’ stage: V2 tests: [“rv_timer_cfg_update_on_fly”] } { name: no_interrupt_test desc: ‘’‘This test will update timer value and compare value just before timer is going to expire (multiple times) and verify no interrupt is asserted - Program timer.Active to zero - Program random values in interrupt enable, prescaler, step, mtime and mtime cmp - Update timer config values just before timer is about to expire - Check for no interrupt set’‘’ stage: V2 tests: [“rv_timer_cfg_update_on_fly”] } { name: min_value desc: ‘’‘This test configures the prescaler and mtime to 0. The step is randomised between 0 and 1 to allow the counter to increase sometimes. The register timecmp is randomised to be set up to 5, so some seeds trigger an interrupt directly on configuration if timecmp=0. While others force mtime to increase. This test helps close functional coverage by hitting the minimum values for step, prescaler, mtime and mtimecmp’‘’ stage: V3 tests: [“rv_timer_min”] } { name: max_value desc: ‘’‘This test configures the prescaler, step and mtimecm to the maximum value. The counter is randomised to be up to 5 units lower than the timecmp. By doing this, some seeds trigger an interrupt directly on configuration if timecmp=mtime. While others force mtime to increase. This test helps close functional coverage by hitting the maximum values for step, prescaler, mtime and mtimecmp’‘’ stage: V3 tests: [“rv_timer_max”] } { name: stress desc: ‘’‘Do combinations of multiple of above scenarios to get multiple interrupts asserted at the same time. Scoreboard should be robust enough to deal with all scenarios.’‘’ stage: V2 tests: [“rv_timer_stress_all”] } ] }