Registers

Summary

INTR_STATE

Interrupt State Register

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "gpio", "bits": 32, "attr": ["rw1c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_ENABLE

Interrupt Enable Register

• Offset: 0x4
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "gpio", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_TEST

Interrupt Test Register

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "gpio", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ALERT_TEST

Alert Test Register

• Offset: 0xc
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

DATA_IN

GPIO Input data read value

• Offset: 0x10
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "DATA_IN", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DIRECT_OUT

GPIO direct output data write value

• Offset: 0x14
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "DIRECT_OUT", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MASKED_OUT_LOWER

GPIO write data lower with mask.

Masked write for DATA_OUT[15:0].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OUT[15:0] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OUT[15:0].

• Offset: 0x18
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MASKED_OUT_UPPER

GPIO write data upper with mask.

Masked write for DATA_OUT[31:16].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OUT[31:16] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OUT[31:16].

• Offset: 0x1c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DIRECT_OE

GPIO Output Enable.

Setting direct_oe[i] to 1 enables output mode for GPIO[i]

• Offset: 0x20
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "DIRECT_OE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MASKED_OE_LOWER

GPIO write Output Enable lower with mask.

Masked write for DATA_OE[15:0], the register that controls output mode for GPIO pins [15:0].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OE[15:0] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OE[15:0].

• Offset: 0x24
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MASKED_OE_UPPER

GPIO write Output Enable upper with mask.

Masked write for DATA_OE[31:16], the register that controls output mode for GPIO pins [31:16].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OE[31:16] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OE[31:16].

• Offset: 0x28
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_CTRL_EN_RISING

GPIO interrupt enable for GPIO, rising edge.

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_RISING[i] enables rising-edge interrupt detection on GPIO[i].

• Offset: 0x2c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "INTR_CTRL_EN_RISING", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_CTRL_EN_FALLING

GPIO interrupt enable for GPIO, falling edge.

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_FALLING[i] enables falling-edge interrupt detection on GPIO[i].

• Offset: 0x30
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "INTR_CTRL_EN_FALLING", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_CTRL_EN_LVLHIGH

GPIO interrupt enable for GPIO, level high.

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_LVLHIGH[i] enables level high interrupt detection on GPIO[i].

• Offset: 0x34
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "INTR_CTRL_EN_LVLHIGH", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_CTRL_EN_LVLLOW

GPIO interrupt enable for GPIO, level low.

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_LVLLOW[i] enables level low interrupt detection on GPIO[i].

• Offset: 0x38
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "INTR_CTRL_EN_LVLLOW", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CTRL_EN_INPUT_FILTER

filter enable for GPIO input bits.

If CTRL_EN_INPUT_FILTER[i] is true, a value of input bit [i] must be stable for 16 cycles before transitioning.

• Offset: 0x3c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "CTRL_EN_INPUT_FILTER", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

HW_STRAPS_DATA_IN_VALID

Indicates whether the data in HW_STRAPS_DATA_IN is valid.

• Offset: 0x40
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "HW_STRAPS_DATA_IN_VALID", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}

HW_STRAPS_DATA_IN

GPIO input data that was sampled as straps at most once after the block came out of reset.

The behavior of this register depends on the GpioAsHwStrapsEn parameter.

• If the parameter is false then the register reads as zero.
• If the parameter is true then GPIO input data is sampled after reset on the first cycle where the strap_en_i input is high. The sampled data is then stored in this register.
• Offset: 0x44
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "HW_STRAPS_DATA_IN", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INP_PRD_CNT_CTRL

Control register of one input period counter.

• Reset default: 0x4
• Reset mask: 0xffff07

Instances

Fields

{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "continuous_mode", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "polarity", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 5}, {"name": "input_select", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "prescaler", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}

INP_PRD_CNT_CTRL . prescaler

Prescaler for this input period counter. The basic idea is that the value returned in INP_PRD_CNT_VAL can be multiplied by the value of this register plus one to obtain the number of clk_i cycles between two relevant edges.

For example, assume the input pattern 00100100:

• For prescaler = 0, INP_PRD_CNT_VAL = 2
• For prescaler = 1, INP_PRD_CNT_VAL = 1

Note that, regardless of the prescaler, the input is sampled at every positive edge of clk_i. The detection of relevant edges is thus not affected by the prescaler.

This may only be changed while the enable field is zero.

INP_PRD_CNT_CTRL . input_select

Index (starting at 0) of the input that this period counter should operate on. The value must be smaller than the number of inputs (N), as only the ceil(log2(N)) least significant bits of this field are considered.

This may only be changed while the enable field is zero.

INP_PRD_CNT_CTRL . polarity

Polarity of this input period counter. If 0, falling edges of the input are relevant. If 1, rising edges of the input are relevant.

This field may only be changed while the enable field is zero.

INP_PRD_CNT_CTRL . continuous_mode

Continuously count the input period. When one measurement is completed (see description of enable field) and this field is set, all of the following apply:

• the wait for a relevant edge will immediately restart, with an internal counter of zero (while INP_PRD_CNT_VAL keeps the value of the completed measurement);
• the enable field is not cleared.

This field may only be changed while the enable field is zero.

INP_PRD_CNT_CTRL . enable

Enable this input period counter. After enabling, this counter waits for the next relevant edge (see polarity field) of the input to start counting. After that, it counts clock cycles until the next relevant edge. On that edge, the measurement is complete and the count is stored in the INP_PRD_CNT_VAL register of this input period counter. Then, if the continuous_mode field of this register is not set, the counter clears the enable field and returns to idle (see description of the continuous_mode field for what happens if that field is set).

INP_PRD_CNT_VAL

Output value of one input period counter.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "value", "bits": 32, "attr": ["rc"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INP_PRD_CNT_VAL . value

Number of clock cycles in one complete period. If this contains the value 0, no complete period has been measured since the last time this register got cleared. The minimum number of clock cycles in one complete period is 1, which is returned when the input inverts for one clock cycle and then inverts again.

Expected values for some example patterns:

• 01010101 -> 1
• 00100100 -> 2
• 00010001 -> 3

The counter saturates at the maximum value.

This register gets cleared after every read from SW.