OpenTitan Documentation

Verify that sending an instantiate command via the SW path returns OK. Instantiate the CSRNG with flag0 set to true and clen set to 12. Verify that sending a generate command via the SW path returns glen=1 number of words followed by an OK.

Verify the reset values as indicated in the RAL specification.

• Write all CSRs with a random value.
• Apply reset to the DUT as well as the RAL model.
• Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify accessibility of CSRs as indicated in the RAL specification.

• Loop through each CSR to write it with a random value.
• Read the CSR back and check for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within individual bits of a CSR.

• Walk a 1 through each CSR by flipping 1 bit at a time.
• Read the CSR back and check for correctness while adhering to its access policies.
• This verify that writing a specific bit within the CSR did not affect any of the other bits.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within the CSR address space.

• Loop through each CSR to write it with a random value
• Shuffle and read ALL CSRs back.
• All CSRs except for the one that was written in this iteration should read back the previous value.
• The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify random reset during CSR/memory access.

• Run csr_rw sequence to randomly access CSRs
• If memory exists, run mem_partial_access in parallel with csr_rw
• Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.

Verify regwen CSR and its corresponding lockable CSRs.

• Randomly access all CSRs
• Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

• If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
• If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

This test verifies the behavior of the Interrupt State Register. Verify cs_cmd_req_done interrupt asserts when glen number of genbit words have been generated. Verify cs_entropy_req interrupt asserts when instantiate or reseed is called with flag0 set to false. Verify cs_hw_inst_exc interrupt asserts when any of the application interfaces responds with a CSRNG_ERROR response status signal. Verify cs_fatal_err interrupt asserts when any bit of err_code register is set. Verify that each interrupt clears back to 0 after writing the corresponding interrupt state bit.

Verify recov_alert asserts when recov_alert_sts becomes non-zero. Verify each respective bit of recov_alert_sts asserts when:

• Either of the 3 values in the control register are not valid kMultiBitBool values.
• When an initiate or reseed command is sent where flag0 is not a valid kMultiBitBool value.
• The genbits bus value is equal to the prior valid value.
• When an illegal command is used (0x0,0x6-0xf). Verify that writing zeros to the recoverable alert status register resets all the status bits. Verify fatal_alert asserts when:
• An illegal state is reached.
• The AES block raises a fatal alert.
• There is an integrity failure on the bus (this is covered by an automated test).

Verify err_code register bits assert when:

• An error has been detected in any of the internal fifos and the corresponding write/read/state bits.
• An illegal state is reached in any of the 6 state machines.
• An error is detected in the generate command counter. Verify that the err_code register clears all bits after reset.

Verify all csrng commands req/status behave as predicted on all applications: HW0, HW1 and SW. Verify above for all valid values of acmd, clen, flags, glen. Verify for multiple hw app interfaces running in parallel. Verify sw/hw app interfaces running in parallel. Verify main_sm_state for sw/hw apps. Verify that genbits generates the amount specified by glen. Verify fips bit is set to the inverse of flag0 that was used on the last initialize or reseed. Verify that if otp_en_csrng_sw_app_read is set, genbits and int_state_value registers are readable, and unreadable otherwise. Verify that when AES_HALT is set during a generate command that no request is sent to the AES block. Verify commands with continuous/non-continuous valid. Verify that if FIPS bit drops at input from entropy source that the generated block also has FIPS low.

Verify lifecycle hardware debug mode. When lc_hw_debug_en_i is set to on, the seed from the entropy source must be xor'ed with the diversification value.

Combine the other individual testpoints while injecting TL errors and running CSR tests in parallel.

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

• Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
• Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
• Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
• Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
• Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
• Repeat the above steps a bunch of times.

Verify common alert_test CSR that allows SW to mock-inject alert requests.

• Enable a random set of alert requests by writing random value to alert_test CSR.
• Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
• During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
• Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
• Repeat the above steps a bunch of times.

Access out of bounds address and verify correctness of response / behavior

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec

• TL-UL protocol error cases
  • invalid opcode
  • some mask bits not set when opcode is PutFullData
  • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
  • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
  • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
  • size is greater than 2
• OpenTitan defined error cases
  • access unmapped address, expect d_error = 1 when devmode_i == 1
  • write a CSR with unaligned address, e.g. a_address[1:0] != 0
  • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
  • write a memory with a_mask != '1 when it doesn't support partial accesses
  • read a WO (write-only) memory
  • write a RO (read-only) memory
  • write with instr_type = True

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Verify that the data integrity check violation generates an alert.

• Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
• Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs

Verify the countermeasure(s) CONFIG.REGWEN. Verify that:

1. REGWEN cannot be set back to 1 after being set to 0 once.
2. If REGWEN is not set, the CTRL and ERR_CODE_TEST registers cannot be modified.

Verify the countermeasure(s) CONFIG.MUBI. Verify that upon writing invalid MUBI values to the CTRL register:

1. the DUT signals a recoverable alert and sets the correct bit in the RECOV_ALERT_STS register, and
2. the DUT can be configured back to a safe configuration and the RECOV_ALERT_STS register can be cleared.

Verify the countermeasure(s) INTERSIG.MUBI. Verify that unless the otp_en_csrng_sw_app_read input signal is equal to MuBi8True and CTRL.SW_APP_ENABLE or CTRL.READ_INT_STATE is set to kMultiBitBool4True the DUT doesn't allow reading the genbits or the internal state from the GENBITS or INT_STATE_VAL register, respectively.

Verify the countermeasure(s) MAIN_SM.FSM.SPARSE. The csrng_intr and csrng_err tests verify that if the FSM state is forced to an illegal state encoding 1) this is reported with a cs_fatal_err interrupt in the INTR_STATE register and 2) the corresponding bit in the ERR_CODE register is set. They currently don't check whether the DUT actually triggers a fatal alert. Alert connection and triggering are verified through automated FPV.

Verify the countermeasure(s) UPDATE.FSM.SPARSE. The csrng_intr and csrng_err tests verify that if the FSM state is forced to an illegal state encoding 1) this is reported with a cs_fatal_err interrupt in the INTR_STATE register and 2) the corresponding bit in the ERR_CODE register is set. They currently don't check whether the DUT actually triggers a fatal alert. Alert connection and triggering are verified through automated FPV.

Verify the countermeasure(s) BLK_ENC.FSM.SPARSE. The csrng_intr and csrng_err tests verify that if the FSM state is forced to an illegal state encoding 1) this is reported with a cs_fatal_err interrupt in the INTR_STATE register and 2) the corresponding bit in the ERR_CODE register is set. They currently don't check whether the DUT actually triggers a fatal alert. Alert connection and triggering are verified through automated FPV.

Verify the countermeasure(s) OUTBLK.FSM.SPARSE. The csrng_intr and csrng_err tests verify that if the FSM state is forced to an illegal state encoding 1) this is reported with a cs_fatal_err interrupt in the INTR_STATE register and 2) the corresponding bit in the ERR_CODE register is set. They currently don't check whether the DUT actually triggers a fatal alert. Alert connection and triggering are verified through automated FPV.

Verify the countermeasure(s) GEN_CMD.CTR.REDUN. The csrng_intr and csrng_err tests verify that if there is a mismatch in the redundant counters of the Generate command counter 1) this is reported with a cs_fatal_err interrupt in the INTR_STATE register and 2) the corresponding bit in the ERR_CODE register is set. They currently don't check whether the DUT actually triggers a fatal alert. Alert connection and triggering are verified through automated FPV.

Verify the countermeasure(s) DRBG_UPD.CTR.REDUN. The csrng_intr and csrng_err tests verify that if there is a mismatch in the redundant counters of the CTR_DRBG update counter 1) this is reported with a cs_fatal_err interrupt in the INTR_STATE register and 2) the corresponding bit in the ERR_CODE register is set. They currently don't check whether the DUT actually triggers a fatal alert. Alert connection and triggering are verified through automated FPV.

Verify the countermeasure(s) DRBG_GEN.CTR.REDUN. The csrng_intr and csrng_err tests verify that if there is a mismatch in the redundant counters of the CTR_DRBG generate counter 1) this is reported with a cs_fatal_err interrupt in the INTR_STATE register and 2) the corresponding bit in the ERR_CODE register is set. They currently don't check whether the DUT actually triggers a fatal alert. Alert connection and triggering are verified through automated FPV.

Verify the countermeasure(s) CTRL.MUBI. Verify that upon writing an Application Interface Command Header for an Instantiate or Reseed command to the CMD_REQ register with an invalid MUBI value in the FLAG0 field, the DUT signals a recoverable alert and sets the correct bit in the RECOV_ALERT_STS register.

Verify the countermeasure(s) MAIN_SM.CTR.LOCAL_ESC. Verify that upon a mismatch in any of the redundant counters the main FSM enters a terminal error state and that the DUT signals a fatal alert.

Verify the countermeasure(s) CONSTANTS.LC_GATED. Verify that the RndCnstCsKeymgrDivNonProduction seed diversification constant can be used if and only if the lc_hw_debug_en input signal is driven to On and that RndCnstCsKeymgrDivProduction is used otherwise.

Verify the countermeasure(s) SW_GENBITS.BUS.CONSISTENCY. Verify that if two subsequent read requests to the SW application interface obtain the same data, the DUT signals a recoverable alert and sets the correct bit in the RECOV_ALERT_STS register. Verify that the RECOV_ALERT_STS register can be cleared.

Verify the countermeasure(s) TILE_LINK.BUS.INTEGRITY.

Verify the countermeasure(s) AES_CIPHER.FSM.SPARSE. The csrng_intr and csrng_err tests verify that if the FSM state is forced to an illegal state encoding 1) this is reported with a cs_fatal_err interrupt in the INTR_STATE register and 2) the corresponding bit in the ERR_CODE register is set. They currently don't check whether the DUT actually triggers a fatal alert. Alert connection and triggering are verified through automated FPV.

Verify the countermeasure(s) AES_CIPHER.FSM.REDUN. It is ensured that upon forcing the state of any of the independent, redundant logic rails of the AES cipher core FSM to a different valid encoding, 1) this signals a fatal alert, 2) this is reported with a cs_fatal_err interrupt in the INTR_STATE register and 3) the corresponding bit in the ERR_CODE register is set.

Verify the countermeasure(s) AES_CIPHER.CTRL.SPARSE. It is ensured that upon forcing the value of an important critical control signal inside the AES cipher core to an invalid encoding, 1) this signals a fatal alert, 2) this is reported with a cs_fatal_err interrupt in the INTR_STATE register and 3) the corresponding bit in the ERR_CODE register is set.

Verify the countermeasure(s) AES_CIPHER.FSM.LOCAL_ESC. Upon detecting a local alert condition inside the AES cipher core FSM, the FSM stops processing data and locks up. The DUT must 1) signal a fatal alert, 2) report this with a cs_fatal_err interrupt in the INTR_STATE register and 3) set corresponding bit in the ERR_CODE register.

Verify the countermeasure(s) AES_CIPHER.CTR.REDUN. It is ensured that upon forcing the value of any of the independent, redundant logic rails of round counter inside the AES cipher core FSM, the FSM stops processing data and locks up. The DUT must 1) signal a fatal alert, 2) report this with a cs_fatal_err interrupt in the INTR_STATE register and 3) set corresponding bit in the ERR_CODE register.

Verify the countermeasure(s) AES_CIPHER.DATA_REG.LOCAL_ESC. SVAs inside the testbench are used to ensure that upon local escalation triggered through FI the AES cipher core doesn't release intermediate state into other CSRNG registers.

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Covers that all csrng configuration options have been tested. Individual config settings that will be covered include:

• otp_en_cs_sw_app_read
• sw_app_enable
• read_int_state
• enable
• regwen has been true and false
• intr_state has had each bit set and unset at least once (handled in comportable ip coverage) Cross:
• intr_enable and intr_state (handled in comportable ip coverage)

Covers that all csrng commands and variations have been tested for all apps. Individual commands and command options that will be covered include:

• app
• acmd, clen, flags, glen
• continuous/non-continuous valid Crosses of
• app/acmd
• acmd/clen
• acmd/flag0
• acmd/glen
• For the instantiate and reseed command:
  • flag0 false and clen 0
  • flag0 false and clen >0
  • flag0 true and clen 0
  • flag0 true and clen >0

Covers all possible fatal errors and possible AES FSM errors inside CSRNG.

Covers ERR_CODE_TEST register values for setting up fatal errors.

Covers all possible recoverable alert cases.

Covers each app's stage FIFO statuses.

• cp_hw0_cmd_depth, cp_hw1_cmd_depth, cp_sw_cmd_depth : Covers current number of commands in FIFO
• cp_hw0_genbits_depth, cp_hw1_genbits_depth, cp_sw_genbits_depth : Covers current number of genbit responses in FIFO
• cmd_depth_cross : Cross for checking each command FIFO status in different apps
• genbits_depth_cross : Cross for checking genbits FIFO status in different apps
• hw0_cmd_push_cross, hw1_cmd_push_cross, sw_cmd_push_cross : command FIFO fill status x command FIFO write valid x command FIFO write ready
• hw0_cmd_pop_cross, hw1_cmd_pop_cross, sw_cmd_pop_cross : command FIFO fill status x command FIFO read ready
• hw0_genbits_pop_cross, hw1_genbits_pop_cross, sw_genbits_pop_cross : genbits FIFO fill status x genbits FIFO read valid x genbits FIFO read ready

Covers all possible hw_exc_sts responses from each HW instance and the sub-fields of sw_cmd_sts, which are cmd_rdy and cmd_sts.

Cover each lockable reg field with these 2 cases:

• When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
• When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

Cover the following error cases on TL-UL bus:

• TL-UL protocol error cases.
• OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.