Testpoints
Stage | Name | Tests | Description |
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V1 | smoke | pattgen_smoke | Smoke test for pattgen ip in which dut is randomly programmed to generate random patterns on output channels. Stimulus:
Checking:
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V1 | csr_hw_reset | pattgen_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
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V1 | csr_rw | pattgen_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
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V1 | csr_bit_bash | pattgen_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
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V1 | csr_aliasing | pattgen_csr_aliasing | Verify no aliasing within the CSR address space.
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V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
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V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw pattgen_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | perf | pattgen_perf | Checking ip operation at min/max bandwidth Stimulus:
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V2 | cnt_rollover | cnt_rollover | Checking ip operation with random counter values Stimulus:
Checking:
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V2 | error | pattgen_error | Reset then re-start the output channel on the fly. Stimulus:
Checking:
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V2 | stress_all | pattgen_stress_all | Stress_all test is a random mix of all the test above except csr tests. |
V2 | alert_test | pattgen_alert_test | Verify common
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V2 | intr_test | pattgen_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
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V2 | tl_d_oob_addr_access | pattgen_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | pattgen_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec
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V2 | tl_d_outstanding_access | pattgen_csr_hw_reset pattgen_csr_rw pattgen_csr_aliasing pattgen_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | pattgen_csr_hw_reset pattgen_csr_rw pattgen_csr_aliasing pattgen_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | pattgen_tl_intg_err pattgen_sec_cm | Verify that the data integrity check violation generates an alert.
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V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | Verify the countermeasure(s) BUS.INTEGRITY. |
V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers. |
Covergroups
Name | Description |
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ctrl_cg | Covers that all valid enable and polarity settings for the Pattgen control register have been tested. Individual enable and polarity settings that will be covered include:
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inter_cg | intr_cg is defined in cip_base_env_cov and referenced in pattgen_scoreboard |
pattern_data_ch0_0_cg | Covers various data_0 values of the channel0 seed pattern ranges, to ensure that Pattgen can operate successfully on different pattern lengths. we will cover that an acceptable distribution of lengths has been seen, and specifically cover corner cases. The covergroup takes data from TL_UL scoreboard input |
pattern_data_ch0_1_cg | Similar to pattern_data_ch0_0_cg, except using data_1 values |
pattern_data_ch1_0_cg | Similar to pattern_data_ch0_0_cg. |
pattern_data_ch1_1_cg | Similar to pattern_data_ch0_1_cg. |
pattern_len_ch0_cg | Covers various Lengths of the channel0 seed pattern ranges, to ensure that Pattgen can operate successfully on different pattern lengths. we will cover that an acceptable distribution of lengths has been seen, and specifically cover some corner cases. |
pattern_len_ch1_cg | Similar to channel 0. |
pattern_prediv_ch0_cg | Covers various numbers of clock divide ratios of the channel0, to ensure that Pattgen can operate successfully on different clock divide ratios. we will cover that an acceptable distribution of lengths has been seen, and specifically cover corner cases. |
pattern_prediv_ch1_cg | Similar to channel 0. |
pattern_reps_ch0_cg | Covers various numbers of channel repetitions of the channel0, to ensure that Pattgen can operate successfully on different pattern lengths. we will cover that an acceptable distribution of lengths has been seen, and specifically cover all corner cases. |
pattern_reps_ch1_cg | Similar to channel 0. |
pattgen_ch0_cnt_reset_cg | Covers that ch0 counter values resets to zero when it reaches the assigned value. It includes:
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pattgen_ch1_cnt_reset_cg | Covers that ch1 counter values resets to zero when it reaches the assigned value. It includes:
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pattgen_counters_max_values_cg | Covers the initial and maximum counter values of the following:
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pattgen_op_cg | Covers the ch0 pattern generation complete interrupt and event done. Covers the ch1 pattern generation complete interrupt and event done. |
program_while_busy_cg | Program the DUT while pattern is being produced to insure current pattern is not being corrupt. |
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
tl_errors_cg | Cover the following error cases on TL-UL bus:
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tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |