Registers

Summary

Name	Offset	Length	Description
clkmgr.`ALERT_TEST`	0x0	4	Alert Test Register
clkmgr.`JITTER_REGWEN`	0x10	4	Jitter write enable
clkmgr.`JITTER_ENABLE`	0x14	4	Enable jittery clock
clkmgr.`CLK_ENABLES`	0x18	4	Clock enable for software gateable clocks.
clkmgr.`CLK_HINTS`	0x1c	4	Clock hint for software gateable transactional clocks during active mode.
clkmgr.`CLK_HINTS_STATUS`	0x20	4	Since the final state of `CLK_HINTS` is not always determined by software,
clkmgr.`MEASURE_CTRL_REGWEN`	0x24	4	Measurement control write enable
clkmgr.`IO_MEAS_CTRL_EN`	0x28	4	Enable for measurement control
clkmgr.`IO_MEAS_CTRL_SHADOWED`	0x2c	4	Configuration controls for io measurement.
clkmgr.`MAIN_MEAS_CTRL_EN`	0x30	4	Enable for measurement control
clkmgr.`MAIN_MEAS_CTRL_SHADOWED`	0x34	4	Configuration controls for main measurement.
clkmgr.`RECOV_ERR_CODE`	0x38	4	Recoverable Error code
clkmgr.`FATAL_ERR_CODE`	0x3c	4	Error code

ALERT_TEST

Alert Test Register

Offset: 0x0
Reset default: 0x0
Reset mask: 0x3

Fields

{"reg": [{"name": "recov_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

Bits	Type	Reset	Name	Description
31:2				Reserved
1	wo	0x0	fatal_fault	Write 1 to trigger one alert event of this kind.
0	wo	0x0	recov_fault	Write 1 to trigger one alert event of this kind.

JITTER_REGWEN

Jitter write enable

Offset: 0x10
Reset default: 0x1
Reset mask: 0x1

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

Bits	Type	Reset	Name	Description
31:1				Reserved
0	rw0c	0x1	EN	When 1, the value of `JITTER_ENABLE` can be changed. When 0, writes have no effect.

JITTER_ENABLE

Enable jittery clock

Offset: 0x14
Reset default: 0x9
Reset mask: 0xf
Register enable: JITTER_REGWEN

Fields

{"reg": [{"name": "VAL", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

Bits	Type	Reset	Name	Description
31:4				Reserved
3:0	rw	0x9	VAL	Enable jittery clock. A value of kMultiBitBool4False disables the jittery clock, while all other values enable jittery clock.

CLK_ENABLES

Clock enable for software gateable clocks. These clocks are directly controlled by software.

Offset: 0x18
Reset default: 0x1
Reset mask: 0x1

Fields

{"reg": [{"name": "CLK_IO_PERI_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}

Bits	Type	Reset	Name	Description
31:1				Reserved
0	rw	0x1	CLK_IO_PERI_EN	0 CLK_IO_PERI is disabled. 1 CLK_IO_PERI is enabled.

CLK_HINTS

Clock hint for software gateable transactional clocks during active mode. During low power mode, all clocks are gated off regardless of the software hint.

Transactional clocks are not fully controlled by software. Instead software provides only a disable hint.

When software provides a disable hint, the clock manager checks to see if the associated hardware block is idle. If the hardware block is idle, then the clock is disabled. If the hardware block is not idle, the clock is kept on.

For the enable case, the software hint is immediately honored and the clock turned on. Hardware does not provide any feedback in this case.

Offset: 0x1c
Reset default: 0xf
Reset mask: 0xf

Fields

{"reg": [{"name": "CLK_MAIN_AES_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_OTBN_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

Bits	Type	Reset	Name	Description
31:4				Reserved
3	rw	0x1	CLK_MAIN_OTBN_HINT	0 CLK_MAIN_OTBN can be disabled. 1 CLK_MAIN_OTBN is enabled.
2	rw	0x1	CLK_MAIN_KMAC_HINT	0 CLK_MAIN_KMAC can be disabled. 1 CLK_MAIN_KMAC is enabled.
1	rw	0x1	CLK_MAIN_HMAC_HINT	0 CLK_MAIN_HMAC can be disabled. 1 CLK_MAIN_HMAC is enabled.
0	rw	0x1	CLK_MAIN_AES_HINT	0 CLK_MAIN_AES can be disabled. 1 CLK_MAIN_AES is enabled.

CLK_HINTS_STATUS

Since the final state of CLK_HINTS is not always determined by software, this register provides read feedback for the current clock state.

Offset: 0x20
Reset default: 0xf
Reset mask: 0xf

Fields

{"reg": [{"name": "CLK_MAIN_AES_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_OTBN_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}

Bits	Type	Reset	Name	Description
31:4				Reserved
3	ro	0x1	CLK_MAIN_OTBN_VAL	0 CLK_MAIN_OTBN is disabled. 1 CLK_MAIN_OTBN is enabled.
2	ro	0x1	CLK_MAIN_KMAC_VAL	0 CLK_MAIN_KMAC is disabled. 1 CLK_MAIN_KMAC is enabled.
1	ro	0x1	CLK_MAIN_HMAC_VAL	0 CLK_MAIN_HMAC is disabled. 1 CLK_MAIN_HMAC is enabled.
0	ro	0x1	CLK_MAIN_AES_VAL	0 CLK_MAIN_AES is disabled. 1 CLK_MAIN_AES is enabled.

MEASURE_CTRL_REGWEN

Measurement control write enable

Offset: 0x24
Reset default: 0x1
Reset mask: 0x1

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

Bits	Type	Reset	Name	Description
31:1				Reserved
0	rw0c	0x1	EN	When 1, the value of the measurement control can be set. When 0, writes have no effect.

IO_MEAS_CTRL_EN

Enable for measurement control

Offset: 0x28
Reset default: 0x9
Reset mask: 0xf
Register enable: MEASURE_CTRL_REGWEN

Fields

{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

Bits	Type	Reset	Name	Description
31:4				Reserved
3:0	rw	0x9	EN	Enable measurement for io

IO_MEAS_CTRL_SHADOWED

Configuration controls for io measurement.

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

Offset: 0x2c
Reset default: 0xec8a
Reset mask: 0x3ffff
Register enable: MEASURE_CTRL_REGWEN

Fields

{"reg": [{"name": "HI", "bits": 9, "attr": ["rw"], "rotate": 0}, {"name": "LO", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 14}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

Bits	Type	Reset	Name	Description
31:18				Reserved
17:9	rw	0x76	LO	Min threshold for io measurement
8:0	rw	0x8a	HI	Max threshold for io measurement

MAIN_MEAS_CTRL_EN

Enable for measurement control

Offset: 0x30
Reset default: 0x9
Reset mask: 0xf
Register enable: MEASURE_CTRL_REGWEN

Fields

{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

Bits	Type	Reset	Name	Description
31:4				Reserved
3:0	rw	0x9	EN	Enable measurement for main

MAIN_MEAS_CTRL_SHADOWED

Configuration controls for main measurement.

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

Offset: 0x34
Reset default: 0xec8a
Reset mask: 0x3ffff
Register enable: MEASURE_CTRL_REGWEN

Fields

{"reg": [{"name": "HI", "bits": 9, "attr": ["rw"], "rotate": 0}, {"name": "LO", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 14}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

Bits	Type	Reset	Name	Description
31:18				Reserved
17:9	rw	0x76	LO	Min threshold for main measurement
8:0	rw	0x8a	HI	Max threshold for main measurement

RECOV_ERR_CODE

Recoverable Error code

Offset: 0x38
Reset default: 0x0
Reset mask: 0x1f

Fields

{"reg": [{"name": "SHADOW_UPDATE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "IO_MEASURE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "MAIN_MEASURE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "IO_TIMEOUT_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "MAIN_TIMEOUT_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}

Bits	Type	Reset	Name	Description
31:5				Reserved
4	rw1c	0x0	MAIN_TIMEOUT_ERR	main has timed out.
3	rw1c	0x0	IO_TIMEOUT_ERR	io has timed out.
2	rw1c	0x0	MAIN_MEASURE_ERR	main has encountered a measurement error.
1	rw1c	0x0	IO_MEASURE_ERR	io has encountered a measurement error.
0	rw1c	0x0	SHADOW_UPDATE_ERR	One of the shadow registers encountered an update error.

FATAL_ERR_CODE

Error code

Offset: 0x3c
Reset default: 0x0
Reset mask: 0x7

Fields

{"reg": [{"name": "REG_INTG", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "IDLE_CNT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SHADOW_STORAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

Bits	Type	Reset	Name	Description
31:3				Reserved
2	ro	0x0	SHADOW_STORAGE_ERR	One of the shadow registers encountered a storage error.
1	ro	0x0	IDLE_CNT	One of the idle counts encountered a duplicate error.
0	ro	0x0	REG_INTG	Register file has experienced a fatal integrity error.