Registers

Summary

ALERT_TEST

Alert Test Register

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "recov_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

EXTCLK_CTRL_REGWEN

External clock control write enable

• Offset: 0x4
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

EXTCLK_CTRL

Select external clock

• Offset: 0x8
• Reset default: 0x99
• Reset mask: 0xff
• Register enable: EXTCLK_CTRL_REGWEN

Fields

{"reg": [{"name": "SEL", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HI_SPEED_SEL", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}}

EXTCLK_CTRL . HI_SPEED_SEL

A value of kMultiBitBool4True selects nominal speed external clock. All other values selects low speed clocks.

Note this field only has an effect when the EXTCLK_CTRL.SEL field is set to kMultiBitBool4True.

Nominal speed means the external clock is approximately the same frequency as the internal oscillator source. When this option is used, all clocks operate at roughly the nominal frequency.

Low speed means the external clock is approximately half the frequency of the internal oscillator source. When this option is used, the internal dividers are stepped down. As a result, previously undivided clocks now run at half frequency, while previously divided clocks run at roughly the nominal frequency.

See external clock switch support in documentation for more details.

EXTCLK_CTRL . SEL

When the current value is not kMultiBitBool4True, writing a value of kMultiBitBool4True selects external clock as clock for the system. Writing any other value has no impact.

When the current value is kMultiBitBool4True, writing a value of kMultiBitBool4False selects internal clock as clock for the system. Writing any other value during this stage has no impact.

While this register can always be programmed, it only takes effect when debug functions are enabled in life cycle TEST, DEV or RMA states.

EXTCLK_STATUS

Status of requested external clock switch

• Offset: 0xc
• Reset default: 0x9
• Reset mask: 0xf

Fields

{"reg": [{"name": "ACK", "bits": 4, "attr": ["ro"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

EXTCLK_STATUS . ACK

When EXTCLK_CTRL.SEL is set to kMultiBitBool4True, this field reflects whether the clock has been switched the external source.

kMultiBitBool4True indicates the switch is complete. kMultiBitBool4False indicates the switch is either not possible or still ongoing.

JITTER_REGWEN

Jitter write enable

• Offset: 0x10
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

JITTER_ENABLE

Enable jittery clock

• Offset: 0x14
• Reset default: 0x9
• Reset mask: 0xf
• Register enable: JITTER_REGWEN

Fields

{"reg": [{"name": "VAL", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CLK_ENABLES

Clock enable for software gateable clocks. These clocks are directly controlled by software.

• Offset: 0x18
• Reset default: 0x3
• Reset mask: 0x3

Fields

{"reg": [{"name": "CLK_IO_DIV4_PERI_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_IO_DIV2_PERI_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}

CLK_HINTS

Clock hint for software gateable transactional clocks during active mode. During low power mode, all clocks are gated off regardless of the software hint.

Transactional clocks are not fully controlled by software. Instead software provides only a disable hint.

When software provides a disable hint, the clock manager checks to see if the associated hardware block is idle. If the hardware block is idle, then the clock is disabled. If the hardware block is not idle, the clock is kept on.

For the enable case, the software hint is immediately honored and the clock turned on. Hardware does not provide any feedback in this case.

• Offset: 0x1c
• Reset default: 0xf
• Reset mask: 0xf

Fields

{"reg": [{"name": "CLK_MAIN_AES_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_OTBN_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

CLK_HINTS_STATUS

Since the final state of CLK_HINTS is not always determined by software, this register provides read feedback for the current clock state.

• Offset: 0x20
• Reset default: 0xf
• Reset mask: 0xf

Fields

{"reg": [{"name": "CLK_MAIN_AES_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_OTBN_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}

MEASURE_CTRL_REGWEN

Measurement control write enable

• Offset: 0x24
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

IO_DIV4_MEAS_CTRL_EN

Enable for measurement control

• Offset: 0x28
• Reset default: 0x9
• Reset mask: 0xf
• Register enable: MEASURE_CTRL_REGWEN

Fields

{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

IO_DIV4_MEAS_CTRL_SHADOWED

Configuration controls for io_div4 measurement.

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

• Offset: 0x2c
• Reset default: 0xec8a
• Reset mask: 0x3ffff
• Register enable: MEASURE_CTRL_REGWEN

Fields

{"reg": [{"name": "HI", "bits": 9, "attr": ["rw"], "rotate": 0}, {"name": "LO", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 14}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MAIN_MEAS_CTRL_EN

Enable for measurement control

• Offset: 0x30
• Reset default: 0x9
• Reset mask: 0xf
• Register enable: MEASURE_CTRL_REGWEN

Fields

{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MAIN_MEAS_CTRL_SHADOWED

Configuration controls for main measurement.

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

• Offset: 0x34
• Reset default: 0xec8a
• Reset mask: 0x3ffff
• Register enable: MEASURE_CTRL_REGWEN

Fields

{"reg": [{"name": "HI", "bits": 9, "attr": ["rw"], "rotate": 0}, {"name": "LO", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 14}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

RECOV_ERR_CODE

Recoverable Error code

• Offset: 0x38
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "SHADOW_UPDATE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "IO_DIV4_MEASURE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "MAIN_MEASURE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "IO_DIV4_TIMEOUT_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "MAIN_TIMEOUT_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}

FATAL_ERR_CODE

Error code

• Offset: 0x3c
• Reset default: 0x0
• Reset mask: 0x7

Fields

{"reg": [{"name": "REG_INTG", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "IDLE_CNT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SHADOW_STORAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}