Advanced Encryption Standard.
Isolated from the surrounding environment, particularly from networks or the operating system.
The process of a device taking some measurement and checking it matches what is expected.
Unit of measurement for “symbols per second” where symbols are some unit being communicated over a channel.
Often abbreviated to Bd, kBd (1000 Bd), MBd (1000 kBd), and GBd (1000 MBd).
Comportable (hardware) Intellectual Property.
See the comportability specification.
Cyclic Redundancy Check.
Cryptographically Secure Random Number Generator.
Client to Authenticator Protocol.
A protocol for authentication devices to communicate with a host computer.
ChipWhisperer CW310 “Bergen” FPGA board.
ChipWhisperer CW340 “Luna” FPGA baseboard.
A work-in-progress integrated OpenTitan top level.
Device Interface Function.
Design verification simulator tool.
The first discrete OpenTitan top level. See Earl Grey for a the full specification.
Electronic Design Automation.
Entropy Distribution Network.
Embedded Position Independent Code.
Enhanced Physical Memory Protection.
A RISC-V extension to the physical memory protection part of the RISC-V privileged architecture specification. Also known as “Smepmp”.
Fast Identity Online version 2.
A collection of protocol specifications for authenticating a user with a device or server.
Federal Information Process Standards.
A type of non-volatile reprogrammable memory.
Field Programmable Gate Array.
Formal Property Verification.
Galois Field of order 2.
Hardware Description Language.
Hash-based Message Authentication Code.
Hardware Security Module.
A custom OpenTitan development harness for testing and debugging deployments on CW310 and CW340 FPGA boards.
The 32-bit RISC-V core used in OpenTitan chips.
Keccak Message Authentication Code.
Read-Only Memory encoded into the “mask” used to fabricate silicon.
A list of connections between nodes of a circuit.
OpenTitan Big Number accelerator - a RISC-V-like programmable coprocessor for asymmetric cryptographic algorithms.
One-Time Programmable (memory).
Public Key Infrastructure.
Physical Memory Protection.
Pseudorandom Number Generator.
Request For Comments.
The open source instruction set architecture used for OpenTitan cores.
Random Number Generator.
Root of Trust.
RISC-V Debug Module.
Secure Hash Algorithms.
The semiconductor material that most microchips are made from.
A simple test used to check that some feature works to some degree, even if not in depth.
System on a Chip.
Serial Peripheral Interface.
Static Random-Access Memory.
Externally-exposed pins used to provide early-boot configuration to OpenTitan.
Test Access Port.
The process of fabricating a chip.
Trusted Computing Base.
TileLink Uncached Lightweight (bus/crossbar).
An embedded operating system implemented in Rust.
A full chip design, including all its components and external connections.
Trusted Platform Module.
Universal Asynchronous Receiver-Transmitter.