Registers

Summary

NameOffsetLengthDescription
pwrmgr.INTR_STATE0x04Interrupt State Register
pwrmgr.INTR_ENABLE0x44Interrupt Enable Register
pwrmgr.INTR_TEST0x84Interrupt Test Register
pwrmgr.ALERT_TEST0xc4Alert Test Register
pwrmgr.CTRL_CFG_REGWEN0x104Controls the configurability of the !!CONTROL register.
pwrmgr.CONTROL0x144Control register
pwrmgr.CFG_CDC_SYNC0x184The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the
pwrmgr.WAKEUP_EN_REGWEN0x1c4Configuration enable for wakeup_en register
pwrmgr.WAKEUP_EN0x204Bit mask for enabled wakeups
pwrmgr.WAKE_STATUS0x244A read only register of all current wake requests post enable mask
pwrmgr.RESET_EN_REGWEN0x284Configuration enable for reset_en register
pwrmgr.RESET_EN0x2c4Bit mask for enabled reset requests
pwrmgr.RESET_STATUS0x304A read only register of all current reset requests post enable mask
pwrmgr.ESCALATE_RESET_STATUS0x344A read only register of escalation reset request
pwrmgr.WAKE_INFO_CAPTURE_DIS0x384Indicates which functions caused the chip to wakeup
pwrmgr.WAKE_INFO0x3c4Indicates which functions caused the chip to wakeup.
pwrmgr.FAULT_STATUS0x404A read only register that shows the existing faults

INTR_STATE

Interrupt State Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

{"reg": [{"name": "wakeup", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw1c0x0wakeupWake from low power state. See wake info for more details

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

{"reg": [{"name": "wakeup", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw0x0wakeupEnable interrupt when INTR_STATE.wakeup is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

{"reg": [{"name": "wakeup", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0wo0x0wakeupWrite 1 to force INTR_STATE.wakeup to 1.

ALERT_TEST

Alert Test Register

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
BitsTypeResetNameDescription
31:1Reserved
0wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.

CTRL_CFG_REGWEN

Controls the configurability of the CONTROL register.

This register ensures the contents do not change once a low power hint and WFI has occurred.

It unlocks whenever a low power transition has completed (transition back to the ACTIVE state) for any reason.

  • Offset: 0x10
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0ro0x1ENConfiguration enable. This bit defaults to 1 and is set to 0 by hardware when low power entry is initiated. When the device transitions back from low power state to active state, this bit is set back to 1 to allow software configuration of CONTROL

CONTROL

Control register

  • Offset: 0x14
  • Reset default: 0x180
  • Reset mask: 0x1f1
  • Register enable: CTRL_CFG_REGWEN

Fields

{"reg": [{"name": "LOW_POWER_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "CORE_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IO_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "USB_CLK_EN_LP", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "USB_CLK_EN_ACTIVE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MAIN_PD_N", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
BitsTypeResetName
31:9Reserved
8rw0x1MAIN_PD_N
7rw0x1USB_CLK_EN_ACTIVE
6rw0x0USB_CLK_EN_LP
5rw0x0IO_CLK_EN
4rw0x0CORE_CLK_EN
3:1Reserved
0rw0x0LOW_POWER_HINT

CONTROL . MAIN_PD_N

Active low, main power domain power down

ValueNameDescription
0x0Power downMain power domain is powered down during low power state.
0x1Power upMain power domain is kept powered during low power state

CONTROL . USB_CLK_EN_ACTIVE

USB clock enable during active power state

ValueNameDescription
0x0DisabledUSB clock disabled during active power state
0x1EnabledUSB clock enabled during active power state

CONTROL . USB_CLK_EN_LP

USB clock enable during low power state

ValueNameDescription
0x0DisabledUSB clock disabled during low power state
0x1EnabledUSB clock enabled during low power state. However, if !!CONTROL.MAIN_PD_N is 0, USB clock is disabled during low power state.

CONTROL . IO_CLK_EN

IO clock enable during low power state

ValueNameDescription
0x0DisabledIO clock disabled during low power state
0x1EnabledIO clock enabled during low power state

CONTROL . CORE_CLK_EN

core clock enable during low power state

ValueNameDescription
0x0DisabledCore clock disabled during low power state
0x1EnabledCore clock enabled during low power state

CONTROL . LOW_POWER_HINT

The low power hint to power manager. The hint is an indication for how the manager should treat the next WFI. Once the power manager begins a low power transition, or if a valid reset request is registered, this bit is automatically cleared by HW.

ValueNameDescription
0x0NoneNo low power intent
0x1Low PowerNext WFI should trigger low power entry

CFG_CDC_SYNC

The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the fast clock domain but used in the slow clock domain.

The configuration are not propagated across the clock boundary until this register is triggered and read. See fields below for more details

  • Offset: 0x18
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

{"reg": [{"name": "SYNC", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:1Reserved
0rw0x0SYNC

CFG_CDC_SYNC . SYNC

Configuration sync. When this bit is written to 1, a sync pulse is generated. When the sync completes, this bit then self clears.

Software should write this bit to 1, wait for it to clear, before assuming the slow clock domain has accepted the programmed values.

WAKEUP_EN_REGWEN

Configuration enable for wakeup_en register

  • Offset: 0x1c
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ENWhen 1, WAKEUP_EN register can be configured. When 0, WAKEUP_EN register cannot be configured.

WAKEUP_EN

Bit mask for enabled wakeups

  • Offset: 0x20
  • Reset default: 0x0
  • Reset mask: 0x3f
  • Register enable: WAKEUP_EN_REGWEN

Fields

{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:6Reserved
5rw0x0EN_5Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.
4rw0x0EN_4Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.
3rw0x0EN_3Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.
2rw0x0EN_2Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.
1rw0x0EN_1Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.
0rw0x0EN_0Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.

WAKE_STATUS

A read only register of all current wake requests post enable mask

  • Offset: 0x24
  • Reset default: 0x0
  • Reset mask: 0x3f

Fields

{"reg": [{"name": "VAL_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:6Reserved
5ro0x0VAL_5Current value of wake requests
4ro0x0VAL_4Current value of wake requests
3ro0x0VAL_3Current value of wake requests
2ro0x0VAL_2Current value of wake requests
1ro0x0VAL_1Current value of wake requests
0ro0x0VAL_0Current value of wake requests

RESET_EN_REGWEN

Configuration enable for reset_en register

  • Offset: 0x28
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ENWhen 1, RESET_EN register can be configured. When 0, RESET_EN register cannot be configured.

RESET_EN

Bit mask for enabled reset requests

  • Offset: 0x2c
  • Reset default: 0x0
  • Reset mask: 0x3
  • Register enable: RESET_EN_REGWEN

Fields

{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:2Reserved
1rw0x0EN_1Whenever a particular bit is set to 1, that reset request is enabled. Whenever a particular bit is set to 0, that reset request cannot reset the device.
0rw0x0EN_0Whenever a particular bit is set to 1, that reset request is enabled. Whenever a particular bit is set to 0, that reset request cannot reset the device.

RESET_STATUS

A read only register of all current reset requests post enable mask

  • Offset: 0x30
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

{"reg": [{"name": "VAL_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:2Reserved
1ro0x0VAL_1Current value of reset request
0ro0x0VAL_0Current value of reset request

ESCALATE_RESET_STATUS

A read only register of escalation reset request

  • Offset: 0x34
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

{"reg": [{"name": "VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0ro0x0VALWhen 1, an escalation reset has been seen. When 0, there is no escalation reset.

WAKE_INFO_CAPTURE_DIS

Indicates which functions caused the chip to wakeup

  • Offset: 0x38
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

{"reg": [{"name": "VAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw0x0VALWhen written to 1, this actively suppresses the wakeup info capture. When written to 0, wakeup info capture timing is controlled by HW.

WAKE_INFO

Indicates which functions caused the chip to wakeup. The wake info recording begins whenever the device begins a valid low power entry.

This capture is continued until it is explicitly disabled through WAKE_INFO_CAPTURE_DIS. This means it is possible to capture multiple wakeup reasons.

  • Offset: 0x3c
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

{"reg": [{"name": "REASONS", "bits": 6, "attr": ["rw1c"], "rotate": 0}, {"name": "FALL_THROUGH", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ABORT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}}
BitsTypeResetName
31:8Reserved
7rw1c0x0ABORT
6rw1c0x0FALL_THROUGH
5:0rw1c0x0REASONS

WAKE_INFO . ABORT

The abort wakeup reason indicates that despite setting a WFI and providing a low power hint, an active flash / lifecycle / otp transaction was ongoing when the power controller attempted to initiate low power entry.

The power manager detects this condition, halts low power entry and reports as a wakeup reason

WAKE_INFO . FALL_THROUGH

The fall through wakeup reason indicates that despite setting a WFI and providing a low power hint, an interrupt arrived at just the right time to break the executing core out of WFI.

The power manager detects this condition, halts low power entry and reports as a wakeup reason

WAKE_INFO . REASONS

Various peripheral wake reasons

FAULT_STATUS

A read only register that shows the existing faults

  • Offset: 0x40
  • Reset default: 0x0
  • Reset mask: 0x7

Fields

{"reg": [{"name": "REG_INTG_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ESC_TIMEOUT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_PD_GLITCH", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
BitsTypeResetNameDescription
31:3Reserved
2ro0x0MAIN_PD_GLITCHWhen 1, unexpected power glitch was observed on main PD.
1ro0x0ESC_TIMEOUTWhen 1, an escalation clock / reset timeout has occurred.
0ro0x0REG_INTG_ERRWhen 1, an integrity error has occurred.