Referring to the Comportable guideline for peripheral device functionality, the module edn has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: none
  • Bus Device Interfaces (TL-UL): tl
  • Bus Host Interfaces (TL-UL): none
  • Peripheral Pins for Chip IO: none

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription
csrng_cmdcsrng_pkg::csrngreq_rspreq1EDN supports a signal CSRNG application interface.
ednedn_pkg::ednreq_rsprsp8The collection of peripheral ports supported by edn. The width (4) indicates the number of peripheral ports on a single instance. Due to limitations in the parametrization of top-level interconnects this value is not currently parameterizable. However, the number of peripheral ports may change in a future revision.


Interrupt NameTypeDescription
edn_cmd_req_doneEventAsserted when a software CSRNG request has completed.
edn_fatal_errEventAsserted when a FIFO error occurs.

Security Alerts

Alert NameDescription
recov_alertThis alert is triggered when entropy bus data matches on consecutive clock cycles.
fatal_alertThis alert triggers (i) if an illegal state machine state is reached, or (ii) if a fatal integrity failure is detected on the TL-UL bus.

Security Countermeasures

Countermeasure IDDescription
EDN.CONFIG.REGWENRegisters are protected from writes.
EDN.CONFIG.MUBIRegisters have multi-bit encoded fields.
EDN.MAIN_SM.FSM.SPARSEThe EDN main state machine uses a sparse state encoding.
EDN.ACK_SM.FSM.SPARSEThe EDN ACK state machine uses a sparse state encoding.
EDN.FIFO.CTR.REDUNThe FIFO pointers of several FIFOs are implemented with duplicate counters.
EDN.CTR.REDUNCounter hardening on the generate command maximum requests counter.
EDN.MAIN_SM.CTR.LOCAL_ESCA mismatch detected inside any EDN counter moves the main state machine into a terminal error state.
EDN.CS_RDATA.BUS.CONSISTENCYComparison on successive bus values for genbits returned from csrng that will distribute over the endpoint buses.
EDN.TILE_LINK.BUS.INTEGRITYTilelink end-to-end bus integrity scheme.