Referring to the Comportable guideline for peripheral device functionality, the module
edn has the following hardware interfaces defined
- Primary Clock:
- Other Clocks: none
- Bus Device Interfaces (TL-UL):
- Bus Host Interfaces (TL-UL): none
- Peripheral Pins for Chip IO: none
|EDN supports a signal CSRNG application interface.
|The collection of peripheral ports supported by edn. The width (4) indicates the number of peripheral ports on a single instance. Due to limitations in the parametrization of top-level interconnects this value is not currently parameterizable. However, the number of peripheral ports may change in a future revision.
|Asserted when a software CSRNG request has completed.
|Asserted when a FIFO error occurs.
|This alert is triggered when entropy bus data matches on consecutive clock cycles.
|This alert triggers (i) if an illegal state machine state is reached, or (ii) if a fatal integrity failure is detected on the TL-UL bus.
|Registers are protected from writes.
|Registers have multi-bit encoded fields.
|The EDN main state machine uses a sparse state encoding.
|The EDN ACK state machine uses a sparse state encoding.
|Counter hardening on the generate command maximum requests counter.
|A mismatch detected inside any EDN counter moves the main state machine into a terminal error state.
|Comparison on successive bus values for genbits returned from csrng that will distribute over the endpoint buses.
|Tilelink end-to-end bus integrity scheme.