RV_PLIC Checklist

This checklist is for Hardware Stage transitions for the RV_PLIC peripheral. All checklist items refer to the content in the Checklist.

Design Checklist

D1

TypeItemResolutionNote/Collaterals
DocumentationSPEC_COMPLETEDoneRV_PLIC Spec
DocumentationCSR_DEFINEDDone
RTLCLKRST_CONNECTEDDone
RTLIP_TOPDone
RTLIP_INSTANTIABLEDone
RTLPHYSICAL_MACROS_DEFINED_80Done
RTLFUNC_IMPLEMENTEDDone
RTLASSERT_KNOWN_ADDEDDone
Code QualityLINT_SETUPDone

D2

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURESN/A
DocumentationBLOCK_DIAGRAMDone
DocumentationDOC_INTERFACEDone
DocumentationMISSING_FUNCN/A
DocumentationFEATURE_FROZENDone
RTLFEATURE_COMPLETEDone
RTLAREA_CHECKDone
RTLPORT_FROZENDone
RTLARCHITECTURE_FROZENDone
RTLREVIEW_TODODoneOne TODO about Vivado Issue
RTLSTYLE_XDone
Code QualityLINT_PASSDone
Code QualityCDC_SETUPN/A
Code QualityTIMING_CHECKDoneFmax @ 50MHz on NexysVideo
Code QualityCDC_SYNCMACRON/A
SecuritySEC_CM_DOCUMENTEDN/A

D2S

TypeItemResolutionNote/Collaterals
SecuritySEC_CM_ASSETS_LISTEDDone
SecuritySEC_CM_IMPLEMENTEDDone
SecuritySEC_CM_RND_CNSTN/A
SecuritySEC_CM_NON_RESET_FLOPSN/A
SecuritySEC_CM_SHADOW_REGSN/A
SecuritySEC_CM_RTL_REVIEWEDN/A
SecuritySEC_CM_COUNCIL_REVIEWEDN/AThis block only contains the bus-integrity CM.

D3

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURES_D3Done
RTLTODO_COMPLETEDone
Code QualityLINT_COMPLETEDone
Code QualityCDC_COMPLETEWaivedNo block-level flow available - waived to top-level signoff.
Code QualityRDC_COMPLETEWaivedNo block-level flow available - waived to top-level signoff.
ReviewREVIEW_RTLDone
ReviewREVIEW_DELETED_FFWaivedNo block-level flow available - waived to top-level signoff.
ReviewREVIEW_SW_CHANGEDone
ReviewREVIEW_SW_ERRATADone
ReviewReviewer(s)Doneeunchan@ gac@ chencindy@ ttrippel@
ReviewSignoff dateDone2022-07-25

Verification Checklist

V1

V2

V2S

TypeItemResolutionNote/Collaterals
DocumentationSEC_CM_TESTPLAN_COMPLETEDWaivedWaived since only 1 standard sec_cm - bus integrity.
TestsFPV_SEC_CM_PROVENDoneThe bus integrity cm has been proven formally.
TestsSIM_SEC_CM_VERIFIEDN/AThis module only has an FPV testbench.
CoverageSIM_COVERAGE_REVIEWEDN/AThis module only has an FPV testbench.
ReviewSEC_CM_DV_REVIEWEDWaivedWaived since only 1 standard sec_cm - bus integrity.

V3

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V3Not Started
TestsX_PROP_ANALYSIS_COMPLETEDNot Started
TestsFPV_ASSERTIONS_PROVEN_AT_V3Not Started
RegressionSIM_NIGHTLY_REGRESSION_AT_V3Not Started
CoverageSIM_CODE_COVERAGE_AT_100Not Started
CoverageSIM_FUNCTIONAL_COVERAGE_AT_100Not Started
CoverageFPV_CODE_COVERAGE_AT_100Not Started
CoverageFPV_COI_COVERAGE_AT_100Not Started
Code QualityALL_TODOS_RESOLVEDNot Started
Code QualityNO_TOOL_WARNINGS_THROWNNot Started
Code QualityTB_LINT_COMPLETENot Started
IntegrationPRE_VERIFIED_SUB_MODULES_V3Not Started
IssuesNO_ISSUES_PENDINGNot Started
ReviewReviewer(s)Not Started
ReviewSignoff dateNot Started