Registers

A number of memory-mapped registers are available to control Ibex-related functionality that’s specific to OpenTitan.

Summary

ALERT_TEST

Alert Test Register

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0xf

Fields

{"reg": [{"name": "fatal_sw_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "recov_sw_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_hw_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "recov_hw_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}}

SW_RECOV_ERR

Software recoverable error

• Offset: 0x4
• Reset default: 0x9
• Reset mask: 0xf

Fields

{"reg": [{"name": "VAL", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

SW_FATAL_ERR

Software fatal error

• Offset: 0x8
• Reset default: 0x9
• Reset mask: 0xf

Fields

{"reg": [{"name": "VAL", "bits": 4, "attr": ["rw1s"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

IBUS_REGWEN

Ibus address control regwen.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

IBUS_REGWEN . EN

Ibus address controls write enable. Once set to 0, it can longer be configured to 1

IBUS_ADDR_EN

Enable Ibus address matching

• Reset default: 0x0
• Reset mask: 0x1
• Register enable: IBUS_REGWEN

Instances

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

IBUS_ADDR_MATCHING

Matching region programming for ibus.

The value programmed is done at power-of-2 alignment. For example, if the intended matching region is 0x8000_0000 to 0x8000_FFFF, the value programmed is 0x8000_7FFF.

The value programmed can be determined from the translation granule. Assume the user wishes to translate a specific 64KB block to a different address: 64KB has a hex value of 0x10000. Subtract 1 from this value and then right shift by one to obtain 0x7FFF. This value is then logically OR’d with the upper address bits that would select which 64KB to translate.

In this example, the user wishes to translate the 0x8000-th 64KB block. The value programmed is then 0x8000_7FFF.

If the user were to translate the 0x8001-th 64KB block, the value programmed would be 0x8001_7FFF.

• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: IBUS_REGWEN

Instances

Fields

{"reg": [{"name": "VAL", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

IBUS_REMAP_ADDR

The remap address after a match has been made. The remap bits apply only to top portion of address bits not covered by the matching region.

For example, if the translation region is 64KB, the remapped address applies only to the upper address bits that select which 64KB to be translated.

• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: IBUS_REGWEN

Instances

Fields

{"reg": [{"name": "VAL", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DBUS_REGWEN

Dbus address control regwen.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DBUS_REGWEN . EN

Ibus address controls write enable. Once set to 0, it can longer be configured to 1

DBUS_ADDR_EN

Enable dbus address matching

• Reset default: 0x0
• Reset mask: 0x1
• Register enable: DBUS_REGWEN

Instances

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DBUS_ADDR_MATCHING

See IBUS_ADDR_MATCHING_0 for detailed description.

• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: DBUS_REGWEN

Instances

Fields

{"reg": [{"name": "VAL", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DBUS_REMAP_ADDR

See IBUS_REMAP_ADDR_0 for a detailed description.

• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: DBUS_REGWEN

Instances

Fields

{"reg": [{"name": "VAL", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

NMI_ENABLE

Enable mask for NMI. Once an enable mask is set, it cannot be disabled.

• Offset: 0x40c
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "ALERT_EN", "bits": 1, "attr": ["rw1s"], "rotate": -90}, {"name": "WDOG_EN", "bits": 1, "attr": ["rw1s"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}

NMI_STATE

Current NMI state

• Offset: 0x410
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "ALERT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "WDOG", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ERR_STATUS

error status

• Offset: 0x414
• Reset default: 0x0
• Reset mask: 0x701

Fields

{"reg": [{"name": "REG_INTG_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 7}, {"name": "FATAL_INTG_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "FATAL_CORE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "RECOV_CORE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}

RND_DATA

Random data from EDN

• Offset: 0x418
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "DATA", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

RND_DATA . DATA

Random bits taken from the EDN. RND_STATUS.RND_DATA_VALID indicates if this data is valid. When valid, reading from this register invalidates the data and requests new data from the EDN. The register becomes valid again when the EDN provides new data. When invalid the register value will read as 0x0 with an EDN request for new data pending. Upon reset the data will be invalid with a new EDN request pending.

RND_STATUS

Status of random data in RND_DATA

• Offset: 0x41c
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "RND_DATA_VALID", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RND_DATA_FIPS", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}

FPGA_INFO

FPGA build timestamp info. This register only contains valid data for fpga, for all other variants it is simply 0.

• Offset: 0x420
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "VAL", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DV_SIM_WINDOW

Exposed tlul window for DV only purposes.

• Word Aligned Offset Range: 0x440to0x45c
• Size (words): 8
• Access: rw
• Byte writes are supported.