Registers

Summary

NameOffsetLengthDescription
csrng.INTR_STATE0x04Interrupt State Register
csrng.INTR_ENABLE0x44Interrupt Enable Register
csrng.INTR_TEST0x84Interrupt Test Register
csrng.ALERT_TEST0xc4Alert Test Register
csrng.REGWEN0x104Register write enable for all control registers
csrng.CTRL0x144Control register
csrng.CMD_REQ0x184Command request register
csrng.SW_CMD_STS0x1c4Application interface command status register
csrng.GENBITS_VLD0x204Generate bits returned valid register
csrng.GENBITS0x244Generate bits returned register
csrng.INT_STATE_NUM0x284Internal state number register
csrng.INT_STATE_VAL0x2c4Internal state read access register
csrng.HW_EXC_STS0x304Hardware instance exception status register
csrng.RECOV_ALERT_STS0x344Recoverable alert status register
csrng.ERR_CODE0x384Hardware detection of error conditions status register
csrng.ERR_CODE_TEST0x3c4Test error conditions register
csrng.MAIN_SM_STATE0x404Main state machine state debug register

INTR_STATE

Interrupt State Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3rw1c0x0cs_fatal_errAsserted when a FIFO error or a fatal alert occurs. Check the ERR_CODE register to get more information.
2rw1c0x0cs_hw_inst_excAsserted when a hardware-attached CSRNG instance encounters a command exception
1rw1c0x0cs_entropy_reqAsserted when a request for entropy has been made.
0rw1c0x0cs_cmd_req_doneAsserted when a command request is completed.

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3rw0x0cs_fatal_errEnable interrupt when INTR_STATE.cs_fatal_err is set.
2rw0x0cs_hw_inst_excEnable interrupt when INTR_STATE.cs_hw_inst_exc is set.
1rw0x0cs_entropy_reqEnable interrupt when INTR_STATE.cs_entropy_req is set.
0rw0x0cs_cmd_req_doneEnable interrupt when INTR_STATE.cs_cmd_req_done is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3wo0x0cs_fatal_errWrite 1 to force INTR_STATE.cs_fatal_err to 1.
2wo0x0cs_hw_inst_excWrite 1 to force INTR_STATE.cs_hw_inst_exc to 1.
1wo0x0cs_entropy_reqWrite 1 to force INTR_STATE.cs_entropy_req to 1.
0wo0x0cs_cmd_req_doneWrite 1 to force INTR_STATE.cs_cmd_req_done to 1.

ALERT_TEST

Alert Test Register

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1wo0x0fatal_alertWrite 1 to trigger one alert event of this kind.
0wo0x0recov_alertWrite 1 to trigger one alert event of this kind.

REGWEN

Register write enable for all control registers

  • Offset: 0x10
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1REGWENWhen true, all writeable registers can be modified. When false, they become read-only.

CTRL

Control register

  • Offset: 0x14
  • Reset default: 0x999
  • Reset mask: 0xfff
  • Register enable: REGWEN

Fields

BitsTypeResetNameDescription
31:12Reserved
11:8rw0x9READ_INT_STATESetting this field to kMultiBitBool4True will enable reading from the INT_STATE_VAL register. Reading the internal state of the enable instances will be enabled only if the otp_en_csrng_sw_app_read input vector is set to the enable encoding.
7:4rw0x9SW_APP_ENABLESetting this field to kMultiBitBool4True will enable reading from the GENBITS register. This application interface for software (register based) will be enabled only if the otp_en_csrng_sw_app_read input vector is set to the enable encoding.
3:0rw0x9ENABLESetting this field to kMultiBitBool4True will enable the CSRNG module. The modules of the entropy complex may only be enabled and disabled in a specific order, see Programmers Guide for details.

CMD_REQ

Command request register

  • Offset: 0x18
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0wo0x0CMD_REQWriting this request with defined CSRNG commands will initiate all possible CSRNG actions. The application interface must wait for the “ack” to return before issuing new commands.

SW_CMD_STS

Application interface command status register

  • Offset: 0x1c
  • Reset default: 0x1
  • Reset mask: 0x3

Fields

BitsTypeResetName
31:2Reserved
1ro0x0CMD_STS
0ro0x1CMD_RDY

SW_CMD_STS . CMD_STS

This one bit field is the status code returned with the application command ack. It is updated each time a command ack is asserted on the internal application interface for software use. 0b0: Request completed successfully 0b1: Request completed with an error

SW_CMD_STS . CMD_RDY

This bit indicates when the command interface is ready to accept commands.

GENBITS_VLD

Generate bits returned valid register

  • Offset: 0x20
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1roxGENBITS_FIPSThis bit is set when genbits are FIPS/CC compliant.
0roxGENBITS_VLDThis bit is set when genbits are available on this application interface.

GENBITS

Generate bits returned register

  • Offset: 0x24
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetName
31:0roxGENBITS

GENBITS . GENBITS

Reading this register will get the generated bits that were requested with the generate request. This register must be read four times for each request made. For example, an application command generate request with a clen value of 4 requires this register to be read 16 times to get all of the data out of the FIFO path. Note that for GENBITS to be able to deliver random numbers, also CTRL.SW_APP_ENABLE needs to be set to kMultiBitBool4True. In addition, the otp_en_csrng_sw_app_read input needs to be set to kMultiBitBool8True. Otherwise, the register reads as 0.

INT_STATE_NUM

Internal state number register

  • Offset: 0x28
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

BitsTypeResetName
31:4Reserved
3:0rw0x0INT_STATE_NUM

INT_STATE_NUM . INT_STATE_NUM

Setting this field will set the number for which internal state can be selected for a read access. Up to 16 internal state values can be chosen from this register. The actual number of valid internal state fields is set by parameter NHwApps plus 1 software app. For those selections that point to reserved locations (greater than NHwApps plus 1), the returned value will be zero. Writing this register will also reset the internal read pointer for the INT_STATE_VAL register. Note: This register should be read back after being written to ensure that the INT_STATE_VAL read back is accurate.

INT_STATE_VAL

Internal state read access register

  • Offset: 0x2c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetName
31:0roxINT_STATE_VAL

INT_STATE_VAL . INT_STATE_VAL

Reading this register will dump out the contents of the selected internal state field. Since the internal state field is 448 bits wide, it will require 14 reads from this register to gather the entire field. Once 14 reads have been done, the internal read pointer (selects 32 bits of the 448 bit field) will reset to zero. The INT_STATE_NUM can be re-written at this time (internal read pointer is also reset), and then another internal state field can be read. Note that for INT_STATE_VAL to provide read access to the internal state, also CTRL.READ_INT_STATE needs to be set to kMultiBitBool4True. In addition, the otp_en_csrng_sw_app_read input needs to be set to kMultiBitBool8True. Otherwise, the register reads as 0.

HW_EXC_STS

Hardware instance exception status register

  • Offset: 0x30
  • Reset default: 0x0
  • Reset mask: 0xffff

Fields

BitsTypeResetName
31:16Reserved
15:0rw0c0x0HW_EXC_STS

HW_EXC_STS . HW_EXC_STS

Reading this register indicates whether one of the CSRNG HW instances has encountered an exception. Each bit corresponds to a particular hardware instance, with bit 0 corresponding to instance HW0, bit 1 corresponding to instance HW1, and so forth. (To monitor the status of requests made to the SW instance, check the SW_CMD_STS register). Writing a zero to this register resets the status bits.

RECOV_ALERT_STS

Recoverable alert status register

  • Offset: 0x34
  • Reset default: 0x0
  • Reset mask: 0x300f

Fields

BitsTypeResetNameDescription
31:14Reserved
13rw0c0x0CS_MAIN_SM_ALERTThis bit is set when an unsupported/illegal CSRNG command is being processed. The main FSM will hang unless the module enable field is set to the disabled state.
12rw0c0x0CS_BUS_CMP_ALERTThis bit is set when the software application port genbits bus value is equal to the prior valid value on the bus, indicating a possible attack. Writing a zero resets this status bit.
11:4Reserved
3rw0c0x0ACMD_FLAG0_FIELD_ALERTThis bit is set when the FLAG0 field in the Application Command is set to a value other than kMultiBitBool4True or kMultiBitBool4False. Writing a zero resets this status bit.
2rw0c0x0READ_INT_STATE_FIELD_ALERTThis bit is set when the READ_INT_STATE field in the CTRL register is set to a value other than kMultiBitBool4True or kMultiBitBool4False. Writing a zero resets this status bit.
1rw0c0x0SW_APP_ENABLE_FIELD_ALERTThis bit is set when the SW_APP_ENABLE field in the CTRL register is set to a value other than kMultiBitBool4True or kMultiBitBool4False. Writing a zero resets this status bit.
0rw0c0x0ENABLE_FIELD_ALERTThis bit is set when the ENABLE field in the CTRL register is set to a value other than kMultiBitBool4True or kMultiBitBool4False. Writing a zero resets this status bit.

ERR_CODE

Hardware detection of error conditions status register

  • Offset: 0x38
  • Reset default: 0x0
  • Reset mask: 0x77f0ffff

Fields

ERR_CODE . FIFO_STATE_ERR

This bit will be set to one when any of the source bits (bits 0 through 15 of this this register) are asserted as a result of an error pulse generated from any FIFO where both the empty and full status bits are set. This bit will stay set until the next reset.

ERR_CODE . FIFO_READ_ERR

This bit will be set to one when any of the source bits (bits 0 through 15 of this this register) are asserted as a result of an error pulse generated from any empty FIFO that has recieved a read pulse. This bit will stay set until the next reset.

ERR_CODE . FIFO_WRITE_ERR

This bit will be set to one when any of the source bits (bits 0 through 15 of this this register) are asserted as a result of an error pulse generated from any full FIFO that has been recieved a write pulse. This bit will stay set until the next reset.

ERR_CODE . CMD_GEN_CNT_ERR

This bit will be set to one when a mismatch in any of the hardened counters has been detected. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . AES_CIPHER_SM_ERR

This bit will be set to one when an AES fatal error has been detected. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . DRBG_UPDOB_SM_ERR

This bit will be set to one when an illegal state has been detected for the ctr_drbg update out block state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . DRBG_UPDBE_SM_ERR

This bit will be set to one when an illegal state has been detected for the ctr_drbg update block encode state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . DRBG_GEN_SM_ERR

This bit will be set to one when an illegal state has been detected for the ctr_drbg gen state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . MAIN_SM_ERR

This bit will be set to one when an illegal state has been detected for the main state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . CMD_STAGE_SM_ERR

This bit will be set to one when an illegal state has been detected for the command stage state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . SFIFO_BLKENC_ERR

This bit will be set to one when an error has been detected for the blkenc FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_GGENBITS_ERR

This bit will be set to one when an error has been detected for the ggenbits FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_GADSTAGE_ERR

This bit will be set to one when an error has been detected for the gadstage FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_GGENREQ_ERR

This bit will be set to one when an error has been detected for the ggenreq FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_GRCSTAGE_ERR

This bit will be set to one when an error has been detected for the grcstage FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_GBENCACK_ERR

This bit will be set to one when an error has been detected for the gbencack FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_FINAL_ERR

This bit will be set to one when an error has been detected for the final FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_PDATA_ERR

This bit will be set to one when an error has been detected for the pdata FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_BENCACK_ERR

This bit will be set to one when an error has been detected for the bencack FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_BENCREQ_ERR

This bit will be set to one when an error has been detected for the bencreq FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_UPDREQ_ERR

This bit will be set to one when an error has been detected for the updreq FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_KEYVRC_ERR

This bit will be set to one when an error has been detected for the keyvrc FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_RCSTAGE_ERR

This bit will be set to one when an error has been detected for the rcstage FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_CMDREQ_ERR

This bit will be set to one when an error has been detected for the cmdreq FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_GENBITS_ERR

This bit will be set to one when an error has been detected for the command stage genbits FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_CMD_ERR

This bit will be set to one when an error has been detected for the command stage command FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE_TEST

Test error conditions register

  • Offset: 0x3c
  • Reset default: 0x0
  • Reset mask: 0x1f
  • Register enable: REGWEN

Fields

BitsTypeResetName
31:5Reserved
4:0rw0x0ERR_CODE_TEST

ERR_CODE_TEST . ERR_CODE_TEST

Setting this field will set the bit number for which an error will be forced in the hardware. This bit number is that same one found in the ERR_CODE register. The action of writing this register will force an error pulse. The sole purpose of this register is to test that any error properly propagates to either an interrupt or an alert.

MAIN_SM_STATE

Main state machine state debug register

  • Offset: 0x40
  • Reset default: 0x4e
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7:0ro0x4eMAIN_SM_STATEThis is the state of the CSRNG main state machine. See the RTL file csrng_main_sm for the meaning of the values.