Interrupt Controller Technical Specification


This document specifies the Interrupt Controller (RV_PLIC) functionality. This module conforms to the Comportable guideline for peripheral functionality. See that document for integration overview within the broader top level system.


  • RISC-V Platform-Level Interrupt Controller (PLIC) compliant interrupt controller
  • Support arbitrary number of interrupt vectors (up to 255) and targets
  • Support interrupt enable, interrupt status registers
  • Memory-mapped MSIP register per HART for software interrupt control.


The RV_PLIC module is designed to manage various interrupt sources from the peripherals. It receives interrupt events as either edge or level of the incoming interrupt signals (intr_src_i) and can notify multiple targets.


The RV_PLIC is compatible with any RISC-V core implementing the RISC-V privilege specification.