V1 | smoke | uart_smoke |
- UART smoke test with few bytes transmitted and received asynchronously and
in parallel with scoreboard checks
- TX and RX have 2 independent threads respectively.
- program one Tx item in register and wait for it to complete at uart interface,
before send another one
- sequencally send one Rx byte, then immediately read from register and check it
|
V1 | csr_hw_reset | uart_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
- Write all CSRs with a random value.
- Apply reset to the DUT as well as the RAL model.
- Read each CSR and compare it against the reset value.
it is mandatory to replicate this test for each reset that affects
all or a subset of the CSRs.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
|
V1 | csr_rw | uart_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
- Loop through each CSR to write it with a random value.
- Read the CSR back and check for correctness while adhering to its
access policies.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
|
V1 | csr_bit_bash | uart_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
- Walk a 1 through each CSR by flipping 1 bit at a time.
- Read the CSR back and check for correctness while adhering to its
access policies.
- This verify that writing a specific bit within the CSR did not affect
any of the other bits.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
|
V1 | csr_aliasing | uart_csr_aliasing | Verify no aliasing within the CSR address space.
- Loop through each CSR to write it with a random value
- Shuffle and read ALL CSRs back.
- All CSRs except for the one that was written in this iteration should
read back the previous value.
- The CSR that was written in this iteration is checked for correctness
while adhering to its access policies.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
|
V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
- Run csr_rw sequence to randomly access CSRs
- If memory exists, run mem_partial_access in parallel with csr_rw
- Randomly issue reset and then use hw_reset sequence to check all CSRs
are reset to default value
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
|
V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw
uart_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
- Randomly access all CSRs
- Test when regwen CSR is set, its corresponding lockable CSRs become
read-only registers
Note:
- If regwen CSR is HW read-only, this feature can be fully tested by common
CSR tests - csr_rw and csr_aliasing.
- If regwen CSR is HW updated, a separate test should be created to test it.
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | base_random_seq | uart_tx_rx |
- This is the basic sequence that is extended by most of random sequence.
- TX and RX have 2 independent threads respectively.
- TX: keep programming csr wdata with random delay when fifo isn't full
- RX: 2 processes. One is to send item through uart interface when fifo isn't full
and the other is to read csr rdata when fifo isn't empty
|
V2 | parity | uart_smoke
uart_tx_rx | Send / receive bytes with parity and odd parity enabled randomly. |
V2 | parity_error | uart_rx_parity_err
uart_intr |
- Enable parity and randomly set even/odd parity
- Inject parity error randomly on data sent from rx and ensure the interrupt is
raised
|
V2 | watermark | uart_tx_rx
uart_intr |
- Program random tx/rx fifo watermark level and keep sending random tx/rx data
to fifo.
- As the number of pending data entries in the tx/rx fifo reaches the programmed
watermark level (fifo size >= watermark level), ensure that the watermark interrupt
is asserted
- Ensure interrupt stays asserted until cleared as well as fifo level dropped.
The tx/rx watermark interrupt is sticky
|
V2 | fifo_full | uart_fifo_full | Send over 32 bytes of data but stop when fifo is full |
V2 | fifo_overflow | uart_fifo_overflow |
- Keep sending over 32 bytes of data over tx/rx fifo
- Ensure excess data bytes are dropped and check overflow interrupt
- This uart_fifo_overflow_vseq is extent from uart_fifo_full_vseq and override the
constraint to be able to send data over fifo size
|
V2 | fifo_reset | uart_fifo_reset |
- Fill up the tx/rx fifo. After a random number of bytes shows up on fifo, reset
the fifo and ensure that the remaining data bytes do not show up
- this sequence is extent from uart_fifo_overflow_vseq, so it can also reset when fifo
is at any level, including full or overflow
|
V2 | rx_frame_err | uart_intr |
- Inject frame error in parity and non-parity cases by not setting stop bit = 1
- Ensure the interrupt gets asserted
|
V2 | rx_break_err | uart_intr |
- Program random number of break detection characters
- create a frame error scenario and send random number of 0 bytes
- If that random number exceeds the programmed break characters
- Ensure that the break_err interrupt is asserted
|
V2 | rx_timeout | uart_intr |
- Program timeout_ctrl register to randomize the timeout. Send random number of
data over rx
- Wait until it's about to timeout, then check timeout interrupt doesn't fire. Wait
for timeout and check timeout interrupt fires
- Wait until it's about to timeout, then use either read csr rdata or send RX item
through uart interface to reset timeout timer in order to ensure timeout never
fires
|
V2 | perf | uart_perf | Run fifo_full_vseq with very small delays |
V2 | sys_loopback | uart_loopback |
- Enable system looback, then drive uart TX and data will be loopbacked through RX
- After loopback is done, uart.RDATA will be equal to the data programmed to
uart.WDATA
|
V2 | line_loopback | uart_loopback |
- Enable line loopback and drive uart_rx with random data and random delay
- Check uart_tx has same value as uart_rx. There is not synchronizer register between
uart_rx and uart_tx during line loopback
|
V2 | rx_noise_filter | uart_noise_filter |
- Use 16x fast clk to sample it, data on uart_rx need to be stable for 3 clocks,
otherwise, data change won't be taken
- Enable noise filter and drive many glitches. Each glitch doesn't lasts less than
3 clocks
- Ensure the noise will be filterred out and it doesn't affect next normal
transaction
|
V2 | rx_start_bit_filter | uart_rx_start_bit_filter |
- Start bit should last for at least half baud clock, otherwise, it will be dropped
- It's always enabled. Drive start bit for less than half cycle.
- Ensure the start bit will be dropped
|
V2 | tx_overide | uart_tx_ovrd | Enable override control and use register programming to drive uart output
directly. |
V2 | rx_oversample | uart_rx_oversample |
- Use 16x baud clock to sample uart rx
- Drive uart rx with 16 bits value, using 16x baud clock
- Read RX oversampled value and ensure it's same as driven value
|
V2 | long_b2b_transfer | uart_long_xfer_wo_dly |
- Reduce delay to fill TX fifo and read RX fifo to ensure back2back transfers
- Use long back2back transfer to ensure clock difference won't be accumulated across transactions
- Uart monitor checks the clock offset between sender and receiver is never over 1/4 of the period
|
V2 | stress_all | uart_stress_all |
- Combine above sequences in one test to run sequentially, except csr sequence and
uart_rx_oversample_vseq (requires zero_delays)
- Randomly add reset between each sequence
|
V2 | stress_all_with_reset | uart_stress_all_with_rand_reset | Have random reset in parallel with stress_all and tl_errors sequences |
V2 | alert_test | uart_alert_test | Verify common alert_test CSR that allows SW to mock-inject alert requests.
- Enable a random set of alert requests by writing random value to
alert_test CSR.
- Check each
alert_tx.alert_p pin to verify that only the requested alerts
are triggered.
- During alert_handshakes, write
alert_test CSR again to verify that:
If alert_test writes to current ongoing alert handshake, the alert_test
request will be ignored.
If alert_test writes to current idle alert handshake, a new alert_handshake
should be triggered.
- Wait for the alert handshakes to finish and verify
alert_tx.alert_p pins
all sets back to 0.
- Repeat the above steps a bunch of times.
|
V2 | intr_test | uart_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
- Enable a random set of interrupts by writing random value(s) to
intr_enable CSR(s).
- Randomly "turn on" interrupts by writing random value(s) to intr_test
CSR(s).
- Read all intr_state CSR(s) back to verify that it reflects the same value
as what was written to the corresponding intr_test CSR.
- Check the cfg.intr_vif pins to verify that only the interrupts that were
enabled and turned on are set.
- Clear a random set of interrupts by writing a randomly value to intr_state
CSR(s).
- Repeat the above steps a bunch of times.
|
V2 | tl_d_oob_addr_access | uart_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | uart_tl_errors | Drive unsupported requests via TL interface and verify correctness of response
/ behavior. Below error cases are tested bases on the
TLUL spec
- TL-UL protocol error cases
- invalid opcode
- some mask bits not set when opcode is
PutFullData
- mask does not match the transfer size, e.g.
a_address = 0x00 , a_size = 0 ,
a_mask = 'b0010
- mask and address misaligned, e.g.
a_address = 0x01 , a_mask = 'b0001
- address and size aren't aligned, e.g.
a_address = 0x01 , a_size != 0
- size is greater than 2
- OpenTitan defined error cases
- access unmapped address, expect
d_error = 1 when devmode_i == 1
- write a CSR with unaligned address, e.g.
a_address[1:0] != 0
- write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
- write a memory with
a_mask != '1 when it doesn't support partial accesses
- read a WO (write-only) memory
- write a RO (read-only) memory
- write with
instr_type = True
|
V2 | tl_d_outstanding_access | uart_csr_hw_reset
uart_csr_rw
uart_csr_aliasing
uart_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one
transaction outstanding within the TL device. Also, verify one outstanding when back-
to-back accesses are made to the same address. |
V2 | tl_d_partial_access | uart_csr_hw_reset
uart_csr_rw
uart_csr_aliasing
uart_same_csr_outstanding | Access CSR with one or more bytes of data.
For read, expect to return all word value of the CSR.
For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | uart_tl_intg_err
uart_sec_cm | Verify that the data integrity check violation generates an alert.
- Randomly inject errors on the control, data, or the ECC bits during CSR accesses.
Verify that triggers the correct fatal alert.
- Inject a fault at the onehot check in
u_reg.u_prim_reg_we_check and verify the
corresponding fatal alert occurs
|
V2S | sec_cm_bus_integrity | uart_tl_intg_err | Verify the countermeasure(s) BUS.INTEGRITY. |