Registers

Summary

ALERT_TEST

Alert Test Register

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_cnsty_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}

RESET_REQ

Software requested system reset.

• Offset: 0x4
• Reset default: 0x9
• Reset mask: 0xf

Fields

{"reg": [{"name": "VAL", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

RESET_INFO

Device reset reason.

• Offset: 0x8
• Reset default: 0x1
• Reset mask: 0xff

Fields

{"reg": [{"name": "POR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "LOW_POWER_EXIT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "SW_RESET", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "HW_REQ", "bits": 5, "attr": ["rw1c"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}

RESET_INFO . HW_REQ

Indicates when a device has reset due to a hardware requested reset. The bit mapping is as follows: b3: sysrst_ctrl_aon: OpenTitan reset request to rstmgr (running on AON clock). b4: aon_timer_aon: watchdog reset requestt b5: pwrmgr_aon: main power glitch reset request b6: alert_handler: escalation reset request b7: rv_dm: non-debug-module reset request

RESET_INFO . SW_RESET

Indicates when a device has reset due to RESET_REQ.

RESET_INFO . LOW_POWER_EXIT

Indicates when a device has reset due low power exit.

RESET_INFO . POR

Indicates when a device has reset due to power up.

ALERT_REGWEN

Alert write enable

• Offset: 0xc
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ALERT_INFO_CTRL

Alert info dump controls.

• Offset: 0x10
• Reset default: 0x0
• Reset mask: 0xf1
• Register enable: ALERT_REGWEN

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "INDEX", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ALERT_INFO_ATTR

Alert info dump attributes.

• Offset: 0x14
• Reset default: 0x0
• Reset mask: 0xf

Fields

{"reg": [{"name": "CNT_AVAIL", "bits": 4, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

ALERT_INFO

Alert dump information prior to last reset. Which value read is controlled by the ALERT_INFO_CTRL register.

• Offset: 0x18
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "VALUE", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CPU_REGWEN

Cpu write enable

• Offset: 0x1c
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CPU_INFO_CTRL

Cpu info dump controls.

• Offset: 0x20
• Reset default: 0x0
• Reset mask: 0xf1
• Register enable: CPU_REGWEN

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "INDEX", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CPU_INFO_ATTR

Cpu info dump attributes.

• Offset: 0x24
• Reset default: 0x0
• Reset mask: 0xf

Fields

{"reg": [{"name": "CNT_AVAIL", "bits": 4, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

CPU_INFO

Cpu dump information prior to last reset. Which value read is controlled by the CPU_INFO_CTRL register.

• Offset: 0x28
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "VALUE", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

SW_RST_REGWEN

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in SW_RST_CTRL_N can be changed.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

SW_RST_CTRL_N

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "VAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ERR_CODE

A bit vector of all the errors that have occurred in reset manager

• Offset: 0x6c
• Reset default: 0x0
• Reset mask: 0x7

Fields

{"reg": [{"name": "REG_INTG_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RESET_CONSISTENCY_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FSM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}