Ibex RISC-V Core Wrapper Technical Specification
| Regression | Version | Stages | Results |
|---|---|---|---|
rv_core_ibex | 3.0.0 | D1, V0 |     |
This IP has been taped out in Earl Grey 1.0.0. The corresponding documentation and regression results can be found here.
rv_core_ibex is currently under active development as CHERIoT support is added, the bitmanip extension is upgraded to the ratified version, and the Zc* compressed ISA extensions are included. This is indicated by the development stages (see
rv_core_ibex.hjsonand here). As of this the documentation can slightly differ from the current RTL implementation. The documentation for the rv_core_ibex version with design stage D2S and verification stage V2S (v2.1.0) can be found under the Earl Grey v1.0.0 documentation here.
Overview
This document specifies Ibex CPU core wrapper functionality.
Features
- Instantiation of a Ibex RV32 CPU Core.
- TileLink Uncached Light (TL-UL) host interfaces for the instruction and data ports.
- Simple address translation.
- NMI support for security alert events for watchdog bark.
- General error status collection and alert generation.
- Crash dump collection for software debug.
- Write-once switch between the ePMP and CHERIoT execution modes.
Description
The Ibex RISC-V Core Wrapper instantiates an Ibex RV32 CPU Core, and wraps its data and instruction memory interfaces to TileLink Uncached Light (TL-UL).
All configuration parameters of Ibex are passed through, except for the TRVK ports (signals starting with trvk_), which are not yet exposed.
BaseIsa is not exposed: it is fixed to the CHERIoT-capable base ISA, and the wrapper holds the execution mode switch that selects between ePMP and CHERIoT mode at runtime.
The pipelining of the bus adapters is configurable.
Compatibility
Ibex is a compliant RV32 RISC-V CPU core, as documented in the Ibex documentation.
The TL-UL bus interfaces exposed by this wrapper block are compliant to the TileLink Uncached Lite Specification version 1.7.1.