Registers

Summary

INTR_STATE

Interrupt State Register

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "io_status_change", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "init_status_change", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

INTR_ENABLE

Interrupt Enable Register

• Offset: 0x4
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "io_status_change", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "init_status_change", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

INTR_TEST

Interrupt Test Register

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "io_status_change", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "init_status_change", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

ALERT_TEST

Alert Test Register

• Offset: 0xc
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "recov_alert", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_alert", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

CFG_REGWEN

Controls the configurability of FATAL_ALERT_EN register.

• Offset: 0x10
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ALERT_TRIG

Alert trigger test

• Offset: 0x14
• Reset default: 0x0
• Reset mask: 0x7ff

Fields

{"reg": [{"name": "VAL_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ALERT_EN

Each multibit value enables a corresponding alert.

• Reset default: 0x6
• Reset mask: 0xf

Instances

Fields

{"reg": [{"name": "VAL", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ALERT_EN . VAL

kMultiBitBool4True - An alert event is enabled. kMultiBitBool4False - An alert event is disabled.

At reset, all alerts are enabled. This is by design so that no alerts get missed unless they get disabled explicitly. Firmware can disable alerts that may be problematic for the designated use case.

FATAL_ALERT_EN

Each bit marks a corresponding alert as fatal or recoverable.

Note that alerts are ignored if they are not enabled in ALERT_EN.

• Offset: 0x44
• Reset default: 0x0
• Reset mask: 0x7ff
• Register enable: CFG_REGWEN

Fields

{"reg": [{"name": "VAL_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "VAL_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

FATAL_ALERT_EN . VAL_10

1 - An alert event is fatal. 0 - An alert event is recoverable.

At reset, all alerts are recoverable. This is by design so that a false-positive alert event early in the reset sequence doesn’t jam the alert until the next reset. Firmware can define alerts that are critical for the designated use case as fatal.

FATAL_ALERT_EN . VAL_9

1 - An alert event is fatal. 0 - An alert event is recoverable.

At reset, all alerts are recoverable. This is by design so that a false-positive alert event early in the reset sequence doesn’t jam the alert until the next reset. Firmware can define alerts that are critical for the designated use case as fatal.

FATAL_ALERT_EN . VAL_8

1 - An alert event is fatal. 0 - An alert event is recoverable.

At reset, all alerts are recoverable. This is by design so that a false-positive alert event early in the reset sequence doesn’t jam the alert until the next reset. Firmware can define alerts that are critical for the designated use case as fatal.

FATAL_ALERT_EN . VAL_7

1 - An alert event is fatal. 0 - An alert event is recoverable.

At reset, all alerts are recoverable. This is by design so that a false-positive alert event early in the reset sequence doesn’t jam the alert until the next reset. Firmware can define alerts that are critical for the designated use case as fatal.

FATAL_ALERT_EN . VAL_6

1 - An alert event is fatal. 0 - An alert event is recoverable.

At reset, all alerts are recoverable. This is by design so that a false-positive alert event early in the reset sequence doesn’t jam the alert until the next reset. Firmware can define alerts that are critical for the designated use case as fatal.

FATAL_ALERT_EN . VAL_5

1 - An alert event is fatal. 0 - An alert event is recoverable.

At reset, all alerts are recoverable. This is by design so that a false-positive alert event early in the reset sequence doesn’t jam the alert until the next reset. Firmware can define alerts that are critical for the designated use case as fatal.

FATAL_ALERT_EN . VAL_4

1 - An alert event is fatal. 0 - An alert event is recoverable.

At reset, all alerts are recoverable. This is by design so that a false-positive alert event early in the reset sequence doesn’t jam the alert until the next reset. Firmware can define alerts that are critical for the designated use case as fatal.

FATAL_ALERT_EN . VAL_3

1 - An alert event is fatal. 0 - An alert event is recoverable.

At reset, all alerts are recoverable. This is by design so that a false-positive alert event early in the reset sequence doesn’t jam the alert until the next reset. Firmware can define alerts that are critical for the designated use case as fatal.

FATAL_ALERT_EN . VAL_2

1 - An alert event is fatal. 0 - An alert event is recoverable.

At reset, all alerts are recoverable. This is by design so that a false-positive alert event early in the reset sequence doesn’t jam the alert until the next reset. Firmware can define alerts that are critical for the designated use case as fatal.

FATAL_ALERT_EN . VAL_1

1 - An alert event is fatal. 0 - An alert event is recoverable.

At reset, all alerts are recoverable. This is by design so that a false-positive alert event early in the reset sequence doesn’t jam the alert until the next reset. Firmware can define alerts that are critical for the designated use case as fatal.

FATAL_ALERT_EN . VAL_0

1 - An alert event is fatal. 0 - An alert event is recoverable.

At reset, all alerts are recoverable. This is by design so that a false-positive alert event early in the reset sequence doesn’t jam the alert until the next reset. Firmware can define alerts that are critical for the designated use case as fatal.

RECOV_ALERT

Each bit represents a recoverable alert that has been triggered by AST. Since these are recoverable alerts, they can be cleared by software.

• Offset: 0x48
• Reset default: 0x0
• Reset mask: 0x7ff

Fields

{"reg": [{"name": "VAL_0", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "VAL_1", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "VAL_2", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "VAL_3", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "VAL_4", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "VAL_5", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "VAL_6", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "VAL_7", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "VAL_8", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "VAL_9", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "VAL_10", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

FATAL_ALERT

Each bit represents a fatal alert that has been triggered by AST. Since these registers represent fatal alerts, they cannot be cleared.

The lower bits are used for ast alert events. The upper bits are used for local events.

• Offset: 0x4c
• Reset default: 0x0
• Reset mask: 0xfff

Fields

{"reg": [{"name": "VAL_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_8", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_9", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_10", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_11", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

STATUS

Status readback for ast

• Offset: 0x50
• Reset default: 0x0
• Reset mask: 0x7

Fields

{"reg": [{"name": "ast_init_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "io_pok", "bits": 2, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

MANUAL_PAD_ATTR_REGWEN

Register write enable for attributes of manual pads

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

MANUAL_PAD_ATTR

Attributes of manual pads. This register has WARL behavior since not every pad may support each attribute. The mapping of registers to pads is as follows (only supported for targets that instantiate chip_earlgrey_asic):

• MANUAL_PAD_ATTR_0: CC1
• MANUAL_PAD_ATTR_1: CC2
• MANUAL_PAD_ATTR_2: FLASH_TEST_MODE0
• MANUAL_PAD_ATTR_3: FLASH_TEST_MODE1
• Reset default: 0x0
• Reset mask: 0x8c

Instances

Fields

{"reg": [{"bits": 2}, {"name": "pull_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pull_select", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "input_disable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

MANUAL_PAD_ATTR . input_disable

Disable input drivers. Setting this to 1 for pads that are not used as input can reduce their leakage current.

MANUAL_PAD_ATTR . pull_select

Pull select (0: pull-down, 1: pull-up).

MANUAL_PAD_ATTR . pull_en

Enable pull-up or pull-down resistor.