Name | Offset | Length | Description |
pattgen.INTR_STATE | 0x0 | 4 | Interrupt State Register |
pattgen.INTR_ENABLE | 0x4 | 4 | Interrupt Enable Register |
pattgen.INTR_TEST | 0x8 | 4 | Interrupt Test Register |
pattgen.ALERT_TEST | 0xc | 4 | Alert Test Register |
pattgen.CTRL | 0x10 | 4 | PATTGEN control register |
pattgen.PREDIV_CH0 | 0x14 | 4 | PATTGEN pre-divider register for Channel 0 |
pattgen.PREDIV_CH1 | 0x18 | 4 | PATTGEN pre-divider register for Channel 1 |
pattgen.DATA_CH0_0 | 0x1c | 4 | PATTGEN seed pattern multi-registers for Channel 0. |
pattgen.DATA_CH0_1 | 0x20 | 4 | PATTGEN seed pattern multi-registers for Channel 0. |
pattgen.DATA_CH1_0 | 0x24 | 4 | PATTGEN seed pattern multi-registers for Channel 1. |
pattgen.DATA_CH1_1 | 0x28 | 4 | PATTGEN seed pattern multi-registers for Channel 1. |
pattgen.SIZE | 0x2c | 4 | PATTGEN pattern length |
Interrupt State Register
- Offset:
0x0
- Reset default:
0x0
- Reset mask:
0x3
Bits | Type | Reset | Name | Description |
31:2 | | | | Reserved |
1 | rw1c | 0x0 | done_ch1 | raise if pattern generation on Channel 1 is complete |
0 | rw1c | 0x0 | done_ch0 | raise if pattern generation on Channel 0 is complete |
Interrupt Enable Register
- Offset:
0x4
- Reset default:
0x0
- Reset mask:
0x3
Interrupt Test Register
- Offset:
0x8
- Reset default:
0x0
- Reset mask:
0x3
Alert Test Register
- Offset:
0xc
- Reset default:
0x0
- Reset mask:
0x1
Bits | Type | Reset | Name | Description |
31:1 | | | | Reserved |
0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. |
PATTGEN control register
- Offset:
0x10
- Reset default:
0x0
- Reset mask:
0xf
Bits | Type | Reset | Name | Description |
31:4 | | | | Reserved |
3 | rw | 0x0 | POLARITY_CH1 | Clock (pcl ) polarity for Channel 1. If low, pda signal changes on falling edge of pcl signal, otherwise pda changes on rising edge. Note that writes to a channel’s configuration registers have no effect while the channel is enabled. |
2 | rw | 0x0 | POLARITY_CH0 | Clock (pcl ) polarity for Channel 0. If low, pda signal changes on falling edge of pcl signal, otherwise pda changes on rising edge. Note that writes to a channel’s configuration registers have no effect while the channel is enabled. |
1 | rw | 0x0 | ENABLE_CH1 | Enable pattern generator functionality for Channel 1 |
0 | rw | 0x0 | ENABLE_CH0 | Enable pattern generator functionality for Channel 0 |
PATTGEN pre-divider register for Channel 0
- Offset:
0x14
- Reset default:
0x0
- Reset mask:
0xffffffff
Bits | Type | Reset | Name | Description |
31:0 | rw | 0x0 | CLK_RATIO | Clock divider ratio fpr Channel 0 (relative to I/O clock). Note that writes to a channel’s configuration registers have no effect while the channel is enabled. |
PATTGEN pre-divider register for Channel 1
- Offset:
0x18
- Reset default:
0x0
- Reset mask:
0xffffffff
Bits | Type | Reset | Name | Description |
31:0 | rw | 0x0 | CLK_RATIO | Clock divider ratio for Channel 1 (relative to I/O clock). Note that writes to a channel’s configuration registers have no effect while the channel is enabled. |
PATTGEN seed pattern multi-registers for Channel 0.
- Reset default:
0x0
- Reset mask:
0xffffffff
Name | Offset |
DATA_CH0_0 | 0x1c |
DATA_CH0_1 | 0x20 |
Bits | Type | Reset | Name | Description |
31:0 | rw | 0x0 | DATA | Seed pattern for Channel 0 (1-64 bits). Note that writes to a channel’s configuration registers have no effect while the channel is enabled. |
PATTGEN seed pattern multi-registers for Channel 1.
- Reset default:
0x0
- Reset mask:
0xffffffff
Name | Offset |
DATA_CH1_0 | 0x24 |
DATA_CH1_1 | 0x28 |
Bits | Type | Reset | Name | Description |
31:0 | rw | 0x0 | DATA | Seed pattern for Channel 1 (1-64 bits). Note that writes to a channel’s configuration registers have no effect while the channel is enabled. |
PATTGEN pattern length
- Offset:
0x2c
- Reset default:
0x0
- Reset mask:
0xffffffff
Bits | Type | Reset | Name | Description |
31:22 | rw | 0x0 | REPS_CH1 | Number of pattern repetitions for Channel 1, minus 1. Valid values: 0..1023. Note that writes to a channel’s configuration registers have no effect while the channel is enabled. |
21:16 | rw | 0x0 | LEN_CH1 | Length of the seed pattern for Channel 1, minus 1. Valid values: 0..63. Note that writes to a channel’s configuration registers have no effect while the channel is enabled. |
15:6 | rw | 0x0 | REPS_CH0 | Number of pattern repetitions for Channel 0, minus 1. Valid values: 0..1023. Note that writes to a channel’s configuration registers have no effect while the channel is enabled. |
5:0 | rw | 0x0 | LEN_CH0 | Length of the seed pattern for Channel 0, minus 1. Valid values: 0..63. Note that writes to a channel’s configuration registers have no effect while the channel is enabled. |